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Searched refs:csneg (Results 1 – 25 of 30) sorted by relevance

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/external/libhevc/common/arm64/
Dihevc_deblk_luma_horz.s137 csneg x9,x9,x9,pl
142 csneg x8,x8,x8,pl // dp0 value is stored in x8
166 csneg x12,x12,x12,pl
172 csneg x11,x11,x11,pl // dp3 value is stored in x8
228 csneg x2,x2,x2,pl
231 csneg x8,x8,x8,pl
240 csneg x7,x7,x7,pl
284 csneg x8,x8,x8,pl
288 csneg x2,x2,x2,pl
298 csneg x7,x7,x7,pl
Dihevc_deblk_luma_vert.s130 csneg x9,x9,x9,pl
140 csneg x8,x8,x8,pl
165 csneg x12,x12,x12,pl
171 csneg x11,x11,x11,pl // dp3 value is stored in x8
226 csneg x8,x8,x8,pl
229 csneg x2,x2,x2,pl
239 csneg x7,x7,x7,pl
279 csneg x8,x8,x8,pl
283 csneg x2,x2,x2,pl
292 csneg x7,x7,x7,pl
/external/llvm/test/CodeGen/AArch64/
Dcond-sel.ll175 ; CHECK: csneg {{w[0-9]+}}, [[LHS]], [[RHS]], ls
183 ; CHECK: csneg {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
192 ; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
200 ; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
Darm64-csel.ll83 ; CHECK-next: csneg
159 ; CHECK: csneg w0, w1, w2, ne
170 ; CHECK: csneg x0, x1, x2, ne
Darm64-early-ifcvt.ll186 ; CHECK-NEXT: csneg w0, w1, w0, eq
204 ; CHECK-NEXT: csneg x0, x1, x0, eq
222 ; CHECK-NEXT: csneg w0, w1, w0, ne
240 ; CHECK-NEXT: csneg x0, x1, x0, ne
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs524 0x01,0x14,0x93,0x5a = csneg w1, w0, w19, ne
525 0xbf,0x04,0x89,0x5a = csneg wzr, w5, w9, eq
526 0xe9,0xc7,0x9e,0x5a = csneg w9, wzr, w30, gt
527 0x81,0x47,0x9f,0x5a = csneg w1, w28, wzr, mi
528 0xf3,0xb6,0x9d,0xda = csneg x19, x23, x29, lt
529 0x7f,0xa4,0x84,0xda = csneg xzr, x3, x4, ge
530 0xe5,0x27,0x86,0xda = csneg x5, xzr, x6, hs
531 0x07,0x35,0x9f,0xda = csneg x7, x8, xzr, lo
/external/llvm/test/MC/AArch64/
Dbasic-a64-instructions.s1383 csneg w1, w0, w19, ne
1384 csneg wzr, w5, w9, eq
1385 csneg w9, wzr, w30, gt
1386 csneg w1, w28, wzr, mi
1392 csneg x19, x23, x29, lt
1393 csneg xzr, x3, x4, ge
1394 csneg x5, xzr, x6, cs
1395 csneg x7, x8, xzr, cc
Darm64-arithmetic-encoding.s556 csneg w1, w2, w3, eq
557 csneg x1, x2, x3, eq
Dbasic-a64-diagnostics.s1375 csneg w20, w21, wsp, mi
1376 csneg x0, sp, x29, le
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-arithmetic.txt524 # CHECK: csneg w1, w2, w3, eq
526 # CHECK: csneg x1, x2, x3, eq
Dbasic-a64-instructions.txt928 # CHECK: csneg w1, w0, w19, ne
929 # CHECK: csneg wzr, w5, w9, eq
930 # CHECK: csneg w9, wzr, w30, gt
931 # CHECK: csneg w1, w28, wzr, mi
932 # CHECK: csneg x19, x23, x29, lt
933 # CHECK: csneg xzr, x3, x4, ge
934 # CHECK: csneg x5, xzr, x6, hs
935 # CHECK: csneg x7, x8, xzr, lo
1002 # CHECK: csneg x4, x8, x8, al
/external/vixl/test/aarch64/
Dtest-disasm-aarch64.cc2191 COMPARE(csneg(w18, w19, w20, vs), "csneg w18, w19, w20, vs"); in TEST()
2192 COMPARE(csneg(x21, x22, x23, vc), "csneg x21, x22, x23, vc"); in TEST()
2210 COMPARE(csneg(x6, x7, x8, al), "csneg x6, x7, x8, al"); in TEST()
2211 COMPARE(csneg(x7, x8, x9, nv), "csneg x7, x8, x9, nv"); in TEST()
Dtest-trace-aarch64.cc138 __ csneg(w7, w8, w9, hi); in GenerateTestSequenceBase() local
139 __ csneg(w7, w8, w9, ls); in GenerateTestSequenceBase() local
140 __ csneg(x10, x11, x12, eq); in GenerateTestSequenceBase() local
141 __ csneg(x10, x11, x12, ne); in GenerateTestSequenceBase() local
Dtest-cpu-features-aarch64.cc260 TEST_NONE(csneg_0, csneg(w0, w1, w2, ge))
261 TEST_NONE(csneg_1, csneg(x0, x1, x2, cc))
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour82 0x~~~~~~~~~~~~~~~~ 5a898507 csneg w7, w8, w9, hi
83 0x~~~~~~~~~~~~~~~~ 5a899507 csneg w7, w8, w9, ls
84 0x~~~~~~~~~~~~~~~~ da8c056a csneg x10, x11, x12, eq
85 0x~~~~~~~~~~~~~~~~ da8c156a csneg x10, x11, x12, ne
Dlog-disasm82 0x~~~~~~~~~~~~~~~~ 5a898507 csneg w7, w8, w9, hi
83 0x~~~~~~~~~~~~~~~~ 5a899507 csneg w7, w8, w9, ls
84 0x~~~~~~~~~~~~~~~~ da8c056a csneg x10, x11, x12, eq
85 0x~~~~~~~~~~~~~~~~ da8c156a csneg x10, x11, x12, ne
Dlog-cpufeatures-custom82 0x~~~~~~~~~~~~~~~~ 5a898507 csneg w7, w8, w9, hi
83 0x~~~~~~~~~~~~~~~~ 5a899507 csneg w7, w8, w9, ls
84 0x~~~~~~~~~~~~~~~~ da8c056a csneg x10, x11, x12, eq
85 0x~~~~~~~~~~~~~~~~ da8c156a csneg x10, x11, x12, ne
Dlog-cpufeatures82 0x~~~~~~~~~~~~~~~~ 5a898507 csneg w7, w8, w9, hi
83 0x~~~~~~~~~~~~~~~~ 5a899507 csneg w7, w8, w9, ls
84 0x~~~~~~~~~~~~~~~~ da8c056a csneg x10, x11, x12, eq
85 0x~~~~~~~~~~~~~~~~ da8c156a csneg x10, x11, x12, ne
Dlog-cpufeatures-colour82 0x~~~~~~~~~~~~~~~~ 5a898507 csneg w7, w8, w9, hi
83 0x~~~~~~~~~~~~~~~~ 5a899507 csneg w7, w8, w9, ls
84 0x~~~~~~~~~~~~~~~~ da8c056a csneg x10, x11, x12, eq
85 0x~~~~~~~~~~~~~~~~ da8c156a csneg x10, x11, x12, ne
Dlog-all447 0x~~~~~~~~~~~~~~~~ 5a898507 csneg w7, w8, w9, hi
449 0x~~~~~~~~~~~~~~~~ 5a899507 csneg w7, w8, w9, ls
451 0x~~~~~~~~~~~~~~~~ da8c056a csneg x10, x11, x12, eq
453 0x~~~~~~~~~~~~~~~~ da8c156a csneg x10, x11, x12, ne
/external/vixl/src/aarch64/
Dassembler-aarch64.cc748 void Assembler::csneg(const Register& rd, in csneg() function in vixl::aarch64::Assembler
784 csneg(rd, rn, rn, InvertCondition(cond)); in cneg()
Dassembler-aarch64.h897 void csneg(const Register& rd,
Dmacro-assembler-aarch64.h1383 csneg(rd, rn, rm, cond); in Csneg()
/external/capstone/arch/AArch64/
DAArch64MappingInsnOp.inc929 { /* AArch64_CSNEGWr, ARM64_INS_CSNEG: csneg $rd, $rn, $rm, $cond */
933 { /* AArch64_CSNEGXr, ARM64_INS_CSNEG: csneg $rd, $rn, $rm, $cond */
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td5402 def t2CSNEG : CS<"csneg", 0b1011>;

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