Searched refs:ds_add_rtn_u64 (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | local-atomics64.ll | 24 ; GCN: ds_add_rtn_u64
38 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
51 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
61 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
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| /external/llvm/test/MC/AMDGPU/ |
| D | ds.s | 365 ds_add_rtn_u64 v[8:9], v2, v[4:5] label
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| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | ds_vi.txt | 258 # VI: ds_add_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xc0,0xd8,0x02,0x04,0x00,0x08]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | DSInstructions.td | 468 defm DS_ADD_RTN_U64 : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 866 defm DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "ds_add_rtn_u64", VReg_64, "ds_add_u64">;
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_instruction_selection.cpp | 6727 op64_rtn = aco_opcode::ds_add_rtn_u64; in visit_shared_atomic()
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