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Searched refs:opc2 (Results 1 – 25 of 25) sorted by relevance

/external/arm-trusted-firmware/include/arch/aarch32/
Darch_helpers.h22 #define _DEFINE_COPROCR_WRITE_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \ argument
25 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
28 #define _DEFINE_COPROCR_READ_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \ argument
32 __asm__ volatile ("mrc "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : "=r" (v));\
109 #define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ argument
113 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
116 #define _DEFINE_BPIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ argument
120 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
123 #define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ argument
126 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
[all …]
Dasm_macros.S32 .macro ldcopr reg, coproc, opc1, CRn, CRm, opc2 argument
33 mrc \coproc, \opc1, \reg, \CRn, \CRm, \opc2
40 .macro stcopr reg, coproc, opc1, CRn, CRm, opc2 argument
41 mcr \coproc, \opc1, \reg, \CRn, \CRm, \opc2
/external/llvm/test/TableGen/
DBitsInit.td7 bits<2> opc2 = { 1, 0 };
9 bits<2> a = { opc, opc2 }; // error!
10 bits<2> b = { opc{0}, opc2{0} };
11 bits<2> c = { opc{1}, opc2{1} };
17 // CHECK: bits<2> opc2 = { 1, 0 };
/external/arm-trusted-firmware/lib/aarch32/
Dcache_helpers.S22 .macro do_dcache_maintenance_by_mva op, coproc, opc1, CRn, CRm, opc2 argument
31 stcopr r0, \coproc, \opc1, \CRn, \CRm, \opc2
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td221 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
225 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
230 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
233 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
237 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
242 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
258 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
263 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
269 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
274 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreInstrInfo.td213 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
217 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
222 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
225 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
229 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
234 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
250 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
255 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
261 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
266 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_emit_gk110.cpp48 void emitForm_21(const Instruction *, uint32_t opc2, uint32_t opc1);
425 CodeEmitterGK110::emitForm_21(const Instruction *i, uint32_t opc2, in emitForm_21() argument
439 code[1] = (0xc << 28) | (opc2 << 20); in emitForm_21()
1848 uint64_t opc1, opc2; in emitSUCalc() local
1857 case OP_SUCLAMP: opc1 = 0xb00; opc2 = 0x580; break; in emitSUCalc()
1858 case OP_SUBFM: opc1 = 0xb68; opc2 = 0x1e8; break; in emitSUCalc()
1859 case OP_SUEAU: opc1 = 0xb6c; opc2 = 0x1ec; break; in emitSUCalc()
1864 emitForm_21(i, opc2, opc1); in emitSUCalc()
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td4151 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4160 bits<3> opc2;
4167 let Inst{7-5} = opc2;
4196 c_imm:$CRm, imm0_7:$opc2),
4198 imm:$CRm, imm:$opc2)]>,
4205 c_imm:$CRm, imm0_7:$opc2),
4207 imm:$CRm, imm:$opc2)]> {
4217 c_imm:$CRm, imm0_7:$opc2), []>;
4224 c_imm:$CRm, imm0_7:$opc2), []> {
4231 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
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DARMInstrInfo.td4813 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4814 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4816 imm:$CRm, imm:$opc2)]>,
4822 bits<3> opc2;
4827 let Inst{7-5} = opc2;
4835 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4836 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4838 imm:$CRm, imm:$opc2)]>,
4845 bits<3> opc2;
4850 let Inst{7-5} = opc2;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrInfo.td5158 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5159 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5161 timm:$CRm, timm:$opc2)]>,
5167 bits<3> opc2;
5172 let Inst{7-5} = opc2;
5182 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5183 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5185 timm:$CRm, timm:$opc2)]>,
5192 bits<3> opc2;
5197 let Inst{7-5} = opc2;
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DARMInstrThumb2.td4385 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4394 bits<3> opc2;
4401 let Inst{7-5} = opc2;
4434 c_imm:$CRm, imm0_7:$opc2),
4436 timm:$CRm, timm:$opc2)]>,
4443 c_imm:$CRm, imm0_7:$opc2),
4445 timm:$CRm, timm:$opc2)]> {
4455 c_imm:$CRm, imm0_7:$opc2), []>;
4462 c_imm:$CRm, imm0_7:$opc2), []> {
4469 def : T2v6Pat<(int_arm_mrc timm:$cop, timm:$opc1, timm:$CRn, timm:$CRm, timm:$opc2),
[all …]
/external/llvm/lib/Target/X86/
DX86InstrMMX.td113 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
127 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
DX86InstrAVX512.td2411 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2419 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2421 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
DX86InstrSSE.td3903 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3925 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrMMX.td51 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
66 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
DX86InstrSSE.td3506 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3529 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3538 multiclass PDI_binop_rmi_all<bits<8> opc, bits<8> opc2, Format ImmForm,
3545 defm V#NAME : PDI_binop_rmi<opc, opc2, ImmForm, !strconcat("v", OpcodeStr),
3549 defm V#NAME#Y : PDI_binop_rmi<opc, opc2, ImmForm, !strconcat("v", OpcodeStr),
3554 defm NAME : PDI_binop_rmi<opc, opc2, ImmForm, OpcodeStr, OpNode, OpNode2,
DX86InstrAVX512.td3115 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
3123 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode,
3125 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode,
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc106 { /* ARM_CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */
109 { /* ARM_CDP2, ARM_INS_CDP2: cdp2 $cop, $opc1, $crd, $crn, $crm, $opc2 */
442 { /* ARM_MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */
445 { /* ARM_MCR2, ARM_INS_MCR2: mcr2 $cop, $opc1, $rt, $crn, $crm, $opc2 */
484 { /* ARM_MRC, ARM_INS_MRC: mrc${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */
487 { /* ARM_MRC2, ARM_INS_MRC2: mrc2 $cop, $opc1, $rt, $crn, $crm, $opc2 */
5392 { /* ARM_t2CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */
5395 { /* ARM_t2CDP2, ARM_INS_CDP2: cdp2${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */
5707 { /* ARM_t2MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */
5710 { /* ARM_t2MCR2, ARM_INS_MCR2: mcr2${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */
[all …]
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc106 { /* ARM_CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */
109 { /* ARM_CDP2, ARM_INS_CDP2: cdp2 $cop, $opc1, $crd, $crn, $crm, $opc2 */
442 { /* ARM_MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */
445 { /* ARM_MCR2, ARM_INS_MCR2: mcr2 $cop, $opc1, $rt, $crn, $crm, $opc2 */
484 { /* ARM_MRC, ARM_INS_MRC: mrc${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */
487 { /* ARM_MRC2, ARM_INS_MRC2: mrc2 $cop, $opc1, $rt, $crn, $crm, $opc2 */
5392 { /* ARM_t2CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */
5395 { /* ARM_t2CDP2, ARM_INS_CDP2: cdp2${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */
5707 { /* ARM_t2MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */
5710 { /* ARM_t2MCR2, ARM_INS_MCR2: mcr2${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td5116 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
5120 "$Rx "#opc2#opc1#"($Rs, #$u5)",
5146 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
5150 "$Rx "#opc2#opc1#"($Rs, $Rt)",
5173 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
5177 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
5203 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
5207 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td4186 class BaseMemTag<bits<2> opc1, bits<2> opc2, string asm_insn,
4196 let Inst{11-10} = opc2;
4226 class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn,
4228 : BaseMemTag<opc1, opc2, asm_insn, asm_opnds, cstr, oops, iops> {
10316 bit opc1, bit opc2, RegisterOperand dst_reg,
10344 let Inst{12} = opc2;
10354 multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype,
10357 def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64,
10365 def v8f16_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b01, opc1, opc2,
10375 def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2,
DSVEInstrFormats.td2007 class sve_int_read_vl_a<bit op, bits<5> opc2, string asm>
2017 let Inst{20-16} = opc2{4-0};
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc31006 // MIs[0] opc2
31008 …opc2) => (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:…
31015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
31037 // MIs[0] opc2
31039 …opc2) => (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm…
31046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
31066 // MIs[0] opc2
31068 …opc2) => (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (tim…
31075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
31097 // MIs[0] opc2
[all …]
DARMGenMCCodeEmitter.inc7682 // op: opc2
7901 // op: opc2
12664 // op: opc2
15730 // op: opc2
15835 // op: opc2
15877 // op: opc2
DARMGenDAGISel.inc31090 /* 66532*/ OPC_RecordChild7, // #6 = $opc2
31101 …$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) - Complexity = 26
31102 …timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
31110 …$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) - Complexity = 26
31111 …timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
31135 /* 66620*/ OPC_RecordChild7, // #6 = $opc2
31144 …$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) - Complexity = 26
31145 …timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
31153 …$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) - Complexity = 26
31154 …timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
[all …]