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Searched refs:sse4a (Results 1 – 25 of 33) sorted by relevance

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/external/llvm/test/Transforms/InstCombine/
Dx86-sse4a.ll10 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %…
13 %1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %y) nounwind
21 %1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> zeroinitializer, <16 x i8> %y) nounwind
29 %1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> zeroinitializer) nounwind
35 ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 8, i8 15)
38 …%1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> <i8 8, i8 15, i8 0, i8 0, i…
46 …%1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> <i64 -1, i64 55>, <16 x i8> <i8 8, i8 15,…
54 …%1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> <i64 -1, i64 undef>, <16 x i8> <i8 16, i8…
64 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 8, i8 2…
67 %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 8, i8 23)
[all …]
/external/llvm/test/CodeGen/X86/
Dsse4a.ll2 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X32
3 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X32
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X64
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X64
17 %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2)
21 declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind
34 %2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind
38 declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind
50 %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6)
54 declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
[all …]
Dsse4a-intrinsics-fast-isel.ll2 ; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefi…
3 ; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-…
4 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-pre…
5 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --chec…
7 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse4a-builtins.c
19 %res = call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2)
22 declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind readnone
35 %res = call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %bc)
38 declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind readnone
50 %res = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6)
[all …]
Dsse4a-upgrade.ll2 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X32
3 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X32
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X64
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X64
18 tail call void @llvm.x86.sse4a.movnt.ss(i8* %p, <4 x float> %a) nounwind
22 declare void @llvm.x86.sse4a.movnt.ss(i8*, <4 x float>)
35 tail call void @llvm.x86.sse4a.movnt.sd(i8* %p, <2 x double> %a) nounwind
39 declare void @llvm.x86.sse4a.movnt.sd(i8*, <2 x double>)
Dvector-shuffle-sse4a.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3,+sse4a | FileCheck %s --check-prefix=…
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+sse4a | FileCheck %s --check-prefix=AL…
15 %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %a, i8 0, i8 0)
24 %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %a, i8 8, i8 16)
34 %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %a, i8 32, i8 48)
196 %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %a, <2 x i64> %b, i8 0, i8 0)
205 %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %a, <2 x i64> %b, i8 8, i8 16)
215 %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %a, <2 x i64> %b, i8 32, i8 48)
360 declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind
361 declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
Dslow-unaligned-mem.ll61 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse4a 2>&1 | FileCheck %s --check-prefi…
Dfast-isel-nontemporal.ll3 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+sse4a -fast-isel -O0 < %s …
Dnontemporal-2.ll3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=SSE --c…
/external/cpu_features/include/
Dcpuinfo_x86.h60 int sse4a : 1; member
/external/marisa-trie/
Dconfigure.ac155 AC_ARG_ENABLE([sse4a], optenable
156 [AS_HELP_STRING([--enable-sse4a],
/external/clang/lib/Headers/
Dmodule.modulemap110 explicit module sse4a {
/external/cpuinfo/include/
Dcpuinfo.h721 bool sse4a; member
1048 return cpuinfo_isa.sse4a; in cpuinfo_has_x86_sse4a()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DX86TargetParser.def139 X86_FEATURE_COMPAT(11, FEATURE_SSE4_A, "sse4a")
/external/cpuinfo/src/x86/
Disa.c353 isa.sse4a = !!(extended_info.ecx & UINT32_C(0x00000040)); in cpuinfo_x86_detect_isa()
/external/clang/include/clang/Basic/
DBuiltinsX86.def413 TARGET_BUILTIN(__builtin_ia32_extrqi, "V2LLiV2LLiIcIc", "", "sse4a")
414 TARGET_BUILTIN(__builtin_ia32_extrq, "V2LLiV2LLiV16c", "", "sse4a")
415 TARGET_BUILTIN(__builtin_ia32_insertqi, "V2LLiV2LLiV2LLiIcIc", "", "sse4a")
416 TARGET_BUILTIN(__builtin_ia32_insertq, "V2LLiV2LLiV2LLi", "", "sse4a")
417 TARGET_BUILTIN(__builtin_ia32_movntsd, "vd*V2d", "", "sse4a")
418 TARGET_BUILTIN(__builtin_ia32_movntss, "vf*V4f", "", "sse4a")
/external/cpuinfo/test/mock/
Dmemo-pad-7.cc353 TEST(ISA, sse4a) { in TEST() argument
Dzenfone-2e.cc353 TEST(ISA, sse4a) { in TEST() argument
Dzenfone-c.cc353 TEST(ISA, sse4a) { in TEST() argument
Dzenfone-2.cc353 TEST(ISA, sse4a) { in TEST() argument
Dalldocube-iwork8.cc353 TEST(ISA, sse4a) { in TEST() argument
Dleagoo-t5c.cc353 TEST(ISA, sse4a) { in TEST() argument
/external/cpu_features/src/
Dimpl_x86__base_implementation.inl377 // sse4a (See ParseExtraAMDCpuId below).
389 features->sse4a = IsBitSet(leaf_80000001.ecx, 6);
1711 LINE(X86_SSE4A, sse4a, , , ) \
/external/llvm/lib/Target/X86/
DX86.td109 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86.td114 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
/external/clang/include/clang/Driver/
DOptions.td1441 def mno_sse4a : Flag<["-"], "mno-sse4a">, Group<m_x86_Features_Group>;

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