| /external/arm-trusted-firmware/drivers/renesas/common/scif/ |
| D | scif.S | 186 strh w1, [x0, #SCIF_SCSCR]
190 strh w1, [x0, #SCIF_SCFCR]
196 strh w1, [x0, #SCIF_SCFSR]
198 strh w1, [x0, #SCIF_SCLSR]
204 strh w1, [x0, #SCIF_SCSCR]
207 strh w1, [x0, #SCIF_SCSMR]
258 strh w1, [x0, #SCIF_DL]
260 strh w1, [x0, #SCIF_CKS]
272 strh w1, [x0, #SCIF_SCFCR]
276 strh w1, [x0, #SCIF_SCSCR]
[all …]
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-strh.ll | 5 ; CHECK: strh r0, [r1]
12 ; CHECK: strh.w r0, [r1, #4092]
20 ; CHECK: strh r0, [r1, #-128]
29 ; CHECK: strh r0, [r1, r2]
38 ; CHECK: strh r0, [r1, #-128]
48 ; CHECK: strh r0, [r1, r2]
58 ; CHECK: strh.w r0, [r1, r2, lsl #2]
70 ; CHECK: strh r0, [r1, r2]
|
| /external/capstone/suite/MC/ARM/ |
| D | arm-memory-instructions.s.cs | 126 0xb0,0x30,0xc4,0xe1 = strh r3, [r4]
127 0xb4,0x20,0xc7,0xe1 = strh r2, [r7, #4]
128 0xb0,0x14,0xe8,0xe1 = strh r1, [r8, #64]!
129 0xb4,0xc0,0xcd,0xe0 = strh r12, [sp], #4
130 0xb4,0x60,0x85,0xe1 = strh r6, [r5, r4]
131 0xbb,0x30,0xa8,0xe1 = strh r3, [r8, r11]!
132 0xb1,0x10,0x22,0xe1 = strh r1, [r2, -r1]!
133 0xb2,0x90,0x87,0xe0 = strh r9, [r7], r2
134 0xb2,0x40,0x03,0xe0 = strh r4, [r3], -r2
|
| D | basic-thumb-instructions.s.cs | 114 0x1b,0x80 = strh r3, [r3]
115 0x74,0x80 = strh r4, [r6, #2]
116 0xfd,0x87 = strh r5, [r7, #62]
117 0x96,0x53 = strh r6, [r2, r6]
|
| D | basic-thumb2-instructions.s.cs | 938 0x25,0xf8,0x04,0x5c = strh r5, [r5, #-4]
939 0x35,0x84 = strh r5, [r6, #32]
940 0xa6,0xf8,0x21,0x50 = strh.w r5, [r6, #33]
941 0xa6,0xf8,0x01,0x51 = strh.w r5, [r6, #257]
942 0xa7,0xf8,0x01,0xe1 = strh.w lr, [r7, #257]
943 0x28,0xf8,0xff,0x5f = strh r5, [r8, #255]!
944 0x25,0xf8,0x04,0x2f = strh r2, [r5, #4]!
945 0x24,0xf8,0x04,0x1d = strh r1, [r4, #-4]!
946 0x23,0xf8,0xff,0xeb = strh lr, [r3], #255
947 0x22,0xf8,0x04,0x9b = strh r9, [r2], #4
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | fast-isel-ldrh-strh-arm.ll | 85 ; ARM: strh r1, [r0, #-16]
90 ; strh r2, [r0, r1]
98 ; ARM: strh r{{[1-9]}}, [r0]
107 ; ARM: strh r{{[1-9]}}, [r0, #16]
112 ; strh r2, [r0, r1]
119 ; ARM: strh r{{[1-9]}}, [r0]
|
| D | 2014-07-18-earlyclobber-str-post.ll | 15 define i16* @earlyclobber-strh-post(i16* %addr) nounwind {
16 ; CHECK-LABEL: earlyclobber-strh-post
17 ; CHECK-NOT: strh r[[REG:[0-9]+]], [r[[REG]]], #2
|
| D | fast-isel-intrinsic.ll | 163 ; ARM: strh r1, [r0, #12]
174 ; THUMB: strh r1, [r0, #12]
193 ; ARM: strh r1, [r0, #4]
195 ; ARM: strh r1, [r0, #6]
197 ; ARM: strh r1, [r0, #8]
199 ; ARM: strh r1, [r0, #10]
201 ; ARM: strh r1, [r0, #12]
208 ; THUMB: strh r1, [r0, #4]
210 ; THUMB: strh r1, [r0, #6]
212 ; THUMB: strh r1, [r0, #8]
[all …]
|
| D | str_trunc.ll | 15 ; CHECK: strh
16 ; CHECK-NOT: strh
|
| D | bswap16.ll | 15 ; CHECK: strh r[[R1]], [r0]
27 ; CHECK: strh r[[R1]], [r0]
|
| D | MergeConsecutiveStores.ll | 7 ; CHECK: strh [[REG]], [r1], #2
39 ; CHECK: strh [[REG]], [r1], #2
71 ; CHECK-NOT: strh [[REG]], [r1], #2
|
| D | fast-isel.ll | 85 ; THUMB: strh
90 ; ARM: strh
105 ; THUMB: strh
109 ; ARM: strh
|
| D | fp16-promote.ll | 95 ; CHECK-ALL: strh {{r[0-9]+}}, [{{r[0-9]+}}]
155 ; CHECK-ALL: strh {{r[0-9]+}}, [{{r[0-9]+}}]
389 ; CHECK-ALL-NEXT: strh r0, [r1]
819 ; CHECK-ALL: strh
821 ; CHECK-ALL: strh
823 ; CHECK-ALL: strh
825 ; CHECK-ALL: strh
829 ; CHECK-ALL: strh
831 ; CHECK-ALL: strh
833 ; CHECK-ALL: strh
[all …]
|
| D | memcpy-inline.ll | 25 ; CHECK-T1: strh [[TREG2]]
73 ; CHECK: strh [[REG5:r[0-9]+]], [r0]
84 ; CHECK: strh [[REG6]], [r0, #4]
108 ; CHECK-T1: strh [[TREG5]],
|
| D | load.ll | 74 ; CHECK-T1: strh r2, [r0, r1]
75 ; CHECK-T2: strh.w r2, [r0, r1, lsl #1]
156 ; CHECK: strh r1, [r0]
239 ; CHECK: strh r1, [r0, #62]
333 ; CHECK-T1: strh r1, [r0, r2]
334 ; CHECK-T2: strh.w r1, [r0, #64]
433 ; CHECK-T1: strh r1, [r0, r2]
434 ; CHECK-T2: strh.w r1, [r0, #4095]
543 ; CHECK: strh r1, [r0, r2]
|
| D | fast-isel-ldr-str-thumb-neg-index.ll | 116 ; THUMB: strh r{{[0-9]}}, [r0, #-2]
125 ; THUMB: strh r{{[0-9]}}, [r0, #-254]
134 ; THUMB: strh r{{[0-9]}}, [r0]
|
| D | half.ll | 8 ; CHECK: strh [[TMP]], [r1]
24 ; CHECK: strh r1, [r0]
|
| D | mem.ll | 17 ; CHECK: strh
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | memory-arm-instructions.txt | 428 # CHECK: strh r3, [r4
429 # CHECK: strh r2, [r7, #4
430 # CHECK: strh r1, [r8, #64]!
431 # CHECK: strh r12, [sp], #4
447 # CHECK: strh r6, [r5, r4
448 # CHECK: strh r3, [r8, r11]!
449 # CHECK: strh r1, [r2, -r1]!
450 # CHECK: strh r9, [r7], r2
451 # CHECK: strh r4, [r3], -r2
|
| D | thumb1.txt | 448 # CHECK: strh r3, [r3]
449 # CHECK: strh r4, [r6, #2]
450 # CHECK: strh r5, [r7, #62]
460 # CHECK: strh r6, [r2, r6]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 580 strh r3, [r3]
581 strh r4, [r6, #2]
582 strh r5, [r7, #62]
584 @ CHECK: strh r3, [r3] @ encoding: [0x1b,0x80]
585 @ CHECK: strh r4, [r6, #2] @ encoding: [0x74,0x80]
586 @ CHECK: strh r5, [r7, #62] @ encoding: [0xfd,0x87]
592 strh r6, [r2, r6]
594 @ CHECK: strh r6, [r2, r6] @ encoding: [0x96,0x53]
|
| D | arm_instructions.s | 84 @ CHECK: strh r3, [r2, #-0] @ encoding: [0xb0,0x30,0x42,0xe1]
85 strh r3, [r2, #-0]
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-tls-relocs.s | 131 strh w27, [x26, #:tprel_lo12:var]
255 strh w27, [x26, #:dtprel_lo12:var]
|
| D | tls-relocs.s | 140 strh w27, [x26, #:dtprel_lo12:var]
342 strh w27, [x26, #:tprel_lo12:var]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-memcpy-inline.ll | 22 ; CHECK: strh [[REG1]], [x[[BASEREG2]], #8]
67 ; CHECK: strh [[REG5]], [x0, #16]
79 ; CHECK: strh [[REG7]], [x0, #4]
|