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Searched refs:v_mul_u32_u24 (Results 1 – 8 of 8) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dmul_uint24.ll8 ; SI: v_mul_u32_u24
57 ; SI-DAG: v_mul_u32_u24
/external/llvm/test/MC/AMDGPU/
Dvop2.s158 v_mul_u32_u24 v1, v2, v3 label
Dvop_dpp.s374 v_mul_u32_u24 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
Dvop_sdwa.s381 v_mul_u32_u24 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
/external/mesa3d/src/amd/compiler/
Daco_lower_to_hw_instr.cpp98 return aco_opcode::v_mul_u32_u24; in get_reduce_opcode()
1023 bld.vop2_sdwa(aco_opcode::v_mul_u32_u24, dst, in copy_constant()
1100 bld.vop2(aco_opcode::v_mul_u32_u24, dst, Operand((1 << bits) + 1u), op); in do_copy()
Daco_instruction_selection.cpp1730 emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_u32_u24, dst, true); in visit_alu_instr()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DVOP2Instructions.td472 defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32, AMDGPUmul_u24>;
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td1514 defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb, 0x8>, "v_mul_u32_u24",