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Searched refs:vld3 (Results 1 – 25 of 37) sorted by relevance

12

/external/capstone/suite/MC/ARM/
Dneon-vld-encoding.s.cs68 0x0f,0x04,0x61,0xf4 = vld3.8 {d16, d17, d18}, [r1]
69 0x4f,0x64,0x22,0xf4 = vld3.16 {d6, d7, d8}, [r2]
70 0x8f,0x14,0x23,0xf4 = vld3.32 {d1, d2, d3}, [r3]
71 0x1f,0x05,0x60,0xf4 = vld3.8 {d16, d18, d20}, [r0:64]
72 0x4f,0xb5,0x64,0xf4 = vld3.16 {d27, d29, d31}, [r4]
73 0x8f,0x65,0x25,0xf4 = vld3.32 {d6, d8, d10}, [r5]
74 0x01,0xc4,0x26,0xf4 = vld3.8 {d12, d13, d14}, [r6], r1
75 0x42,0xb4,0x27,0xf4 = vld3.16 {d11, d12, d13}, [r7], r2
76 0x83,0x24,0x28,0xf4 = vld3.32 {d2, d3, d4}, [r8], r3
77 0x04,0x45,0x29,0xf4 = vld3.8 {d4, d6, d8}, [r9], r4
[all …]
Dneont2-vld-encoding.s.cs16 0x60,0xf9,0x1f,0x04 = vld3.8 {d16, d17, d18}, [r0:64]
17 0x60,0xf9,0x4f,0x04 = vld3.16 {d16, d17, d18}, [r0]
18 0x60,0xf9,0x8f,0x04 = vld3.32 {d16, d17, d18}, [r0]
19 0x60,0xf9,0x1d,0x05 = vld3.8 {d16, d18, d20}, [r0:64]!
20 0x60,0xf9,0x1d,0x15 = vld3.8 {d17, d19, d21}, [r0:64]!
21 0x60,0xf9,0x4d,0x05 = vld3.16 {d16, d18, d20}, [r0]!
22 0x60,0xf9,0x4d,0x15 = vld3.16 {d17, d19, d21}, [r0]!
23 0x60,0xf9,0x8d,0x05 = vld3.32 {d16, d18, d20}, [r0]!
24 0x60,0xf9,0x8d,0x15 = vld3.32 {d17, d19, d21}, [r0]!
42 0xe0,0xf9,0x2f,0x02 = vld3.8 {d16[1], d17[1], d18[1]}, [r0]
[all …]
/external/llvm/test/MC/ARM/
Dneon-vld-encoding.s157 vld3.8 {d16, d17, d18}, [r1]
158 vld3.16 {d6, d7, d8}, [r2]
159 vld3.32 {d1, d2, d3}, [r3]
160 vld3.8 {d16, d18, d20}, [r0:64]
161 vld3.u16 {d27, d29, d31}, [r4]
162 vld3.i32 {d6, d8, d10}, [r5]
164 vld3.i8 {d12, d13, d14}, [r6], r1
165 vld3.i16 {d11, d12, d13}, [r7], r2
166 vld3.u32 {d2, d3, d4}, [r8], r3
167 vld3.8 {d4, d6, d8}, [r9], r4
[all …]
Dneont2-vld-encoding.s35 @ CHECK: vld3.8 {d16, d17, d18}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x04]
36 vld3.8 {d16, d17, d18}, [r0:64]
37 @ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x60,0xf9,0x4f,0x04]
38 vld3.16 {d16, d17, d18}, [r0]
39 @ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x60,0xf9,0x8f,0x04]
40 vld3.32 {d16, d17, d18}, [r0]
41 @ CHECK: vld3.8 {d16, d18, d20}, [r0:64]! @ encoding: [0x60,0xf9,0x1d,0x05]
42 vld3.8 {d16, d18, d20}, [r0:64]!
43 @ CHECK: vld3.8 {d17, d19, d21}, [r0:64]! @ encoding: [0x60,0xf9,0x1d,0x15]
44 vld3.8 {d17, d19, d21}, [r0:64]!
[all …]
Dneon-vld-vst-align.s2912 vld3.8 {d0, d1, d2}, [r4]
2913 vld3.8 {d0, d1, d2}, [r4:16]
2914 vld3.8 {d0, d1, d2}, [r4:32]
2915 vld3.8 {d0, d1, d2}, [r4:64]
2916 vld3.8 {d0, d1, d2}, [r4:128]
2917 vld3.8 {d0, d1, d2}, [r4:256]
2919 @ CHECK: vld3.8 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x04]
2921 @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:16]
2924 @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:32]
2926 @ CHECK: vld3.8 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x04]
[all …]
/external/llvm/test/CodeGen/ARM/
Dvld3.ll18 ;CHECK: vld3.8 {d16, d17, d18}, [r0:64]
19 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A, i32 32)
28 ;CHECK: vld3.16
30 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8* %tmp0, i32 1)
40 ;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}}
43 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8* %tmp0, i32 1)
54 ;CHECK: vld3.32
56 %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32.p0i8(i8* %tmp0, i32 1)
65 ;CHECK: vld3.32
67 %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32.p0i8(i8* %tmp0, i32 1)
[all …]
D2010-05-20-NEONSpillCrash.ll4 ; the @llvm.arm.neon.vld3.v8i8.p0i8 defined three parts of a register.
8 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly
13 …%tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A2, i32 1) ; <%struct._…
16 …%tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A4, i32 1) ; <%struct._…
19 …%tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A5, i32 1) ; <%struct._…
21 …%tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A6, i32 1) ; <%struct._…
23 …%tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A7, i32 1) ; <%struct._…
26 …%tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A8, i32 1) ; <%struct._…
D2012-08-27-CopyPhysRegCrash.ll8 declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8*, i32) nounwind reado…
22 %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* null, i32 1)
25 %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %9, i32 1)
27 %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %6, i32 1)
31 %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %15, i32 1)
Darm-interleaved-accesses.ll17 ; NEON: vld3.32 {d16, d17, d18}, [r0]
19 ; NONEON-NOT: vld3
96 ; NEON: vld3.32 {d16, d17, d18}, [r0]
98 ; NONEON-NOT: vld3
177 ; NEON: vld3.32 {d16, d18, d20}, [r0]!
178 ; NEON: vld3.32 {d17, d19, d21}, [r0]
180 ; NONEON-NOT: vld3
246 ; NEON: vld3.32
248 ; NONEON-NOT: vld3
Dvld-vst-upgrade.ll28 ; CHECK: vld3.32 {d16, d17, d18}, [r1]
30 %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %ptr, i32 1)
34 declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8*, i32) nounwind readonly
57 ; CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r1]
Dvldlane.ll223 ;CHECK: vld3.8
237 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
251 ;CHECK: vld3.32
265 ;CHECK: vld3.32
280 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
295 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}], {{r[0-9]+}}
312 ;CHECK: vld3.32
326 ;CHECK: vld3.32
508 ;CHECK: vld3.16
Dreg_sequence.ll79 ; CHECK: vld3.8
84 …%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A, i32 1) ; <%struct.__n…
310 …%tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A4, i32 1) ; <%struct._…
312 …%tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A6, i32 1) ; <%struct._…
338 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly
Dvlddup.ll132 ;CHECK: vld3.8 {d16[], d17[], d18[]}, [r2], r1
151 ;CHECK: vld3.16 {d16[], d17[], d18[]}, [r0]
/external/llvm/test/Transforms/EarlyCSE/AArch64/
Dintrinsics.ll168 %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i8(i8* %5)
169 %vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0
170 %vld3.fca.2.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 2
171 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.2.extract)
205 %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i8(i8* %5)
206 %vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0
207 %vld3.fca.1.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 1
208 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.0.extract)
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt1412 # CHECK: vld3.8 {d16, d17, d18}, [r0:64]
1414 # CHECK: vld3.16 {d16, d17, d18}, [r0]
1416 # CHECK: vld3.32 {d16, d17, d18}, [r0]
1418 # CHECK: vld3.8 {d16, d18, d20}, [r0:64]!
1420 # CHECK: vld3.8 {d17, d19, d21}, [r0:64]!
1422 # CHECK: vld3.16 {d16, d18, d20}, [r0]!
1424 # CHECK: vld3.16 {d17, d19, d21}, [r0]!
1426 # CHECK: vld3.32 {d16, d18, d20}, [r0]!
1428 # CHECK: vld3.32 {d17, d19, d21}, [r0]!
1468 # CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0]
[all …]
Dneon.txt1671 # CHECK: vld3.8 {d16, d17, d18}, [r0:64]
1673 # CHECK: vld3.16 {d16, d17, d18}, [r0]
1675 # CHECK: vld3.32 {d16, d17, d18}, [r0]
1677 # CHECK: vld3.8 {d16, d18, d20}, [r0:64]!
1679 # CHECK: vld3.8 {d17, d19, d21}, [r0:64]!
1681 # CHECK: vld3.16 {d16, d18, d20}, [r0]!
1683 # CHECK: vld3.16 {d17, d19, d21}, [r0]!
1685 # CHECK: vld3.32 {d16, d18, d20}, [r0]!
1687 # CHECK: vld3.32 {d17, d19, d21}, [r0]!
1727 # CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0]
[all …]
Dinvalid-thumbv7.txt251 # vld3
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-vector-list-spill.ll93 …%vld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3.v4f32.p0f32(flo…
102 %vld3.extract = extractvalue { <4 x float>, <4 x float>, <4 x float> } %vld3, 0
103 %res = extractelement <4 x float> %vld3.extract, i32 1
/external/renderscript-intrinsics-replacement-toolkit/renderscript-toolkit/src/main/cpp/
DColorMatrix_neon.S180 vld3.32 {d0[0],d2[0],d4[0]}, [r1]!
182 vld3.32 {d0[1],d2[1],d4[1]}, [r1]!
184 vld3.32 {d1[0],d3[0],d5[0]}, [r1]!
186 vld3.32 {d1[1],d3[1],d5[1]}, [r1]!
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc9927 "vld1\004vld2\005vld20\005vld21\004vld3\004vld4\005vld40\005vld41\005vld"
12719 …{ 2370 /* vld3 */, ARM::VLD3DUPdAsm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3…
12720 …{ 2370 /* vld3 */, ARM::VLD3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, A…
12721 …{ 2370 /* vld3 */, ARM::VLD3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3…
12722 …{ 2370 /* vld3 */, ARM::VLD3DUPqAsm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3…
12723 …{ 2370 /* vld3 */, ARM::VLD3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, A…
12724 …{ 2370 /* vld3 */, ARM::VLD3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3…
12725 …{ 2370 /* vld3 */, ARM::VLD3DUPdAsm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3…
12726 …{ 2370 /* vld3 */, ARM::VLD3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, A…
12727 …{ 2370 /* vld3 */, ARM::VLD3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3_…
[all …]
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc2560 { /* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */
2563 { /* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2566 { /* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */
2569 { /* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2572 { /* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn */
2575 { /* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2578 { /* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */
2581 { /* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2584 { /* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */
2587 { /* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */
[all …]
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc2560 { /* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */
2563 { /* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2566 { /* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */
2569 { /* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2572 { /* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn */
2575 { /* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2578 { /* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */
2581 { /* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2584 { /* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */
2587 { /* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td908 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
927 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
1208 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1246 IIC_VLD3lnu, "vld3", Dt,
1519 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1542 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
7377 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
7380 def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
7383 def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
7386 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td889 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []>, Sched<[WriteVLD3]> {
908 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
1215 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1253 IIC_VLD3lnu, "vld3", Dt,
1539 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []>,
1570 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
8113 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
8116 def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
8119 def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
8122 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
[all …]
/external/llvm/test/Transforms/LoopStrengthReduce/ARM/
Divchain-ARM.ll335 %vld3 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %add.ptr7, i32 1)
346 %vadd2 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld2, <8 x i8> %vld3) nounwind
347 %vadd3 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld3, <8 x i8> %vld4) nounwind

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