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Searched refs:vqshrn (Results 1 – 24 of 24) sorted by relevance

/external/llvm/test/MC/ARM/
Dneon-satshift-encoding.s115 @ CHECK: vqshrn.s16 d16, q8, #8 @ encoding: [0x30,0x09,0xc8,0xf2]
116 vqshrn.s16 d16, q8, #8
117 @ CHECK: vqshrn.s32 d16, q8, #16 @ encoding: [0x30,0x09,0xd0,0xf2]
118 vqshrn.s32 d16, q8, #16
119 @ CHECK: vqshrn.s64 d16, q8, #32 @ encoding: [0x30,0x09,0xe0,0xf2]
120 vqshrn.s64 d16, q8, #32
121 @ CHECK: vqshrn.u16 d16, q8, #8 @ encoding: [0x30,0x09,0xc8,0xf3]
122 vqshrn.u16 d16, q8, #8
123 @ CHECK: vqshrn.u32 d16, q8, #16 @ encoding: [0x30,0x09,0xd0,0xf3]
124 vqshrn.u32 d16, q8, #16
[all …]
Dneont2-satshift-encoding.s117 @ CHECK: vqshrn.s16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x09]
118 vqshrn.s16 d16, q8, #8
119 @ CHECK: vqshrn.s32 d16, q8, #16 @ encoding: [0xd0,0xef,0x30,0x09]
120 vqshrn.s32 d16, q8, #16
121 @ CHECK: vqshrn.s64 d16, q8, #32 @ encoding: [0xe0,0xef,0x30,0x09]
122 vqshrn.s64 d16, q8, #32
123 @ CHECK: vqshrn.u16 d16, q8, #8 @ encoding: [0xc8,0xff,0x30,0x09]
124 vqshrn.u16 d16, q8, #8
125 @ CHECK: vqshrn.u32 d16, q8, #16 @ encoding: [0xd0,0xff,0x30,0x09]
126 vqshrn.u32 d16, q8, #16
[all …]
/external/libhevc/common/arm/
Dihevc_inter_pred_chroma_vert_w16inp_w16out.s159 vqshrn.s32 d0,q0,#6 @right shift
160 vqshrn.s32 d30,q4,#6 @right shift
208 vqshrn.s32 d30,q15,#6 @right shift
218 vqshrn.s32 d28,q14,#6 @right shift
230 vqshrn.s32 d26,q13,#6 @right shift
243 vqshrn.s32 d24,q12,#6 @right shift
254 vqshrn.s32 d30,q15,#6 @right shift
266 vqshrn.s32 d28,q14,#6 @right shift
279 vqshrn.s32 d26,q13,#6 @right shift
293 vqshrn.s32 d24,q12,#6 @right shift
[all …]
Dihevc_inter_pred_chroma_vert_w16inp.s159 vqshrn.s32 d0,q0,#6 @right shift
160 vqshrn.s32 d30,q4,#6 @right shift
210 vqshrn.s32 d30,q15,#6 @right shift
220 vqshrn.s32 d28,q14,#6 @right shift
232 vqshrn.s32 d26,q13,#6 @right shift
246 vqshrn.s32 d24,q12,#6 @right shift
258 vqshrn.s32 d30,q15,#6 @right shift
271 vqshrn.s32 d28,q14,#6 @right shift
285 vqshrn.s32 d26,q13,#6 @right shift
300 vqshrn.s32 d24,q12,#6 @right shift
[all …]
Dihevc_inter_pred_filters_luma_vert_w16inp.s182 vqshrn.s32 d8, q4, #6
196 vqshrn.s32 d10, q5, #6
214 vqshrn.s32 d12, q6, #6
237 vqshrn.s32 d14, q7, #6
254 vqshrn.s32 d8, q4, #6
280 vqshrn.s32 d10, q5, #6
300 vqshrn.s32 d12, q6, #6
320 vqshrn.s32 d14, q7, #6
334 vqshrn.s32 d8, q4, #6
347 vqshrn.s32 d10, q5, #6
[all …]
Dihevc_deblk_luma_horz.s502 vqshrn.s16 d14,q7,#1
534 vqshrn.s16 d14,q7,#1
/external/capstone/suite/MC/ARM/
Dneon-satshift-encoding.s.cs58 0x30,0x09,0xc8,0xf2 = vqshrn.s16 d16, q8, #8
59 0x30,0x09,0xd0,0xf2 = vqshrn.s32 d16, q8, #16
60 0x30,0x09,0xe0,0xf2 = vqshrn.s64 d16, q8, #32
61 0x30,0x09,0xc8,0xf3 = vqshrn.u16 d16, q8, #8
62 0x30,0x09,0xd0,0xf3 = vqshrn.u32 d16, q8, #16
63 0x30,0x09,0xe0,0xf3 = vqshrn.u64 d16, q8, #32
Dneont2-satshift-encoding.s.cs58 0xc8,0xef,0x30,0x09 = vqshrn.s16 d16, q8, #8
59 0xd0,0xef,0x30,0x09 = vqshrn.s32 d16, q8, #16
60 0xe0,0xef,0x30,0x09 = vqshrn.s64 d16, q8, #32
61 0xc8,0xff,0x30,0x09 = vqshrn.u16 d16, q8, #8
62 0xd0,0xff,0x30,0x09 = vqshrn.u32 d16, q8, #16
63 0xe0,0xff,0x30,0x09 = vqshrn.u64 d16, q8, #32
/external/llvm/test/CodeGen/ARM/
Dvqshrn.ll5 ;CHECK: vqshrn.s16
13 ;CHECK: vqshrn.s32
21 ;CHECK: vqshrn.s64
29 ;CHECK: vqshrn.u16
37 ;CHECK: vqshrn.u32
45 ;CHECK: vqshrn.u64
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-simd-shift.ll435 %vqshrn = tail call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %b, i32 3)
437 %2 = bitcast <8 x i8> %vqshrn to <1 x i64>
446 %vqshrn = tail call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %b, i32 9)
448 %2 = bitcast <4 x i16> %vqshrn to <1 x i64>
458 %vqshrn = tail call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %b, i32 19)
459 %2 = bitcast <2 x i32> %vqshrn to <1 x i64>
468 %vqshrn = tail call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %b, i32 3)
470 %2 = bitcast <8 x i8> %vqshrn to <1 x i64>
479 %vqshrn = tail call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %b, i32 9)
481 %2 = bitcast <4 x i16> %vqshrn to <1 x i64>
[all …]
/external/libavc/common/arm/
Dih264_deblk_luma_a9.s159 vqshrn.s16 d29, q14, #1 @
160 vqshrn.s16 d28, q5, #1 @Q14 = i_macro_p1
166 vqshrn.s16 d31, q15, #1 @
167 vqshrn.s16 d30, q2, #1 @Q15 = i_macro_q1
/external/renderscript-intrinsics-replacement-toolkit/renderscript-toolkit/src/main/cpp/
DResize_neon.S76 vqshrn.s32 \dstlo, q12, #8 + 16 - VERTBITS
77 vqshrn.s32 \dsthi, q13, #8 + 16 - VERTBITS
95 vqshrn.s32 d25, q12, #8 + 16 - VERTBITS
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt984 # CHECK: vqshrn.s16 d16, q8, #8
986 # CHECK: vqshrn.s32 d16, q8, #16
988 # CHECK: vqshrn.s64 d16, q8, #32
990 # CHECK: vqshrn.u16 d16, q8, #8
992 # CHECK: vqshrn.u32 d16, q8, #16
994 # CHECK: vqshrn.u64 d16, q8, #32
Dneon.txt1095 # CHECK: vqshrn.s16 d16, q8, #8
1097 # CHECK: vqshrn.s32 d16, q8, #16
1099 # CHECK: vqshrn.s64 d16, q8, #32
1101 # CHECK: vqshrn.u16 d16, q8, #8
1103 # CHECK: vqshrn.u32 d16, q8, #16
1105 # CHECK: vqshrn.u64 d16, q8, #32
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc3868 { /* ARM_VQSHRNsv2i32, ARM_INS_VQSHRN: vqshrn${p}.s64 $vd, $vm, $simm */
3871 { /* ARM_VQSHRNsv4i16, ARM_INS_VQSHRN: vqshrn${p}.s32 $vd, $vm, $simm */
3874 { /* ARM_VQSHRNsv8i8, ARM_INS_VQSHRN: vqshrn${p}.s16 $vd, $vm, $simm */
3877 { /* ARM_VQSHRNuv2i32, ARM_INS_VQSHRN: vqshrn${p}.u64 $vd, $vm, $simm */
3880 { /* ARM_VQSHRNuv4i16, ARM_INS_VQSHRN: vqshrn${p}.u32 $vd, $vm, $simm */
3883 { /* ARM_VQSHRNuv8i8, ARM_INS_VQSHRN: vqshrn${p}.u16 $vd, $vm, $simm */
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc3868 { /* ARM_VQSHRNsv2i32, ARM_INS_VQSHRN: vqshrn${p}.s64 $vd, $vm, $simm */
3871 { /* ARM_VQSHRNsv4i16, ARM_INS_VQSHRN: vqshrn${p}.s32 $vd, $vm, $simm */
3874 { /* ARM_VQSHRNsv8i8, ARM_INS_VQSHRN: vqshrn${p}.s16 $vd, $vm, $simm */
3877 { /* ARM_VQSHRNuv2i32, ARM_INS_VQSHRN: vqshrn${p}.u64 $vd, $vm, $simm */
3880 { /* ARM_VQSHRNuv4i16, ARM_INS_VQSHRN: vqshrn${p}.u32 $vd, $vm, $simm */
3883 { /* ARM_VQSHRNuv8i8, ARM_INS_VQSHRN: vqshrn${p}.u16 $vd, $vm, $simm */
/external/vixl/src/aarch32/
Dassembler-aarch32.h5445 void vqshrn(Condition cond,
5450 void vqshrn(DataType dt, in vqshrn() function
5454 vqshrn(al, dt, rd, rm, operand); in vqshrn()
Ddisasm-aarch32.h2272 void vqshrn(Condition cond,
Ddisasm-aarch32.cc6002 void Disassembler::vqshrn(Condition cond, in vqshrn() function in vixl::aarch32::Disassembler
31873 vqshrn(CurrentCond(), in DecodeT32()
32016 vqshrn(CurrentCond(), in DecodeT32()
32159 vqshrn(CurrentCond(), in DecodeT32()
32302 vqshrn(CurrentCond(), in DecodeT32()
32444 vqshrn(CurrentCond(), in DecodeT32()
44401 vqshrn(al, in DecodeA32()
44536 vqshrn(al, in DecodeA32()
44671 vqshrn(al, in DecodeA32()
44806 vqshrn(al, in DecodeA32()
[all …]
Dassembler-aarch32.cc23658 void Assembler::vqshrn(Condition cond, in vqshrn() function in vixl::aarch32::Assembler
23718 Delegate(kVqshrn, &Assembler::vqshrn, cond, dt, rd, rm, operand); in vqshrn()
Dmacro-assembler-aarch32.h8969 vqshrn(cond, dt, rd, rm, operand); in Vqshrn()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc9945 "unt\005vqshl\006vqshlu\006vqshrn\007vqshrnb\007vqshrnt\007vqshrun\010vq"
14061 …{ 3299 /* vqshrn */, ARM::VQSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_Has…
14062 …{ 3299 /* vqshrn */, ARM::VQSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_H…
14063 …{ 3299 /* vqshrn */, ARM::VQSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_H…
14064 …{ 3299 /* vqshrn */, ARM::VQSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_Has…
14065 …{ 3299 /* vqshrn */, ARM::VQSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_H…
14066 …{ 3299 /* vqshrn */, ARM::VQSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_H…
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td5509 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
5511 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td5977 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
5979 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",