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Searched refs:vrecpe (Results 1 – 25 of 35) sorted by relevance

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/external/llvm/test/MC/ARM/
Dneon-reciprocal-encoding.s3 @ CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xf3]
4 vrecpe.u32 d16, d16
5 @ CHECK: vrecpe.u32 q8, q8 @ encoding: [0x60,0x04,0xfb,0xf3]
6 vrecpe.u32 q8, q8
7 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3]
8 vrecpe.f32 d16, d16
9 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3]
10 vrecpe.f32 q8, q8
Dneont2-reciprocal-encoding.s5 @ CHECK: vrecpe.u32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x04]
6 vrecpe.u32 d16, d16
7 @ CHECK: vrecpe.u32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x04]
8 vrecpe.u32 q8, q8
9 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x05]
10 vrecpe.f32 d16, d16
11 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x05]
12 vrecpe.f32 q8, q8
Dfullfp16-neon.s226 vrecpe.f16 d0, d1
227 vrecpe.f16 q0, q1
228 @ ARM: vrecpe.f16 d0, d1 @ encoding: [0x01,0x05,0xb7,0xf3]
229 @ ARM: vrecpe.f16 q0, q1 @ encoding: [0x42,0x05,0xb7,0xf3]
230 @ THUMB: vrecpe.f16 d0, d1 @ encoding: [0xb7,0xff,0x01,0x05]
231 @ THUMB: vrecpe.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x05]
Dfullfp16-neon-neg.s165 vrecpe.f16 d0, d1
166 vrecpe.f16 q0, q1
/external/llvm/test/CodeGen/ARM/
Dvrec.ll5 ;CHECK: vrecpe.u32
7 %tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
13 ;CHECK: vrecpe.u32
15 %tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
21 ;CHECK: vrecpe.f32
23 %tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
29 ;CHECK: vrecpe.f32
31 %tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
35 declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone
36 declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
[all …]
Dneon_div.ll5 ;CHECK: vrecpe.f32
7 ;CHECK: vrecpe.f32
17 ;CHECK: vrecpe.f32
20 ;CHECK: vrecpe.f32
31 ;CHECK: vrecpe.f32
41 ;CHECK: vrecpe.f32
D2009-10-02-NEONSubregsBug.ll38 …%29 = tail call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> zeroinitializer) nounwind ; <<…
63 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
Dvector-extend-narrow.ll57 ; CHECK: vrecpe
D2012-01-23-PostRA-LICM.ll32 %tmp16 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp11) nounwind
101 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
/external/capstone/suite/MC/ARM/
Dneont2-reciprocal-encoding.s.cs2 0xfb,0xff,0x20,0x04 = vrecpe.u32 d16, d16
3 0xfb,0xff,0x60,0x04 = vrecpe.u32 q8, q8
4 0xfb,0xff,0x20,0x05 = vrecpe.f32 d16, d16
5 0xfb,0xff,0x60,0x05 = vrecpe.f32 q8, q8
Dneon-reciprocal-encoding.s.cs2 0x20,0x04,0xfb,0xf3 = vrecpe.u32 d16, d16
3 0x60,0x04,0xfb,0xf3 = vrecpe.u32 q8, q8
4 0x20,0x05,0xfb,0xf3 = vrecpe.f32 d16, d16
5 0x60,0x05,0xfb,0xf3 = vrecpe.f32 q8, q8
/external/arm-neon-tests/
Dref_vrecpe.c43 vrecpe##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \ in exec_vrecpe()
DMakefile.gcc60 vqrshrun_n vstX_lane vtbX vrecpe vrsqrte vcage vcagt vcale \
DMakefile54 vqrshrun_n vstX_lane vtbX vrecpe vrsqrte vcage vcagt vcale \
/external/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-thumb.txt143 # CHECK: vrecpe.f16 d0, d1
144 # CHECK: vrecpe.f16 q0, q1
Dfullfp16-neon-arm.txt143 # CHECK: vrecpe.f16 d0, d1
144 # CHECK: vrecpe.f16 q0, q1
Dneont2.txt822 # CHECK: vrecpe.u32 d16, d16
824 # CHECK: vrecpe.u32 q8, q8
826 # CHECK: vrecpe.f32 d16, d16
828 # CHECK: vrecpe.f32 q8, q8
Dneon.txt931 # CHECK: vrecpe.u32 d16, d16
933 # CHECK: vrecpe.u32 q8, q8
935 # CHECK: vrecpe.f32 d16, d16
937 # CHECK: vrecpe.f32 q8, q8
/external/clang/include/clang/Basic/
Darm_neon.td796 def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">;
956 def FRECPE : SInst<"vrecpe", "dd", "dQd">;
1498 def SCALAR_FRECPE : IInst<"vrecpe", "ss", "SfSd">;
/external/vixl/src/aarch32/
Dassembler-aarch32.h5487 void vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm);
5488 void vrecpe(DataType dt, DRegister rd, DRegister rm) { in vrecpe() function
5489 vrecpe(al, dt, rd, rm); in vrecpe()
5492 void vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm);
5493 void vrecpe(DataType dt, QRegister rd, QRegister rm) { in vrecpe() function
5494 vrecpe(al, dt, rd, rm); in vrecpe()
Ddisasm-aarch32.h2293 void vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm);
2295 void vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm);
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td5337 IIC_VUNAD, "vrecpe", "u32",
5340 IIC_VUNAQ, "vrecpe", "u32",
5343 IIC_VUNAD, "vrecpe", "f32",
5346 IIC_VUNAQ, "vrecpe", "f32",
5349 IIC_VUNAD, "vrecpe", "f16",
5353 IIC_VUNAQ, "vrecpe", "f16",
8171 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
8172 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td5758 IIC_VUNAD, "vrecpe", "u32",
5761 IIC_VUNAQ, "vrecpe", "u32",
5764 IIC_VUNAD, "vrecpe", "f32",
5767 IIC_VUNAQ, "vrecpe", "f32",
5770 IIC_VUNAD, "vrecpe", "f16",
5774 IIC_VUNAQ, "vrecpe", "f16",
8907 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
8908 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc3952 { /* ARM_VRECPEd, ARM_INS_VRECPE: vrecpe${p}.u32 $vd, $vm */
3955 { /* ARM_VRECPEfd, ARM_INS_VRECPE: vrecpe${p}.f32 $vd, $vm */
3958 { /* ARM_VRECPEfq, ARM_INS_VRECPE: vrecpe${p}.f32 $vd, $vm */
3961 { /* ARM_VRECPEq, ARM_INS_VRECPE: vrecpe${p}.u32 $vd, $vm */
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc3952 { /* ARM_VRECPEd, ARM_INS_VRECPE: vrecpe${p}.u32 $vd, $vm */
3955 { /* ARM_VRECPEfd, ARM_INS_VRECPE: vrecpe${p}.f32 $vd, $vm */
3958 { /* ARM_VRECPEfq, ARM_INS_VRECPE: vrecpe${p}.f32 $vd, $vm */
3961 { /* ARM_VRECPEq, ARM_INS_VRECPE: vrecpe${p}.u32 $vd, $vm */

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