1 /*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <endian.h>
9 #include <errno.h>
10 #include <stdint.h>
11 #include <string.h>
12
13 #include <platform_def.h>
14
15 #include <arch_helpers.h>
16 #include <common/debug.h>
17 #include <drivers/delay_timer.h>
18 #include <drivers/ufs.h>
19 #include <lib/mmio.h>
20
21 #define CDB_ADDR_MASK 127
22 #define ALIGN_CDB(x) (((x) + CDB_ADDR_MASK) & ~CDB_ADDR_MASK)
23 #define ALIGN_8(x) (((x) + 7) & ~7)
24
25 #define UFS_DESC_SIZE 0x400
26 #define MAX_UFS_DESC_SIZE 0x8000 /* 32 descriptors */
27
28 #define MAX_PRDT_SIZE 0x40000 /* 256KB */
29
30 static ufs_params_t ufs_params;
31 static int nutrs; /* Number of UTP Transfer Request Slots */
32
ufshc_send_uic_cmd(uintptr_t base,uic_cmd_t * cmd)33 int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd)
34 {
35 unsigned int data;
36
37 if (base == 0 || cmd == NULL)
38 return -EINVAL;
39
40 data = mmio_read_32(base + HCS);
41 if ((data & HCS_UCRDY) == 0)
42 return -EBUSY;
43 mmio_write_32(base + IS, ~0);
44 mmio_write_32(base + UCMDARG1, cmd->arg1);
45 mmio_write_32(base + UCMDARG2, cmd->arg2);
46 mmio_write_32(base + UCMDARG3, cmd->arg3);
47 mmio_write_32(base + UICCMD, cmd->op);
48
49 do {
50 data = mmio_read_32(base + IS);
51 } while ((data & UFS_INT_UCCS) == 0);
52 mmio_write_32(base + IS, UFS_INT_UCCS);
53 return mmio_read_32(base + UCMDARG2) & CONFIG_RESULT_CODE_MASK;
54 }
55
ufshc_dme_get(unsigned int attr,unsigned int idx,unsigned int * val)56 int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val)
57 {
58 uintptr_t base;
59 unsigned int data;
60 int result, retries;
61 uic_cmd_t cmd;
62
63 assert(ufs_params.reg_base != 0);
64
65 if (val == NULL)
66 return -EINVAL;
67
68 base = ufs_params.reg_base;
69 for (retries = 0; retries < 100; retries++) {
70 data = mmio_read_32(base + HCS);
71 if ((data & HCS_UCRDY) != 0)
72 break;
73 mdelay(1);
74 }
75 if (retries >= 100)
76 return -EBUSY;
77
78 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx);
79 cmd.arg2 = 0;
80 cmd.arg3 = 0;
81 cmd.op = DME_GET;
82 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) {
83 result = ufshc_send_uic_cmd(base, &cmd);
84 if (result == 0)
85 break;
86 data = mmio_read_32(base + IS);
87 if (data & UFS_INT_UE)
88 return -EINVAL;
89 }
90 if (retries >= UFS_UIC_COMMAND_RETRIES)
91 return -EIO;
92
93 *val = mmio_read_32(base + UCMDARG3);
94 return 0;
95 }
96
ufshc_dme_set(unsigned int attr,unsigned int idx,unsigned int val)97 int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val)
98 {
99 uintptr_t base;
100 unsigned int data;
101 int result, retries;
102 uic_cmd_t cmd;
103
104 assert((ufs_params.reg_base != 0));
105
106 base = ufs_params.reg_base;
107 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx);
108 cmd.arg2 = 0;
109 cmd.arg3 = val;
110 cmd.op = DME_SET;
111
112 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) {
113 result = ufshc_send_uic_cmd(base, &cmd);
114 if (result == 0)
115 break;
116 data = mmio_read_32(base + IS);
117 if (data & UFS_INT_UE)
118 return -EINVAL;
119 }
120 if (retries >= UFS_UIC_COMMAND_RETRIES)
121 return -EIO;
122
123 return 0;
124 }
125
ufshc_hce_enable(uintptr_t base)126 static int ufshc_hce_enable(uintptr_t base)
127 {
128 unsigned int data;
129 int retries;
130
131 /* Enable Host Controller */
132 mmio_write_32(base + HCE, HCE_ENABLE);
133
134 /* Wait until basic initialization sequence completed */
135 for (retries = 0; retries < HCE_ENABLE_INNER_RETRIES; ++retries) {
136 data = mmio_read_32(base + HCE);
137 if (data & HCE_ENABLE) {
138 break;
139 }
140 udelay(HCE_ENABLE_TIMEOUT_US);
141 }
142 if (retries >= HCE_ENABLE_INNER_RETRIES) {
143 return -ETIMEDOUT;
144 }
145
146 return 0;
147 }
148
ufshc_reset(uintptr_t base)149 static int ufshc_reset(uintptr_t base)
150 {
151 unsigned int data;
152 int retries, result;
153
154 for (retries = 0; retries < HCE_ENABLE_OUTER_RETRIES; ++retries) {
155 result = ufshc_hce_enable(base);
156 if (result == 0) {
157 break;
158 }
159 }
160 if (retries >= HCE_ENABLE_OUTER_RETRIES) {
161 return -EIO;
162 }
163
164 /* Enable Interrupts */
165 data = UFS_INT_UCCS | UFS_INT_ULSS | UFS_INT_UE | UFS_INT_UTPES |
166 UFS_INT_DFES | UFS_INT_HCFES | UFS_INT_SBFES;
167 mmio_write_32(base + IE, data);
168
169 return 0;
170 }
171
ufshc_dme_link_startup(uintptr_t base)172 static int ufshc_dme_link_startup(uintptr_t base)
173 {
174 uic_cmd_t cmd;
175
176 memset(&cmd, 0, sizeof(cmd));
177 cmd.op = DME_LINKSTARTUP;
178 return ufshc_send_uic_cmd(base, &cmd);
179 }
180
ufshc_link_startup(uintptr_t base)181 static int ufshc_link_startup(uintptr_t base)
182 {
183 int data, result;
184 int retries;
185
186 for (retries = DME_LINKSTARTUP_RETRIES; retries > 0; retries--) {
187 result = ufshc_dme_link_startup(base);
188 if (result != 0) {
189 /* Reset controller before trying again */
190 result = ufshc_reset(base);
191 if (result != 0) {
192 return result;
193 }
194 continue;
195 }
196 while ((mmio_read_32(base + HCS) & HCS_DP) == 0)
197 ;
198 data = mmio_read_32(base + IS);
199 if (data & UFS_INT_ULSS)
200 mmio_write_32(base + IS, UFS_INT_ULSS);
201 return 0;
202 }
203 return -EIO;
204 }
205
206 /* Check Door Bell register to get an empty slot */
get_empty_slot(int * slot)207 static int get_empty_slot(int *slot)
208 {
209 unsigned int data;
210 int i;
211
212 data = mmio_read_32(ufs_params.reg_base + UTRLDBR);
213 for (i = 0; i < nutrs; i++) {
214 if ((data & 1) == 0)
215 break;
216 data = data >> 1;
217 }
218 if (i >= nutrs)
219 return -EBUSY;
220 *slot = i;
221 return 0;
222 }
223
get_utrd(utp_utrd_t * utrd)224 static void get_utrd(utp_utrd_t *utrd)
225 {
226 uintptr_t base;
227 int slot = 0, result;
228 utrd_header_t *hd;
229
230 assert(utrd != NULL);
231 result = get_empty_slot(&slot);
232 assert(result == 0);
233
234 /* clear utrd */
235 memset((void *)utrd, 0, sizeof(utp_utrd_t));
236 base = ufs_params.desc_base + (slot * UFS_DESC_SIZE);
237 /* clear the descriptor */
238 memset((void *)base, 0, UFS_DESC_SIZE);
239
240 utrd->header = base;
241 utrd->task_tag = slot + 1;
242 /* CDB address should be aligned with 128 bytes */
243 utrd->upiu = ALIGN_CDB(utrd->header + sizeof(utrd_header_t));
244 utrd->resp_upiu = ALIGN_8(utrd->upiu + sizeof(cmd_upiu_t));
245 utrd->size_upiu = utrd->resp_upiu - utrd->upiu;
246 utrd->size_resp_upiu = ALIGN_8(sizeof(resp_upiu_t));
247 utrd->prdt = utrd->resp_upiu + utrd->size_resp_upiu;
248
249 hd = (utrd_header_t *)utrd->header;
250 hd->ucdba = utrd->upiu & UINT32_MAX;
251 hd->ucdbau = (utrd->upiu >> 32) & UINT32_MAX;
252 /* Both RUL and RUO is based on DWORD */
253 hd->rul = utrd->size_resp_upiu >> 2;
254 hd->ruo = utrd->size_upiu >> 2;
255 (void)result;
256 }
257
258 /*
259 * Prepare UTRD, Command UPIU, Response UPIU.
260 */
ufs_prepare_cmd(utp_utrd_t * utrd,uint8_t op,uint8_t lun,int lba,uintptr_t buf,size_t length)261 static int ufs_prepare_cmd(utp_utrd_t *utrd, uint8_t op, uint8_t lun,
262 int lba, uintptr_t buf, size_t length)
263 {
264 utrd_header_t *hd;
265 cmd_upiu_t *upiu;
266 prdt_t *prdt;
267 unsigned int ulba;
268 unsigned int lba_cnt;
269 int prdt_size;
270
271
272 mmio_write_32(ufs_params.reg_base + UTRLBA,
273 utrd->header & UINT32_MAX);
274 mmio_write_32(ufs_params.reg_base + UTRLBAU,
275 (utrd->upiu >> 32) & UINT32_MAX);
276
277 hd = (utrd_header_t *)utrd->header;
278 upiu = (cmd_upiu_t *)utrd->upiu;
279
280 hd->i = 1;
281 hd->ct = CT_UFS_STORAGE;
282 hd->ocs = OCS_MASK;
283
284 upiu->trans_type = CMD_UPIU;
285 upiu->task_tag = utrd->task_tag;
286 upiu->cdb[0] = op;
287 ulba = (unsigned int)lba;
288 lba_cnt = (unsigned int)(length >> UFS_BLOCK_SHIFT);
289 switch (op) {
290 case CDBCMD_TEST_UNIT_READY:
291 break;
292 case CDBCMD_READ_CAPACITY_10:
293 hd->dd = DD_OUT;
294 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S;
295 upiu->lun = lun;
296 break;
297 case CDBCMD_READ_10:
298 hd->dd = DD_OUT;
299 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S;
300 upiu->lun = lun;
301 upiu->cdb[1] = RW_WITHOUT_CACHE;
302 /* set logical block address */
303 upiu->cdb[2] = (ulba >> 24) & 0xff;
304 upiu->cdb[3] = (ulba >> 16) & 0xff;
305 upiu->cdb[4] = (ulba >> 8) & 0xff;
306 upiu->cdb[5] = ulba & 0xff;
307 /* set transfer length */
308 upiu->cdb[7] = (lba_cnt >> 8) & 0xff;
309 upiu->cdb[8] = lba_cnt & 0xff;
310 break;
311 case CDBCMD_WRITE_10:
312 hd->dd = DD_IN;
313 upiu->flags = UPIU_FLAGS_W | UPIU_FLAGS_ATTR_S;
314 upiu->lun = lun;
315 upiu->cdb[1] = RW_WITHOUT_CACHE;
316 /* set logical block address */
317 upiu->cdb[2] = (ulba >> 24) & 0xff;
318 upiu->cdb[3] = (ulba >> 16) & 0xff;
319 upiu->cdb[4] = (ulba >> 8) & 0xff;
320 upiu->cdb[5] = ulba & 0xff;
321 /* set transfer length */
322 upiu->cdb[7] = (lba_cnt >> 8) & 0xff;
323 upiu->cdb[8] = lba_cnt & 0xff;
324 break;
325 default:
326 assert(0);
327 break;
328 }
329 if (hd->dd == DD_IN)
330 flush_dcache_range(buf, length);
331 else if (hd->dd == DD_OUT)
332 inv_dcache_range(buf, length);
333 if (length) {
334 upiu->exp_data_trans_len = htobe32(length);
335 assert(lba_cnt <= UINT16_MAX);
336 prdt = (prdt_t *)utrd->prdt;
337
338 prdt_size = 0;
339 while (length > 0) {
340 prdt->dba = (unsigned int)(buf & UINT32_MAX);
341 prdt->dbau = (unsigned int)((buf >> 32) & UINT32_MAX);
342 /* prdt->dbc counts from 0 */
343 if (length > MAX_PRDT_SIZE) {
344 prdt->dbc = MAX_PRDT_SIZE - 1;
345 length = length - MAX_PRDT_SIZE;
346 } else {
347 prdt->dbc = length - 1;
348 length = 0;
349 }
350 buf += MAX_PRDT_SIZE;
351 prdt++;
352 prdt_size += sizeof(prdt_t);
353 }
354 utrd->size_prdt = ALIGN_8(prdt_size);
355 hd->prdtl = utrd->size_prdt >> 2;
356 hd->prdto = (utrd->size_upiu + utrd->size_resp_upiu) >> 2;
357 }
358
359 flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t));
360 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
361 return 0;
362 }
363
ufs_prepare_query(utp_utrd_t * utrd,uint8_t op,uint8_t idn,uint8_t index,uint8_t sel,uintptr_t buf,size_t length)364 static int ufs_prepare_query(utp_utrd_t *utrd, uint8_t op, uint8_t idn,
365 uint8_t index, uint8_t sel,
366 uintptr_t buf, size_t length)
367 {
368 utrd_header_t *hd;
369 query_upiu_t *query_upiu;
370
371
372 hd = (utrd_header_t *)utrd->header;
373 query_upiu = (query_upiu_t *)utrd->upiu;
374
375 mmio_write_32(ufs_params.reg_base + UTRLBA,
376 utrd->header & UINT32_MAX);
377 mmio_write_32(ufs_params.reg_base + UTRLBAU,
378 (utrd->header >> 32) & UINT32_MAX);
379
380
381 hd->i = 1;
382 hd->ct = CT_UFS_STORAGE;
383 hd->ocs = OCS_MASK;
384
385 query_upiu->trans_type = QUERY_REQUEST_UPIU;
386 query_upiu->task_tag = utrd->task_tag;
387 query_upiu->ts.desc.opcode = op;
388 query_upiu->ts.desc.idn = idn;
389 query_upiu->ts.desc.index = index;
390 query_upiu->ts.desc.selector = sel;
391 switch (op) {
392 case QUERY_READ_DESC:
393 query_upiu->query_func = QUERY_FUNC_STD_READ;
394 query_upiu->ts.desc.length = htobe16(length);
395 break;
396 case QUERY_WRITE_DESC:
397 query_upiu->query_func = QUERY_FUNC_STD_WRITE;
398 query_upiu->ts.desc.length = htobe16(length);
399 memcpy((void *)(utrd->upiu + sizeof(query_upiu_t)),
400 (void *)buf, length);
401 break;
402 case QUERY_READ_ATTR:
403 case QUERY_READ_FLAG:
404 query_upiu->query_func = QUERY_FUNC_STD_READ;
405 break;
406 case QUERY_CLEAR_FLAG:
407 case QUERY_SET_FLAG:
408 query_upiu->query_func = QUERY_FUNC_STD_WRITE;
409 break;
410 case QUERY_WRITE_ATTR:
411 query_upiu->query_func = QUERY_FUNC_STD_WRITE;
412 memcpy((void *)&query_upiu->ts.attr.value, (void *)buf, length);
413 break;
414 default:
415 assert(0);
416 break;
417 }
418 flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t));
419 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
420 return 0;
421 }
422
ufs_prepare_nop_out(utp_utrd_t * utrd)423 static void ufs_prepare_nop_out(utp_utrd_t *utrd)
424 {
425 utrd_header_t *hd;
426 nop_out_upiu_t *nop_out;
427
428 mmio_write_32(ufs_params.reg_base + UTRLBA,
429 utrd->header & UINT32_MAX);
430 mmio_write_32(ufs_params.reg_base + UTRLBAU,
431 (utrd->header >> 32) & UINT32_MAX);
432
433 hd = (utrd_header_t *)utrd->header;
434 nop_out = (nop_out_upiu_t *)utrd->upiu;
435
436 hd->i = 1;
437 hd->ct = CT_UFS_STORAGE;
438 hd->ocs = OCS_MASK;
439
440 nop_out->trans_type = 0;
441 nop_out->task_tag = utrd->task_tag;
442 flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t));
443 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
444 }
445
ufs_send_request(int task_tag)446 static void ufs_send_request(int task_tag)
447 {
448 unsigned int data;
449 int slot;
450
451 slot = task_tag - 1;
452 /* clear all interrupts */
453 mmio_write_32(ufs_params.reg_base + IS, ~0);
454
455 mmio_write_32(ufs_params.reg_base + UTRLRSR, 1);
456 do {
457 data = mmio_read_32(ufs_params.reg_base + UTRLRSR);
458 } while (data == 0);
459
460 data = UTRIACR_IAEN | UTRIACR_CTR | UTRIACR_IACTH(0x1F) |
461 UTRIACR_IATOVAL(0xFF);
462 mmio_write_32(ufs_params.reg_base + UTRIACR, data);
463 /* send request */
464 mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot);
465 }
466
ufs_check_resp(utp_utrd_t * utrd,int trans_type)467 static int ufs_check_resp(utp_utrd_t *utrd, int trans_type)
468 {
469 utrd_header_t *hd;
470 resp_upiu_t *resp;
471 unsigned int data;
472 int slot;
473
474 hd = (utrd_header_t *)utrd->header;
475 resp = (resp_upiu_t *)utrd->resp_upiu;
476 inv_dcache_range((uintptr_t)hd, UFS_DESC_SIZE);
477 inv_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t));
478 do {
479 data = mmio_read_32(ufs_params.reg_base + IS);
480 if ((data & ~(UFS_INT_UCCS | UFS_INT_UTRCS)) != 0)
481 return -EIO;
482 } while ((data & UFS_INT_UTRCS) == 0);
483 slot = utrd->task_tag - 1;
484
485 data = mmio_read_32(ufs_params.reg_base + UTRLDBR);
486 assert((data & (1 << slot)) == 0);
487 assert(hd->ocs == OCS_SUCCESS);
488 assert((resp->trans_type & TRANS_TYPE_CODE_MASK) == trans_type);
489 (void)resp;
490 (void)slot;
491 return 0;
492 }
493
494 #ifdef UFS_RESP_DEBUG
dump_upiu(utp_utrd_t * utrd)495 static void dump_upiu(utp_utrd_t *utrd)
496 {
497 utrd_header_t *hd;
498 int i;
499
500 hd = (utrd_header_t *)utrd->header;
501 INFO("utrd:0x%x, ruo:0x%x, rul:0x%x, ocs:0x%x, UTRLDBR:0x%x\n",
502 (unsigned int)(uintptr_t)utrd, hd->ruo, hd->rul, hd->ocs,
503 mmio_read_32(ufs_params.reg_base + UTRLDBR));
504 for (i = 0; i < sizeof(utrd_header_t); i += 4) {
505 INFO("[%lx]:0x%x\n",
506 (uintptr_t)utrd->header + i,
507 *(unsigned int *)((uintptr_t)utrd->header + i));
508 }
509
510 for (i = 0; i < sizeof(cmd_upiu_t); i += 4) {
511 INFO("cmd[%lx]:0x%x\n",
512 utrd->upiu + i,
513 *(unsigned int *)(utrd->upiu + i));
514 }
515 for (i = 0; i < sizeof(resp_upiu_t); i += 4) {
516 INFO("resp[%lx]:0x%x\n",
517 utrd->resp_upiu + i,
518 *(unsigned int *)(utrd->resp_upiu + i));
519 }
520 for (i = 0; i < sizeof(prdt_t); i += 4) {
521 INFO("prdt[%lx]:0x%x\n",
522 utrd->prdt + i,
523 *(unsigned int *)(utrd->prdt + i));
524 }
525 }
526 #endif
527
ufs_verify_init(void)528 static void ufs_verify_init(void)
529 {
530 utp_utrd_t utrd;
531 int result;
532
533 get_utrd(&utrd);
534 ufs_prepare_nop_out(&utrd);
535 ufs_send_request(utrd.task_tag);
536 result = ufs_check_resp(&utrd, NOP_IN_UPIU);
537 assert(result == 0);
538 (void)result;
539 }
540
ufs_verify_ready(void)541 static void ufs_verify_ready(void)
542 {
543 utp_utrd_t utrd;
544 int result;
545
546 get_utrd(&utrd);
547 ufs_prepare_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0);
548 ufs_send_request(utrd.task_tag);
549 result = ufs_check_resp(&utrd, RESPONSE_UPIU);
550 assert(result == 0);
551 (void)result;
552 }
553
ufs_query(uint8_t op,uint8_t idn,uint8_t index,uint8_t sel,uintptr_t buf,size_t size)554 static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel,
555 uintptr_t buf, size_t size)
556 {
557 utp_utrd_t utrd;
558 query_resp_upiu_t *resp;
559 int result;
560
561 switch (op) {
562 case QUERY_READ_FLAG:
563 case QUERY_READ_ATTR:
564 case QUERY_READ_DESC:
565 case QUERY_WRITE_DESC:
566 case QUERY_WRITE_ATTR:
567 assert(((buf & 3) == 0) && (size != 0));
568 break;
569 default:
570 /* Do nothing in default case */
571 break;
572 }
573 get_utrd(&utrd);
574 ufs_prepare_query(&utrd, op, idn, index, sel, buf, size);
575 ufs_send_request(utrd.task_tag);
576 result = ufs_check_resp(&utrd, QUERY_RESPONSE_UPIU);
577 assert(result == 0);
578 resp = (query_resp_upiu_t *)utrd.resp_upiu;
579 #ifdef UFS_RESP_DEBUG
580 dump_upiu(&utrd);
581 #endif
582 assert(resp->query_resp == QUERY_RESP_SUCCESS);
583
584 switch (op) {
585 case QUERY_READ_FLAG:
586 *(uint32_t *)buf = (uint32_t)resp->ts.flag.value;
587 break;
588 case QUERY_READ_ATTR:
589 case QUERY_READ_DESC:
590 memcpy((void *)buf,
591 (void *)(utrd.resp_upiu + sizeof(query_resp_upiu_t)),
592 size);
593 break;
594 default:
595 /* Do nothing in default case */
596 break;
597 }
598 (void)result;
599 }
600
ufs_read_attr(int idn)601 unsigned int ufs_read_attr(int idn)
602 {
603 unsigned int value;
604
605 ufs_query(QUERY_READ_ATTR, idn, 0, 0,
606 (uintptr_t)&value, sizeof(value));
607 return value;
608 }
609
ufs_write_attr(int idn,unsigned int value)610 void ufs_write_attr(int idn, unsigned int value)
611 {
612 ufs_query(QUERY_WRITE_ATTR, idn, 0, 0,
613 (uintptr_t)&value, sizeof(value));
614 }
615
ufs_read_flag(int idn)616 unsigned int ufs_read_flag(int idn)
617 {
618 unsigned int value;
619
620 ufs_query(QUERY_READ_FLAG, idn, 0, 0,
621 (uintptr_t)&value, sizeof(value));
622 return value;
623 }
624
ufs_set_flag(int idn)625 void ufs_set_flag(int idn)
626 {
627 ufs_query(QUERY_SET_FLAG, idn, 0, 0, 0, 0);
628 }
629
ufs_clear_flag(int idn)630 void ufs_clear_flag(int idn)
631 {
632 ufs_query(QUERY_CLEAR_FLAG, idn, 0, 0, 0, 0);
633 }
634
ufs_read_desc(int idn,int index,uintptr_t buf,size_t size)635 void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size)
636 {
637 ufs_query(QUERY_READ_DESC, idn, index, 0, buf, size);
638 }
639
ufs_write_desc(int idn,int index,uintptr_t buf,size_t size)640 void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size)
641 {
642 ufs_query(QUERY_WRITE_DESC, idn, index, 0, buf, size);
643 }
644
ufs_read_capacity(int lun,unsigned int * num,unsigned int * size)645 static void ufs_read_capacity(int lun, unsigned int *num, unsigned int *size)
646 {
647 utp_utrd_t utrd;
648 resp_upiu_t *resp;
649 sense_data_t *sense;
650 unsigned char data[CACHE_WRITEBACK_GRANULE << 1];
651 uintptr_t buf;
652 int result;
653 int retry;
654
655 assert((ufs_params.reg_base != 0) &&
656 (ufs_params.desc_base != 0) &&
657 (ufs_params.desc_size >= UFS_DESC_SIZE) &&
658 (num != NULL) && (size != NULL));
659
660 /* align buf address */
661 buf = (uintptr_t)data;
662 buf = (buf + CACHE_WRITEBACK_GRANULE - 1) &
663 ~(CACHE_WRITEBACK_GRANULE - 1);
664 memset((void *)buf, 0, CACHE_WRITEBACK_GRANULE);
665 flush_dcache_range(buf, CACHE_WRITEBACK_GRANULE);
666 do {
667 get_utrd(&utrd);
668 ufs_prepare_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0,
669 buf, READ_CAPACITY_LENGTH);
670 ufs_send_request(utrd.task_tag);
671 result = ufs_check_resp(&utrd, RESPONSE_UPIU);
672 assert(result == 0);
673 #ifdef UFS_RESP_DEBUG
674 dump_upiu(&utrd);
675 #endif
676 resp = (resp_upiu_t *)utrd.resp_upiu;
677 retry = 0;
678 sense = &resp->sd.sense;
679 if (sense->resp_code == SENSE_DATA_VALID) {
680 if ((sense->sense_key == SENSE_KEY_UNIT_ATTENTION) &&
681 (sense->asc == 0x29) && (sense->ascq == 0)) {
682 retry = 1;
683 }
684 }
685 inv_dcache_range(buf, CACHE_WRITEBACK_GRANULE);
686 /* last logical block address */
687 *num = be32toh(*(unsigned int *)buf);
688 if (*num)
689 *num += 1;
690 /* logical block length in bytes */
691 *size = be32toh(*(unsigned int *)(buf + 4));
692 } while (retry);
693 (void)result;
694 }
695
ufs_read_blocks(int lun,int lba,uintptr_t buf,size_t size)696 size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size)
697 {
698 utp_utrd_t utrd;
699 resp_upiu_t *resp;
700 int result;
701
702 assert((ufs_params.reg_base != 0) &&
703 (ufs_params.desc_base != 0) &&
704 (ufs_params.desc_size >= UFS_DESC_SIZE));
705
706 memset((void *)buf, 0, size);
707 get_utrd(&utrd);
708 ufs_prepare_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size);
709 ufs_send_request(utrd.task_tag);
710 result = ufs_check_resp(&utrd, RESPONSE_UPIU);
711 assert(result == 0);
712 #ifdef UFS_RESP_DEBUG
713 dump_upiu(&utrd);
714 #endif
715 resp = (resp_upiu_t *)utrd.resp_upiu;
716 (void)result;
717 return size - resp->res_trans_cnt;
718 }
719
ufs_write_blocks(int lun,int lba,const uintptr_t buf,size_t size)720 size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size)
721 {
722 utp_utrd_t utrd;
723 resp_upiu_t *resp;
724 int result;
725
726 assert((ufs_params.reg_base != 0) &&
727 (ufs_params.desc_base != 0) &&
728 (ufs_params.desc_size >= UFS_DESC_SIZE));
729
730 memset((void *)buf, 0, size);
731 get_utrd(&utrd);
732 ufs_prepare_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size);
733 ufs_send_request(utrd.task_tag);
734 result = ufs_check_resp(&utrd, RESPONSE_UPIU);
735 assert(result == 0);
736 #ifdef UFS_RESP_DEBUG
737 dump_upiu(&utrd);
738 #endif
739 resp = (resp_upiu_t *)utrd.resp_upiu;
740 (void)result;
741 return size - resp->res_trans_cnt;
742 }
743
ufs_enum(void)744 static void ufs_enum(void)
745 {
746 unsigned int blk_num, blk_size;
747 int i;
748
749 /* 0 means 1 slot */
750 nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1;
751 if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE))
752 nutrs = ufs_params.desc_size / UFS_DESC_SIZE;
753
754 ufs_verify_init();
755 ufs_verify_ready();
756
757 ufs_set_flag(FLAG_DEVICE_INIT);
758 mdelay(200);
759 /* dump available LUNs */
760 for (i = 0; i < UFS_MAX_LUNS; i++) {
761 ufs_read_capacity(i, &blk_num, &blk_size);
762 if (blk_num && blk_size) {
763 INFO("UFS LUN%d contains %d blocks with %d-byte size\n",
764 i, blk_num, blk_size);
765 }
766 }
767 }
768
ufs_get_device_info(struct ufs_dev_desc * card_data)769 static void ufs_get_device_info(struct ufs_dev_desc *card_data)
770 {
771 uint8_t desc_buf[DESC_DEVICE_MAX_SIZE];
772
773 ufs_query(QUERY_READ_DESC, DESC_TYPE_DEVICE, 0, 0,
774 (uintptr_t)desc_buf, DESC_DEVICE_MAX_SIZE);
775
776 /*
777 * getting vendor (manufacturerID) and Bank Index in big endian
778 * format
779 */
780 card_data->wmanufacturerid = (uint16_t)((desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8) |
781 (desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]));
782 }
783
ufs_init(const ufs_ops_t * ops,ufs_params_t * params)784 int ufs_init(const ufs_ops_t *ops, ufs_params_t *params)
785 {
786 int result;
787 unsigned int data;
788 uic_cmd_t cmd;
789 struct ufs_dev_desc card = {0};
790
791 assert((params != NULL) &&
792 (params->reg_base != 0) &&
793 (params->desc_base != 0) &&
794 (params->desc_size >= UFS_DESC_SIZE));
795
796 memcpy(&ufs_params, params, sizeof(ufs_params_t));
797
798 if (ufs_params.flags & UFS_FLAGS_SKIPINIT) {
799 result = ufshc_dme_get(0x1571, 0, &data);
800 assert(result == 0);
801 result = ufshc_dme_get(0x41, 0, &data);
802 assert(result == 0);
803 if (data == 1) {
804 /* prepare to exit hibernate mode */
805 memset(&cmd, 0, sizeof(uic_cmd_t));
806 cmd.op = DME_HIBERNATE_EXIT;
807 result = ufshc_send_uic_cmd(ufs_params.reg_base,
808 &cmd);
809 assert(result == 0);
810 data = mmio_read_32(ufs_params.reg_base + UCMDARG2);
811 assert(data == 0);
812 do {
813 data = mmio_read_32(ufs_params.reg_base + IS);
814 } while ((data & UFS_INT_UHXS) == 0);
815 mmio_write_32(ufs_params.reg_base + IS, UFS_INT_UHXS);
816 data = mmio_read_32(ufs_params.reg_base + HCS);
817 assert((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL);
818 }
819 result = ufshc_dme_get(0x1568, 0, &data);
820 assert(result == 0);
821 assert((data > 0) && (data <= 3));
822 } else {
823 assert((ops != NULL) && (ops->phy_init != NULL) &&
824 (ops->phy_set_pwr_mode != NULL));
825
826 result = ufshc_reset(ufs_params.reg_base);
827 assert(result == 0);
828 ops->phy_init(&ufs_params);
829 result = ufshc_link_startup(ufs_params.reg_base);
830 assert(result == 0);
831
832 ufs_enum();
833
834 ufs_get_device_info(&card);
835 if (card.wmanufacturerid == UFS_VENDOR_SKHYNIX) {
836 ufs_params.flags |= UFS_FLAGS_VENDOR_SKHYNIX;
837 }
838
839 ops->phy_set_pwr_mode(&ufs_params);
840 }
841
842 (void)result;
843 return 0;
844 }
845