1 /******************************************************************************
2 *
3 * Copyright (C) 2022 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20
21 /**
22 *******************************************************************************
23 * @file
24 * isvce_api.c
25 *
26 * @brief
27 * Contains api function definitions for H264 encoder
28 *
29 * @author
30 * ittiam
31 *
32 * @par List of Functions:
33 * - api_check_struct_sanity()
34 * - isvce_codec_update_config()
35 * - isvce_set_default_params()
36 * - isvce_init()
37 * - isvce_get_num_rec()
38 * - isvce_fill_num_mem_rec()
39 * - isvce_init_mem_rec()
40 * - isvce_retrieve_memrec()
41 * - isvce_set_flush_mode()
42 * - isvce_get_buf_info()
43 * - isvce_set_dimensions()
44 * - isvce_set_frame_rate()
45 * - isvce_set_bit_rate()
46 * - isvce_set_frame_type()
47 * - isvce_set_qp()
48 * - isvce_set_enc_mode()
49 * - isvce_set_vbv_params()
50 * - isvc_set_air_params()
51 * - isvc_set_me_params()
52 * - isvc_set_ipe_params()
53 * - isvc_set_gop_params()
54 * - isvc_set_profile_params()
55 * - isvc_set_deblock_params()
56 * - isvce_set_num_cores()
57 * - isvce_reset()
58 * - isvce_ctl()
59 * - isvce_api_function()
60 *
61 * @remarks
62 * None
63 *
64 *******************************************************************************
65 */
66
67 /*****************************************************************************/
68 /* File Includes */
69 /*****************************************************************************/
70
71 #include <stdio.h>
72 #include <stddef.h>
73 #include <stdlib.h>
74 #include <string.h>
75 #include <limits.h>
76 #include <assert.h>
77 #include <math.h>
78 #include <stdbool.h>
79
80 #include "ih264_typedefs.h"
81 /* Dependencies of ih264_buf_mgr.h */
82 /* Dependencies of ih264_list.h */
83 #include "ih264_error.h"
84 /* Dependencies of ih264_common_tables.h */
85 #include "ih264_defs.h"
86 #include "ih264_structs.h"
87 #include "ih264_buf_mgr.h"
88 #include "ih264_common_tables.h"
89 #include "ih264_dpb_mgr.h"
90 #include "ih264_list.h"
91 #include "ih264_platform_macros.h"
92 #include "ih264_trans_data.h"
93 #include "ih264_size_defs.h"
94 /* Dependencies of ih264e_cabac_structs.h */
95 #include "ih264_cabac_tables.h"
96 /* Dependencies of ime_structs.h */
97 #include "ime_defs.h"
98 #include "ime_distortion_metrics.h"
99 /* Dependencies of ih264e_structs.h */
100 #include "iv2.h"
101 #include "ive2.h"
102 #include "ih264_defs.h"
103 #include "ih264_deblk_edge_filters.h"
104 #include "ih264_inter_pred_filters.h"
105 #include "ih264_structs.h"
106 #include "ih264_trans_quant_itrans_iquant.h"
107 /* Dependencies of ih264e_bitstream.h */
108 #include "ih264e_error.h"
109 #include "ih264e_bitstream.h"
110 #include "ih264e_cabac_structs.h"
111 #include "irc_cntrl_param.h"
112 #include "irc_frame_info_collector.h"
113 #include "ime_statistics.h"
114 #include "ime_structs.h"
115 /* Dependencies of 'ih264e_utils.h' */
116 #include "ih264e_defs.h"
117 #include "ih264e_rc_mem_interface.h"
118 #include "ih264e_structs.h"
119 #include "ih264e_utils.h"
120 #include "ih264e_version.h"
121 #include "ime.h"
122 #include "isvce.h"
123 #include "isvce_cabac.h"
124 #include "isvce_deblk.h"
125 #include "isvce_defs.h"
126 #include "isvce_downscaler.h"
127 #include "isvce_encode.h"
128 #include "isvce_encode_header.h"
129 #include "isvce_ibl_eval.h"
130 #include "isvce_ilp_mv.h"
131 #include "isvce_intra_modes_eval.h"
132 #include "isvce_me.h"
133 #include "isvce_platform_macros.h"
134 #include "isvce_rate_control.h"
135 #include "isvce_rc_mem_interface.h"
136 #include "isvce_residual_pred.h"
137 #include "isvce_sub_pic_rc.h"
138 #include "isvce_utils.h"
139
140 /*****************************************************************************/
141 /* Function Declarations */
142 /*****************************************************************************/
143
144 /*****************************************************************************/
145 /* Function Definitions */
146 /*****************************************************************************/
147
148 /**
149 *******************************************************************************
150 *
151 * @brief
152 * Used to test arguments for corresponding API call
153 *
154 * @par Description:
155 * For each command the arguments are validated
156 *
157 * @param[in] ps_handle
158 * Codec handle at API level
159 *
160 * @param[in] pv_api_ip
161 * Pointer to input structure
162 *
163 * @param[out] pv_api_op
164 * Pointer to output structure
165 *
166 * @returns error status
167 *
168 * @remarks none
169 *
170 *******************************************************************************
171 */
api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op,isvce_api_cmds_t * ps_iv_api_cmds)172 static IV_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle, void *pv_api_ip, void *pv_api_op,
173 isvce_api_cmds_t *ps_iv_api_cmds)
174 {
175 WORD32 i, j;
176
177 /* output structure expected by the api call */
178 UWORD32 *pu4_api_op = pv_api_op;
179
180 ISVCE_API_COMMAND_TYPE_T e_cmd = ps_iv_api_cmds->e_cmd;
181 ISVCE_CONTROL_API_COMMAND_TYPE_T e_ctl_cmd = ps_iv_api_cmds->e_ctl_cmd;
182
183 if(NULL == pv_api_op || NULL == pv_api_ip)
184 {
185 return (IV_FAIL);
186 }
187
188 /* set error code */
189 pu4_api_op[1] = 0;
190
191 /* error checks on handle */
192 switch(e_cmd)
193 {
194 case ISVCE_CMD_GET_NUM_MEM_REC:
195 case ISVCE_CMD_FILL_NUM_MEM_REC:
196 {
197 break;
198 }
199
200 case ISVCE_CMD_INIT:
201 {
202 if(ps_handle == NULL)
203 {
204 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
205 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
206 return IV_FAIL;
207 }
208
209 if(ps_handle->u4_size != sizeof(iv_obj_t))
210 {
211 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
212 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
213 return IV_FAIL;
214 }
215
216 break;
217 }
218 case ISVCE_CMD_RETRIEVE_MEMREC:
219 case ISVCE_CMD_VIDEO_CTL:
220 case ISVCE_CMD_VIDEO_ENCODE:
221 {
222 if(ps_handle == NULL)
223 {
224 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
225 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
226 return IV_FAIL;
227 }
228
229 if(ps_handle->u4_size != sizeof(iv_obj_t))
230 {
231 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
232 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
233 return IV_FAIL;
234 }
235
236 if(ps_handle->pv_fxns != isvce_api_function)
237 {
238 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
239 *(pu4_api_op + 1) |= IVE_ERR_API_FUNCTION_PTR_NULL;
240 return IV_FAIL;
241 }
242
243 if(ps_handle->pv_codec_handle == NULL)
244 {
245 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
246 *(pu4_api_op + 1) |= IVE_ERR_INVALID_CODEC_HANDLE;
247 return IV_FAIL;
248 }
249
250 break;
251 }
252 default:
253 {
254 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
255 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
256
257 return IV_FAIL;
258 }
259 }
260
261 /* error checks on input output structures */
262 switch(e_cmd)
263 {
264 case ISVCE_CMD_GET_NUM_MEM_REC:
265 {
266 isvce_num_mem_rec_ip_t *ps_ip = pv_api_ip;
267 isvce_num_mem_rec_op_t *ps_op = pv_api_op;
268
269 ps_op->s_ive_op.u4_error_code = 0;
270
271 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_num_mem_rec_ip_t))
272 {
273 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
274 ps_op->s_ive_op.u4_error_code |= IVE_ERR_IP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
275 return (IV_FAIL);
276 }
277
278 if(ps_op->s_ive_op.u4_size != sizeof(isvce_num_mem_rec_op_t))
279 {
280 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
281 ps_op->s_ive_op.u4_error_code |= IVE_ERR_OP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
282 return (IV_FAIL);
283 }
284
285 break;
286 }
287 case ISVCE_CMD_FILL_NUM_MEM_REC:
288 {
289 isvce_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
290 isvce_fill_mem_rec_op_t *ps_op = pv_api_op;
291
292 iv_mem_rec_t *ps_mem_rec = NULL;
293
294 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
295 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
296
297 ps_op->s_ive_op.u4_error_code = 0;
298
299 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_fill_mem_rec_ip_t))
300 {
301 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
302 ps_op->s_ive_op.u4_error_code |= IVE_ERR_IP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
303 return (IV_FAIL);
304 }
305
306 if(ps_op->s_ive_op.u4_size != sizeof(isvce_fill_mem_rec_op_t))
307 {
308 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
309 ps_op->s_ive_op.u4_error_code |= IVE_ERR_OP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
310 return (IV_FAIL);
311 }
312
313 if(max_wd < MIN_WD || max_wd > MAX_WD)
314 {
315 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
316 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
317 return (IV_FAIL);
318 }
319
320 if(max_ht < MIN_HT || max_ht > MAX_HT)
321 {
322 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
323 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
324 return (IV_FAIL);
325 }
326
327 /* verify number of mem rec ptr */
328 if(NULL == ps_ip->s_ive_ip.ps_mem_rec)
329 {
330 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
331 ps_op->s_ive_op.u4_error_code |= IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
332 return (IV_FAIL);
333 }
334
335 /* verify number of mem records */
336 if(ps_ip->s_ive_ip.u4_num_mem_rec != ISVCE_MEM_REC_CNT)
337 {
338 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
339 ps_op->s_ive_op.u4_error_code |= IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
340 return IV_FAIL;
341 }
342
343 /* check mem records sizes are correct */
344 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
345 for(i = 0; i < ISVCE_MEM_REC_CNT; i++)
346 {
347 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
348 {
349 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
350 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
351 return IV_FAIL;
352 }
353 }
354
355 break;
356 }
357 case ISVCE_CMD_INIT:
358 {
359 isvce_init_ip_t *ps_ip = pv_api_ip;
360 isvce_init_op_t *ps_op = pv_api_op;
361
362 iv_mem_rec_t *ps_mem_rec = NULL;
363
364 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
365 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
366 WORD32 wd = ALIGN16(ps_ip->u4_wd);
367 WORD32 ht = ALIGN16(ps_ip->u4_ht);
368
369 ps_op->s_ive_op.u4_error_code = 0;
370
371 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_init_ip_t))
372 {
373 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
374 ps_op->s_ive_op.u4_error_code |= IVE_ERR_IP_INIT_API_STRUCT_SIZE_INCORRECT;
375 return (IV_FAIL);
376 }
377
378 if(ps_op->s_ive_op.u4_size != sizeof(isvce_init_op_t))
379 {
380 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
381 ps_op->s_ive_op.u4_error_code |= IVE_ERR_OP_INIT_API_STRUCT_SIZE_INCORRECT;
382 return (IV_FAIL);
383 }
384
385 if(max_wd < MIN_WD || max_wd > MAX_WD)
386 {
387 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
388 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
389 return (IV_FAIL);
390 }
391
392 if(max_ht < MIN_HT || max_ht > MAX_HT)
393 {
394 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
395 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
396 return (IV_FAIL);
397 }
398
399 if(ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_PIC_CNT ||
400 ps_ip->s_ive_ip.u4_max_ref_cnt < MIN_REF_PIC_CNT)
401 {
402 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
403 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
404 return (IV_FAIL);
405 }
406
407 if(ps_ip->s_ive_ip.u4_max_reorder_cnt != 0)
408 {
409 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
410 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
411 return (IV_FAIL);
412 }
413
414 if((ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_10) &&
415 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_1B) &&
416 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_11) &&
417 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_12) &&
418 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_13) &&
419 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_20) &&
420 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_21) &&
421 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_22) &&
422 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_30) &&
423 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_31) &&
424 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_32) &&
425 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_40) &&
426 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_41) &&
427 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_42) &&
428 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_50) &&
429 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_51))
430 {
431 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
432 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
433 return (IV_FAIL);
434 }
435
436 if(ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P)
437 {
438 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
439 ps_op->s_ive_op.u4_error_code |= IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
440 return (IV_FAIL);
441 }
442
443 if(ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420P)
444 {
445 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
446 ps_op->s_ive_op.u4_error_code |= IH264E_RECON_CHROMA_FORMAT_NOT_SUPPORTED;
447 return (IV_FAIL);
448 }
449
450 if((ps_ip->s_ive_ip.e_rc_mode != IVE_RC_NONE) &&
451 (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_STORAGE) &&
452 (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_CBR_NON_LOW_DELAY))
453 {
454 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
455 ps_op->s_ive_op.u4_error_code |= IH264E_RATE_CONTROL_MODE_NOT_SUPPORTED;
456 return (IV_FAIL);
457 }
458
459 if(ps_ip->s_ive_ip.u4_max_framerate > DEFAULT_MAX_FRAMERATE)
460 {
461 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
462 ps_op->s_ive_op.u4_error_code |= IH264E_FRAME_RATE_NOT_SUPPORTED;
463 return (IV_FAIL);
464 }
465
466 for(i = 0; i < ps_ip->s_svc_inp_params.u1_num_spatial_layers; i++)
467 {
468 if(ps_ip->pu4_max_bitrate[i] > DEFAULT_MAX_BITRATE)
469 {
470 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
471 ps_op->s_ive_op.u4_error_code |= IH264E_BITRATE_NOT_SUPPORTED;
472 return (IV_FAIL);
473 }
474 }
475
476 if(ps_ip->s_ive_ip.u4_num_bframes > SVC_MAX_NUM_BFRAMES)
477 {
478 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
479 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
480 return (IV_FAIL);
481 }
482
483 if(ps_ip->s_ive_ip.u4_num_bframes && (ps_ip->s_ive_ip.u4_max_ref_cnt < 2))
484 {
485 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
486 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
487 return (IV_FAIL);
488 }
489
490 if(ps_ip->s_ive_ip.e_content_type != IV_PROGRESSIVE)
491 {
492 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
493 ps_op->s_ive_op.u4_error_code |= IH264E_CONTENT_TYPE_NOT_SUPPORTED;
494 return (IV_FAIL);
495 }
496
497 if(ps_ip->s_ive_ip.u4_max_srch_rng_x > DEFAULT_MAX_SRCH_RANGE_X)
498 {
499 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
500 ps_op->s_ive_op.u4_error_code |= IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
501 return (IV_FAIL);
502 }
503
504 if(ps_ip->s_ive_ip.u4_max_srch_rng_y > DEFAULT_MAX_SRCH_RANGE_Y)
505 {
506 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
507 ps_op->s_ive_op.u4_error_code |= IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
508 return (IV_FAIL);
509 }
510
511 if(ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_NONE)
512 {
513 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
514 ps_op->s_ive_op.u4_error_code |= IH264E_SLICE_TYPE_INPUT_INVALID;
515 return (IV_FAIL);
516 }
517
518 if(NULL == ps_ip->s_ive_ip.ps_mem_rec)
519 {
520 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
521 ps_op->s_ive_op.u4_error_code |= IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
522 return (IV_FAIL);
523 }
524
525 /* verify number of mem records */
526 if(ps_ip->s_ive_ip.u4_num_mem_rec != ISVCE_MEM_REC_CNT)
527 {
528 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
529 ps_op->s_ive_op.u4_error_code |= IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
530 return (IV_FAIL);
531 }
532
533 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
534
535 /* check memrecords sizes are correct */
536 for(i = 0; i < ((WORD32) ps_ip->s_ive_ip.u4_num_mem_rec); i++)
537 {
538 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
539 {
540 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
541 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
542 return IV_FAIL;
543 }
544
545 /* check memrecords pointers are not NULL */
546 if(ps_mem_rec[i].pv_base == NULL)
547 {
548 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
549 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_BASE_POINTER_NULL;
550 return IV_FAIL;
551 }
552 }
553
554 /* verify memtabs for overlapping regions */
555 {
556 void *start[ISVCE_MEM_REC_CNT];
557 void *end[ISVCE_MEM_REC_CNT];
558
559 start[0] = (ps_mem_rec[0].pv_base);
560 end[0] = ((UWORD8 *) ps_mem_rec[0].pv_base) + ps_mem_rec[0].u4_mem_size - 1;
561
562 for(i = 1; i < ISVCE_MEM_REC_CNT; i++)
563 {
564 /* This array is populated to check memtab overlap */
565 start[i] = (ps_mem_rec[i].pv_base);
566 end[i] = ((UWORD8 *) ps_mem_rec[i].pv_base) + ps_mem_rec[i].u4_mem_size - 1;
567
568 for(j = 0; j < i; j++)
569 {
570 if((start[i] >= start[j]) && (start[i] <= end[j]))
571 {
572 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
573 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_OVERLAP_ERR;
574 return IV_FAIL;
575 }
576
577 if((end[i] >= start[j]) && (end[i] <= end[j]))
578 {
579 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
580 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_OVERLAP_ERR;
581 return IV_FAIL;
582 }
583
584 if((start[i] < start[j]) && (end[i] > end[j]))
585 {
586 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
587 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_OVERLAP_ERR;
588 return IV_FAIL;
589 }
590 }
591 }
592 }
593
594 /* re-validate mem records with init config */
595 {
596 /* mem records */
597 iv_mem_rec_t s_mem_rec_ittiam_api[ISVCE_MEM_REC_CNT];
598
599 /* api interface structs */
600 isvce_fill_mem_rec_ip_t s_ip;
601 isvce_fill_mem_rec_op_t s_op;
602
603 /* error status */
604 IV_STATUS_T e_status;
605
606 /* temp var */
607 WORD32 i;
608
609 isvce_api_cmds_t s_api_cmds = {ISVCE_CMD_FILL_NUM_MEM_REC, ISVCE_CMD_CT_NA};
610
611 s_ip.s_ive_ip.u4_size = sizeof(isvce_fill_mem_rec_ip_t);
612 s_op.s_ive_op.u4_size = sizeof(isvce_fill_mem_rec_op_t);
613
614 s_ip.s_ive_ip.ps_mem_rec = s_mem_rec_ittiam_api;
615 s_ip.s_ive_ip.u4_max_wd = max_wd;
616 s_ip.s_ive_ip.u4_max_ht = max_ht;
617 s_ip.u4_wd = wd;
618 s_ip.u4_ht = ht;
619 s_ip.s_ive_ip.u4_num_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
620 s_ip.s_ive_ip.u4_max_level = ps_ip->s_ive_ip.u4_max_level;
621 s_ip.s_ive_ip.u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
622 s_ip.s_ive_ip.u4_max_reorder_cnt = ps_ip->s_ive_ip.u4_max_reorder_cnt;
623 s_ip.s_ive_ip.e_color_format = ps_ip->s_ive_ip.e_inp_color_fmt;
624 s_ip.s_ive_ip.u4_max_srch_rng_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
625 s_ip.s_ive_ip.u4_max_srch_rng_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
626
627 s_ip.s_svc_inp_params = ps_ip->s_svc_inp_params;
628
629 for(i = 0; i < ISVCE_MEM_REC_CNT; i++)
630 {
631 s_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
632 }
633
634 /* fill mem records */
635 e_status = isvce_api_function(NULL, (void *) &s_ip, (void *) &s_op, &s_api_cmds);
636
637 if(IV_FAIL == e_status)
638 {
639 ps_op->s_ive_op.u4_error_code = s_op.s_ive_op.u4_error_code;
640 return (IV_FAIL);
641 }
642
643 /* verify mem records */
644 for(i = 0; i < ISVCE_MEM_REC_CNT; i++)
645 {
646 if(ps_mem_rec[i].u4_mem_size < s_mem_rec_ittiam_api[i].u4_mem_size)
647 {
648 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
649 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_INSUFFICIENT_SIZE;
650
651 return IV_FAIL;
652 }
653
654 if(ps_mem_rec[i].u4_mem_alignment != s_mem_rec_ittiam_api[i].u4_mem_alignment)
655 {
656 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
657 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_ALIGNMENT_ERR;
658
659 return IV_FAIL;
660 }
661
662 if(ps_mem_rec[i].e_mem_type != s_mem_rec_ittiam_api[i].e_mem_type)
663 {
664 UWORD32 check = IV_SUCCESS;
665 UWORD32 diff =
666 s_mem_rec_ittiam_api[i].e_mem_type - ps_mem_rec[i].e_mem_type;
667
668 if((ps_mem_rec[i].e_mem_type <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM) &&
669 (s_mem_rec_ittiam_api[i].e_mem_type >=
670 IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM))
671 {
672 check = IV_FAIL;
673 }
674
675 if(3 != (s_mem_rec_ittiam_api[i].e_mem_type % 4))
676 {
677 /* It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or
678 * IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM */
679
680 if((diff < 1) || (diff > 3))
681 {
682 /* Difference between 1 and 3 is okay for all cases other than
683 * the two filtered with the MOD condition above */
684 check = IV_FAIL;
685 }
686 }
687 else
688 {
689 if(diff == 1)
690 {
691 /* This particular case is when codec asked for External
692 * Persistent, but got Internal Scratch */
693 check = IV_FAIL;
694 }
695 if((diff != 2) && (diff != 3))
696 {
697 check = IV_FAIL;
698 }
699 }
700
701 if(check == IV_FAIL)
702 {
703 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
704 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_INCORRECT_TYPE;
705
706 return IV_FAIL;
707 }
708 }
709 }
710 }
711
712 break;
713 }
714 case ISVCE_CMD_RETRIEVE_MEMREC:
715 {
716 isvce_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
717 isvce_retrieve_mem_rec_op_t *ps_op = pv_api_op;
718
719 iv_mem_rec_t *ps_mem_rec = NULL;
720
721 ps_op->s_ive_op.u4_error_code = 0;
722
723 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_retrieve_mem_rec_ip_t))
724 {
725 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
726 ps_op->s_ive_op.u4_error_code |=
727 IVE_ERR_IP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
728 return (IV_FAIL);
729 }
730
731 if(ps_op->s_ive_op.u4_size != sizeof(isvce_retrieve_mem_rec_op_t))
732 {
733 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
734 ps_op->s_ive_op.u4_error_code |=
735 IVE_ERR_OP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
736 return (IV_FAIL);
737 }
738
739 if(NULL == ps_ip->s_ive_ip.ps_mem_rec)
740 {
741 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
742 ps_op->s_ive_op.u4_error_code |= IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
743 return (IV_FAIL);
744 }
745
746 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
747
748 /* check memrecords sizes are correct */
749 for(i = 0; i < ISVCE_MEM_REC_CNT; i++)
750 {
751 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
752 {
753 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
754 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
755 return IV_FAIL;
756 }
757 }
758
759 break;
760 }
761 case ISVCE_CMD_VIDEO_ENCODE:
762 {
763 isvce_video_encode_ip_t *ps_ip = pv_api_ip;
764 isvce_video_encode_op_t *ps_op = pv_api_op;
765
766 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_video_encode_ip_t))
767 {
768 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
769 ps_op->s_ive_op.u4_error_code |= IVE_ERR_IP_ENCODE_API_STRUCT_SIZE_INCORRECT;
770 return (IV_FAIL);
771 }
772
773 if(ps_op->s_ive_op.u4_size != sizeof(isvce_video_encode_op_t))
774 {
775 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
776 ps_op->s_ive_op.u4_error_code |= IVE_ERR_OP_ENCODE_API_STRUCT_SIZE_INCORRECT;
777 return (IV_FAIL);
778 }
779
780 break;
781 }
782 case ISVCE_CMD_VIDEO_CTL:
783 {
784 switch(e_ctl_cmd)
785 {
786 case ISVCE_CMD_CTL_GET_ENC_FRAME_DIMENSIONS:
787 {
788 break;
789 }
790 case ISVCE_CMD_CTL_SETDEFAULT:
791 {
792 isvce_ctl_setdefault_ip_t *ps_ip = pv_api_ip;
793 isvce_ctl_setdefault_op_t *ps_op = pv_api_op;
794
795 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_setdefault_ip_t))
796 {
797 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
798 ps_op->s_ive_op.u4_error_code |=
799 IVE_ERR_IP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
800 return IV_FAIL;
801 }
802
803 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_setdefault_op_t))
804 {
805 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
806 ps_op->s_ive_op.u4_error_code |=
807 IVE_ERR_OP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
808 return IV_FAIL;
809 }
810
811 break;
812 }
813 case ISVCE_CMD_CTL_GETBUFINFO:
814 {
815 isvce_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
816 isvce_ctl_getbufinfo_op_t *ps_op = pv_api_op;
817
818 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_getbufinfo_ip_t))
819 {
820 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
821 ps_op->s_ive_op.u4_error_code |=
822 IVE_ERR_IP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
823 return IV_FAIL;
824 }
825
826 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_getbufinfo_op_t))
827 {
828 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
829 ps_op->s_ive_op.u4_error_code |=
830 IVE_ERR_OP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
831 return IV_FAIL;
832 }
833
834 if(ps_ip->s_ive_ip.u4_max_wd < MIN_WD)
835 {
836 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
837 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
838 return (IV_FAIL);
839 }
840
841 if(ps_ip->s_ive_ip.u4_max_ht < MIN_HT)
842 {
843 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
844 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
845 return (IV_FAIL);
846 }
847
848 if((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P) &&
849 (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE) &&
850 (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV) &&
851 (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU))
852 {
853 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
854 ps_op->s_ive_op.u4_error_code |= IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
855 return (IV_FAIL);
856 }
857
858 break;
859 }
860 case ISVCE_CMD_CTL_GETVERSION:
861 {
862 isvce_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
863 isvce_ctl_getversioninfo_op_t *ps_op = pv_api_op;
864
865 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_getversioninfo_ip_t))
866 {
867 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
868 ps_op->s_ive_op.u4_error_code |=
869 IVE_ERR_IP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
870 return IV_FAIL;
871 }
872
873 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_getversioninfo_op_t))
874 {
875 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
876 ps_op->s_ive_op.u4_error_code |=
877 IVE_ERR_OP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
878 return IV_FAIL;
879 }
880
881 if(ps_ip->s_ive_ip.pu1_version == NULL)
882 {
883 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
884 ps_op->s_ive_op.u4_error_code |= IVE_ERR_CTL_GET_VERSION_BUFFER_IS_NULL;
885 return IV_FAIL;
886 }
887
888 break;
889 }
890 case ISVCE_CMD_CTL_FLUSH:
891 {
892 isvce_ctl_flush_ip_t *ps_ip = pv_api_ip;
893 isvce_ctl_flush_op_t *ps_op = pv_api_op;
894
895 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_flush_ip_t))
896 {
897 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
898 ps_op->s_ive_op.u4_error_code |=
899 IVE_ERR_IP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
900 return IV_FAIL;
901 }
902
903 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_flush_op_t))
904 {
905 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
906 ps_op->s_ive_op.u4_error_code |=
907 IVE_ERR_OP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
908 return IV_FAIL;
909 }
910
911 break;
912 }
913 case ISVCE_CMD_CTL_RESET:
914 {
915 isvce_ctl_reset_ip_t *ps_ip = pv_api_ip;
916 isvce_ctl_reset_op_t *ps_op = pv_api_op;
917
918 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_reset_ip_t))
919 {
920 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
921 ps_op->s_ive_op.u4_error_code |=
922 IVE_ERR_IP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
923 return IV_FAIL;
924 }
925
926 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_reset_op_t))
927 {
928 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
929 ps_op->s_ive_op.u4_error_code |=
930 IVE_ERR_OP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
931 return IV_FAIL;
932 }
933
934 break;
935 }
936 case ISVCE_CMD_CTL_SET_NUM_CORES:
937 {
938 isvce_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
939 isvce_ctl_set_num_cores_op_t *ps_op = pv_api_op;
940
941 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_num_cores_ip_t))
942 {
943 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
944 ps_op->s_ive_op.u4_error_code |=
945 IVE_ERR_IP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
946 return IV_FAIL;
947 }
948
949 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_num_cores_op_t))
950 {
951 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
952 ps_op->s_ive_op.u4_error_code |=
953 IVE_ERR_OP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
954 return IV_FAIL;
955 }
956
957 if((ps_ip->s_ive_ip.u4_num_cores < 1) ||
958 (ps_ip->s_ive_ip.u4_num_cores > MAX_NUM_CORES))
959 {
960 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
961 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_NUM_CORES;
962 return IV_FAIL;
963 }
964
965 break;
966 }
967 case ISVCE_CMD_CTL_SET_DIMENSIONS:
968 {
969 isvce_codec_t *ps_codec = (isvce_codec_t *) (ps_handle->pv_codec_handle);
970
971 isvce_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
972 isvce_ctl_set_dimensions_op_t *ps_op = pv_api_op;
973
974 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_dimensions_ip_t))
975 {
976 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
977 ps_op->s_ive_op.u4_error_code |=
978 IVE_ERR_IP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
979 return IV_FAIL;
980 }
981
982 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_dimensions_op_t))
983 {
984 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
985 ps_op->s_ive_op.u4_error_code |=
986 IVE_ERR_OP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
987 return IV_FAIL;
988 }
989
990 if(ps_ip->s_ive_ip.u4_wd < MIN_WD)
991 {
992 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
993 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
994 return (IV_FAIL);
995 }
996
997 if(ps_ip->s_ive_ip.u4_wd > ps_codec->s_cfg.u4_max_wd)
998 {
999 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1000 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
1001 return (IV_FAIL);
1002 }
1003
1004 if(ps_ip->s_ive_ip.u4_ht < MIN_HT)
1005 {
1006 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1007 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
1008 return (IV_FAIL);
1009 }
1010
1011 if(ps_ip->s_ive_ip.u4_ht > ps_codec->s_cfg.u4_max_ht)
1012 {
1013 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1014 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
1015 return (IV_FAIL);
1016 }
1017
1018 if(ps_ip->s_ive_ip.u4_wd & 1)
1019 {
1020 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1021 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
1022 return (IV_FAIL);
1023 }
1024
1025 if(ps_ip->s_ive_ip.u4_ht & 1)
1026 {
1027 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1028 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
1029 return (IV_FAIL);
1030 }
1031
1032 break;
1033 }
1034 case ISVCE_CMD_CTL_SET_FRAMERATE:
1035 {
1036 isvce_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
1037 isvce_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
1038
1039 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_frame_rate_ip_t))
1040 {
1041 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1042 ps_op->s_ive_op.u4_error_code |=
1043 IVE_ERR_IP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1044 return IV_FAIL;
1045 }
1046
1047 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_frame_rate_op_t))
1048 {
1049 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1050 ps_op->s_ive_op.u4_error_code |=
1051 IVE_ERR_OP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1052 return IV_FAIL;
1053 }
1054
1055 if(((ps_ip->s_ive_ip.u4_src_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE) ||
1056 ((ps_ip->s_ive_ip.u4_tgt_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE))
1057 {
1058 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1059 ps_op->s_ive_op.u4_error_code |= IH264E_FRAME_RATE_NOT_SUPPORTED;
1060 return (IV_FAIL);
1061 }
1062
1063 if((ps_ip->s_ive_ip.u4_src_frame_rate == 0) ||
1064 (ps_ip->s_ive_ip.u4_tgt_frame_rate == 0))
1065 {
1066 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1067 ps_op->s_ive_op.u4_error_code |= IH264E_FRAME_RATE_NOT_SUPPORTED;
1068 return (IV_FAIL);
1069 }
1070
1071 if(ps_ip->s_ive_ip.u4_tgt_frame_rate > ps_ip->s_ive_ip.u4_src_frame_rate)
1072 {
1073 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1074 ps_op->s_ive_op.u4_error_code |=
1075 IH264E_TGT_FRAME_RATE_EXCEEDS_SRC_FRAME_RATE;
1076 return (IV_FAIL);
1077 }
1078
1079 break;
1080 }
1081 case ISVCE_CMD_CTL_SET_BITRATE:
1082 {
1083 isvce_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
1084 isvce_ctl_set_bitrate_op_t *ps_op = pv_api_op;
1085
1086 isvce_codec_t *ps_codec = (isvce_codec_t *) (ps_handle->pv_codec_handle);
1087
1088 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_bitrate_ip_t))
1089 {
1090 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1091 ps_op->s_ive_op.u4_error_code |=
1092 IVE_ERR_IP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1093 return IV_FAIL;
1094 }
1095
1096 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_bitrate_op_t))
1097 {
1098 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1099 ps_op->s_ive_op.u4_error_code |=
1100 IVE_ERR_OP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1101 return IV_FAIL;
1102 }
1103
1104 for(i = 0; i < ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers; i++)
1105 {
1106 if((ps_ip->pu4_target_bitrate[i] > DEFAULT_MAX_BITRATE) ||
1107 (ps_ip->pu4_target_bitrate[i] == 0))
1108 {
1109 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1110 ps_op->s_ive_op.u4_error_code |= IH264E_BITRATE_NOT_SUPPORTED;
1111 return (IV_FAIL);
1112 }
1113 }
1114
1115 break;
1116 }
1117 case ISVCE_CMD_CTL_SET_FRAMETYPE:
1118 {
1119 isvce_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
1120 isvce_ctl_set_frame_type_op_t *ps_op = pv_api_op;
1121
1122 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_frame_type_ip_t))
1123 {
1124 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1125 ps_op->s_ive_op.u4_error_code |=
1126 IVE_ERR_IP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1127 return IV_FAIL;
1128 }
1129
1130 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_frame_type_op_t))
1131 {
1132 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1133 ps_op->s_ive_op.u4_error_code |=
1134 IVE_ERR_OP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1135 return IV_FAIL;
1136 }
1137
1138 if((ps_ip->s_ive_ip.e_frame_type != IV_I_FRAME) &&
1139 (ps_ip->s_ive_ip.e_frame_type != IV_P_FRAME) &&
1140 (ps_ip->s_ive_ip.e_frame_type != IV_IDR_FRAME))
1141 {
1142 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1143 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_FORCE_FRAME_INPUT;
1144 return IV_FAIL;
1145 }
1146
1147 break;
1148 }
1149 case ISVCE_CMD_CTL_SET_ME_PARAMS:
1150 {
1151 isvce_codec_t *ps_codec = (isvce_codec_t *) (ps_handle->pv_codec_handle);
1152
1153 isvce_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
1154 isvce_ctl_set_me_params_op_t *ps_op = pv_api_op;
1155
1156 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_me_params_ip_t))
1157 {
1158 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1159 ps_op->s_ive_op.u4_error_code |=
1160 IVE_ERR_IP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1161 return IV_FAIL;
1162 }
1163
1164 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_me_params_op_t))
1165 {
1166 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1167 ps_op->s_ive_op.u4_error_code |=
1168 IVE_ERR_OP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1169 return IV_FAIL;
1170 }
1171
1172 if(ps_ip->s_ive_ip.u4_me_speed_preset != DMND_SRCH)
1173 {
1174 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1175 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_ME_SPEED_PRESET;
1176 return IV_FAIL;
1177 }
1178
1179 if((ps_ip->s_ive_ip.u4_enable_hpel != 0) &&
1180 (ps_ip->s_ive_ip.u4_enable_hpel != 1))
1181 {
1182 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1183 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_HALFPEL_OPTION;
1184 return IV_FAIL;
1185 }
1186
1187 if((ps_ip->s_ive_ip.u4_enable_qpel != 0) &&
1188 (ps_ip->s_ive_ip.u4_enable_qpel != 1))
1189 {
1190 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1191 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_QPEL_OPTION;
1192 return IV_FAIL;
1193 }
1194
1195 if((ps_ip->s_ive_ip.u4_enable_fast_sad != 0))
1196 {
1197 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1198 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_FAST_SAD_OPTION;
1199 return IV_FAIL;
1200 }
1201
1202 if(ps_ip->s_ive_ip.u4_enable_alt_ref > 0)
1203 {
1204 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1205 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_ALT_REF_OPTION;
1206 return IV_FAIL;
1207 }
1208
1209 if(ps_ip->s_ive_ip.u4_srch_rng_x > ps_codec->s_cfg.u4_max_srch_rng_x)
1210 {
1211 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1212 ps_op->s_ive_op.u4_error_code |=
1213 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
1214 return (IV_FAIL);
1215 }
1216
1217 if(ps_ip->s_ive_ip.u4_srch_rng_y > ps_codec->s_cfg.u4_max_srch_rng_y)
1218 {
1219 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1220 ps_op->s_ive_op.u4_error_code |= IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
1221 return (IV_FAIL);
1222 }
1223
1224 break;
1225 }
1226 case ISVCE_CMD_CTL_SET_IPE_PARAMS:
1227 {
1228 isvce_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
1229 isvce_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
1230
1231 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_ipe_params_ip_t))
1232 {
1233 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1234 ps_op->s_ive_op.u4_error_code |=
1235 IVE_ERR_IP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1236 return IV_FAIL;
1237 }
1238
1239 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_ipe_params_op_t))
1240 {
1241 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1242 ps_op->s_ive_op.u4_error_code |=
1243 IVE_ERR_OP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1244 return IV_FAIL;
1245 }
1246
1247 if((ps_ip->s_ive_ip.u4_enable_intra_4x4 != 0) &&
1248 (ps_ip->s_ive_ip.u4_enable_intra_4x4 != 1))
1249 {
1250 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1251 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INTRA4x4_OPTION;
1252 return IV_FAIL;
1253 }
1254
1255 if((ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_CONFIG) &&
1256 (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_SLOWEST) &&
1257 (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_NORMAL) &&
1258 (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FAST) &&
1259 (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_HIGH_SPEED) &&
1260 (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FASTEST))
1261 {
1262 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1263 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_ENC_SPEED_PRESET;
1264 return IV_FAIL;
1265 }
1266
1267 break;
1268 }
1269 case ISVCE_CMD_CTL_SET_GOP_PARAMS:
1270 {
1271 isvce_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
1272 isvce_ctl_set_gop_params_op_t *ps_op = pv_api_op;
1273
1274 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_gop_params_ip_t))
1275 {
1276 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1277 ps_op->s_ive_op.u4_error_code |=
1278 IVE_ERR_IP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1279 return IV_FAIL;
1280 }
1281
1282 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_gop_params_op_t))
1283 {
1284 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1285 ps_op->s_ive_op.u4_error_code |=
1286 IVE_ERR_OP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1287 return IV_FAIL;
1288 }
1289
1290 if((ps_ip->s_ive_ip.u4_i_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE) ||
1291 (ps_ip->s_ive_ip.u4_i_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1292 {
1293 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1294 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INTRA_FRAME_INTERVAL;
1295 return IV_FAIL;
1296 }
1297
1298 if((ps_ip->s_ive_ip.u4_idr_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE) ||
1299 (ps_ip->s_ive_ip.u4_idr_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1300 {
1301 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1302 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_IDR_FRAME_INTERVAL;
1303 return IV_FAIL;
1304 }
1305
1306 break;
1307 }
1308 case ISVCE_CMD_CTL_SET_DEBLOCK_PARAMS:
1309 {
1310 isvce_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
1311 isvce_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
1312
1313 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_deblock_params_ip_t))
1314 {
1315 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1316 ps_op->s_ive_op.u4_error_code |=
1317 IVE_ERR_IP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1318 return IV_FAIL;
1319 }
1320
1321 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_deblock_params_op_t))
1322 {
1323 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1324 ps_op->s_ive_op.u4_error_code |=
1325 IVE_ERR_OP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1326 return IV_FAIL;
1327 }
1328
1329 if((ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_0) &&
1330 (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_2) &&
1331 (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_3) &&
1332 (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_4))
1333 {
1334 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1335 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_DEBLOCKING_TYPE_INPUT;
1336 return IV_FAIL;
1337 }
1338
1339 break;
1340 }
1341 case ISVCE_CMD_CTL_SET_QP:
1342 {
1343 isvce_ctl_set_qp_ip_t *ps_ip = pv_api_ip;
1344 isvce_ctl_set_qp_op_t *ps_op = pv_api_op;
1345
1346 isvce_codec_t *ps_codec = (isvce_codec_t *) (ps_handle->pv_codec_handle);
1347
1348 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_qp_ip_t))
1349 {
1350 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1351 ps_op->s_ive_op.u4_error_code |=
1352 IVE_ERR_IP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1353 return IV_FAIL;
1354 }
1355
1356 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_qp_op_t))
1357 {
1358 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1359 ps_op->s_ive_op.u4_error_code |=
1360 IVE_ERR_OP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1361 return IV_FAIL;
1362 }
1363
1364 for(i = 0; i < ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers; i++)
1365 {
1366 if((ps_ip->pu4_i_qp_max[i] > MAX_H264_QP) ||
1367 (ps_ip->pu4_p_qp_max[i] > MAX_H264_QP) ||
1368 (ps_ip->pu4_b_qp_max[i] > MAX_H264_QP))
1369 {
1370 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1371 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_MAX_FRAME_QP;
1372 return IV_FAIL;
1373 }
1374
1375 /* We donot support QP < 4 */
1376 if((((WORD32) ps_ip->pu4_i_qp_min[i]) < MIN_H264_QP) ||
1377 ((WORD32) ps_ip->pu4_p_qp_min[i] < MIN_H264_QP) ||
1378 (((WORD32) ps_ip->pu4_b_qp_min[i]) < MIN_H264_QP) ||
1379 (ps_ip->pu4_i_qp_min[i] > ps_ip->pu4_i_qp_max[i]) ||
1380 (ps_ip->pu4_p_qp_min[i] > ps_ip->pu4_p_qp_max[i]) ||
1381 (ps_ip->pu4_b_qp_min[i] > ps_ip->pu4_b_qp_max[i]))
1382 {
1383 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1384 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_MIN_FRAME_QP;
1385 return IV_FAIL;
1386 }
1387
1388 if((ps_ip->pu4_i_qp[i] > ps_ip->pu4_i_qp_max[i]) ||
1389 (ps_ip->pu4_p_qp[i] > ps_ip->pu4_p_qp_max[i]) ||
1390 (ps_ip->pu4_b_qp[i] > ps_ip->pu4_b_qp_max[i]))
1391 {
1392 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1393 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP;
1394 return IV_FAIL;
1395 }
1396
1397 if((ps_ip->pu4_i_qp[i] < ps_ip->pu4_i_qp_min[i]) ||
1398 (ps_ip->pu4_p_qp[i] < ps_ip->pu4_p_qp_min[i]) ||
1399 (ps_ip->pu4_b_qp[i] < ps_ip->pu4_b_qp_min[i]))
1400 {
1401 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1402 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP;
1403 return IV_FAIL;
1404 }
1405 }
1406
1407 break;
1408 }
1409 case ISVCE_CMD_CTL_SET_VUI_PARAMS:
1410 {
1411 isvce_vui_ip_t *ps_ip = pv_api_ip;
1412 isvce_vui_op_t *ps_op = pv_api_op;
1413
1414 if(ps_ip->u4_size != sizeof(isvce_vui_ip_t))
1415 {
1416 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1417 ps_op->u4_error_code |= IVE_ERR_IP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT;
1418 return IV_FAIL;
1419 }
1420
1421 if(ps_op->u4_size != sizeof(isvce_vui_op_t))
1422 {
1423 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1424 ps_op->u4_error_code |= IVE_ERR_OP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT;
1425 return IV_FAIL;
1426 }
1427
1428 break;
1429 }
1430 case ISVCE_CMD_CTL_SET_SEI_MDCV_PARAMS:
1431 {
1432 isvce_ctl_set_sei_mdcv_params_ip_t *ps_ip = pv_api_ip;
1433 isvce_ctl_set_sei_mdcv_params_op_t *ps_op = pv_api_op;
1434
1435 if(ps_ip->u4_size != sizeof(isvce_ctl_set_sei_mdcv_params_ip_t))
1436 {
1437 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1438 ps_op->u4_error_code |= IVE_ERR_IP_CTL_SET_SEI_MDCV_STRUCT_SIZE_INCORRECT;
1439 return IV_FAIL;
1440 }
1441
1442 if(ps_op->u4_size != sizeof(isvce_ctl_set_sei_mdcv_params_op_t))
1443 {
1444 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1445 ps_op->u4_error_code |= IVE_ERR_OP_CTL_SET_SEI_MDCV_STRUCT_SIZE_INCORRECT;
1446 return IV_FAIL;
1447 }
1448
1449 if((ps_ip->u1_sei_mdcv_params_present_flag != 0) &&
1450 (ps_ip->u1_sei_mdcv_params_present_flag) != 1)
1451 {
1452 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1453 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1454 return IV_FAIL;
1455 }
1456
1457 if(1 == ps_ip->u1_sei_mdcv_params_present_flag)
1458 {
1459 /* Check values for u2_display_primaries_x and
1460 * u2_display_primaries_y */
1461 for(i = 0; i < 3; i++)
1462 {
1463 if((ps_ip->au2_display_primaries_x[i] >
1464 DISPLAY_PRIMARIES_X_UPPER_LIMIT) ||
1465 (ps_ip->au2_display_primaries_x[i] <
1466 DISPLAY_PRIMARIES_X_LOWER_LIMIT) ||
1467 ((ps_ip->au2_display_primaries_x[i] %
1468 DISPLAY_PRIMARIES_X_DIVISION_FACTOR) != 0))
1469 {
1470 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1471 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1472 return IV_FAIL;
1473 }
1474
1475 if((ps_ip->au2_display_primaries_y[i] >
1476 DISPLAY_PRIMARIES_Y_UPPER_LIMIT) ||
1477 (ps_ip->au2_display_primaries_y[i] <
1478 DISPLAY_PRIMARIES_Y_LOWER_LIMIT) ||
1479 ((ps_ip->au2_display_primaries_y[i] %
1480 DISPLAY_PRIMARIES_Y_DIVISION_FACTOR) != 0))
1481 {
1482 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1483 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1484 return IV_FAIL;
1485 }
1486 }
1487
1488 if((ps_ip->u2_white_point_x > WHITE_POINT_X_UPPER_LIMIT) ||
1489 (ps_ip->u2_white_point_x < WHITE_POINT_X_LOWER_LIMIT) ||
1490 ((ps_ip->u2_white_point_x % WHITE_POINT_X_DIVISION_FACTOR) != 0))
1491 {
1492 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1493 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1494 return IV_FAIL;
1495 }
1496
1497 if((ps_ip->u2_white_point_y > WHITE_POINT_Y_UPPER_LIMIT) ||
1498 (ps_ip->u2_white_point_y < WHITE_POINT_Y_LOWER_LIMIT) ||
1499 ((ps_ip->u2_white_point_y % WHITE_POINT_Y_DIVISION_FACTOR) != 0))
1500 {
1501 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1502 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1503 return IV_FAIL;
1504 }
1505
1506 if((ps_ip->u4_max_display_mastering_luminance >
1507 MAX_DISPLAY_MASTERING_LUMINANCE_UPPER_LIMIT) ||
1508 (ps_ip->u4_max_display_mastering_luminance <
1509 MAX_DISPLAY_MASTERING_LUMINANCE_LOWER_LIMIT) ||
1510 ((ps_ip->u4_max_display_mastering_luminance %
1511 MAX_DISPLAY_MASTERING_LUMINANCE_DIVISION_FACTOR) != 0))
1512 {
1513 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1514 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1515 return IV_FAIL;
1516 }
1517
1518 if((ps_ip->u4_min_display_mastering_luminance >
1519 MIN_DISPLAY_MASTERING_LUMINANCE_UPPER_LIMIT) ||
1520 (ps_ip->u4_min_display_mastering_luminance <
1521 MIN_DISPLAY_MASTERING_LUMINANCE_LOWER_LIMIT))
1522 {
1523 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1524 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1525 return IV_FAIL;
1526 }
1527
1528 if(ps_ip->u4_max_display_mastering_luminance <=
1529 ps_ip->u4_min_display_mastering_luminance)
1530 {
1531 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1532 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1533 return IV_FAIL;
1534 }
1535 }
1536
1537 break;
1538 }
1539 case ISVCE_CMD_CTL_SET_SEI_CLL_PARAMS:
1540 {
1541 isvce_ctl_set_sei_cll_params_ip_t *ps_ip = pv_api_ip;
1542 isvce_ctl_set_sei_cll_params_op_t *ps_op = pv_api_op;
1543
1544 if(ps_ip->u4_size != sizeof(isvce_ctl_set_sei_cll_params_ip_t))
1545 {
1546 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1547 ps_op->u4_error_code |= IVE_ERR_IP_CTL_SET_SEI_CLL_STRUCT_SIZE_INCORRECT;
1548 return IV_FAIL;
1549 }
1550
1551 if(ps_op->u4_size != sizeof(isvce_ctl_set_sei_cll_params_op_t))
1552 {
1553 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1554 ps_op->u4_error_code |= IVE_ERR_OP_CTL_SET_SEI_CLL_STRUCT_SIZE_INCORRECT;
1555 return IV_FAIL;
1556 }
1557
1558 if((ps_ip->u1_sei_cll_params_present_flag != 0) &&
1559 (ps_ip->u1_sei_cll_params_present_flag != 1))
1560 {
1561 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1562 ps_op->u4_error_code |= IH264E_INVALID_SEI_CLL_PARAMS;
1563 return IV_FAIL;
1564 }
1565
1566 break;
1567 }
1568 case ISVCE_CMD_CTL_SET_SEI_AVE_PARAMS:
1569 {
1570 isvce_ctl_set_sei_ave_params_ip_t *ps_ip = pv_api_ip;
1571 isvce_ctl_set_sei_ave_params_op_t *ps_op = pv_api_op;
1572
1573 if(ps_ip->u4_size != sizeof(isvce_ctl_set_sei_ave_params_ip_t))
1574 {
1575 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1576 ps_op->u4_error_code |= IVE_ERR_IP_CTL_SET_SEI_AVE_STRUCT_SIZE_INCORRECT;
1577 return IV_FAIL;
1578 }
1579
1580 if(ps_op->u4_size != sizeof(isvce_ctl_set_sei_ave_params_op_t))
1581 {
1582 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1583 ps_op->u4_error_code |= IVE_ERR_OP_CTL_SET_SEI_AVE_STRUCT_SIZE_INCORRECT;
1584 return IV_FAIL;
1585 }
1586
1587 if((ps_ip->u1_sei_ave_params_present_flag != 0) &&
1588 (ps_ip->u1_sei_ave_params_present_flag != 1))
1589 {
1590 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1591 ps_op->u4_error_code |= IH264E_INVALID_SEI_AVE_PARAMS;
1592 return IV_FAIL;
1593 }
1594
1595 if(1 == ps_ip->u1_sei_ave_params_present_flag)
1596 {
1597 if((0 == ps_ip->u4_ambient_illuminance))
1598 {
1599 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1600 ps_op->u4_error_code |= IH264E_INVALID_SEI_AVE_PARAMS;
1601 return IV_FAIL;
1602 }
1603
1604 if(ps_ip->u2_ambient_light_x > AMBIENT_LIGHT_X_UPPER_LIMIT)
1605 {
1606 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1607 ps_op->u4_error_code |= IH264E_INVALID_SEI_AVE_PARAMS;
1608 return IV_FAIL;
1609 }
1610
1611 if(ps_ip->u2_ambient_light_y > AMBIENT_LIGHT_Y_UPPER_LIMIT)
1612 {
1613 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1614 ps_op->u4_error_code |= IH264E_INVALID_SEI_AVE_PARAMS;
1615 return IV_FAIL;
1616 }
1617 }
1618
1619 break;
1620 }
1621 case ISVCE_CMD_CTL_SET_SEI_CCV_PARAMS:
1622 {
1623 isvce_ctl_set_sei_ccv_params_ip_t *ps_ip = pv_api_ip;
1624 isvce_ctl_set_sei_ccv_params_op_t *ps_op = pv_api_op;
1625
1626 if(ps_ip->u4_size != sizeof(isvce_ctl_set_sei_ccv_params_ip_t))
1627 {
1628 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1629 ps_op->u4_error_code |= IVE_ERR_IP_CTL_SET_SEI_CCV_STRUCT_SIZE_INCORRECT;
1630 return IV_FAIL;
1631 }
1632
1633 if(ps_op->u4_size != sizeof(isvce_ctl_set_sei_ccv_params_op_t))
1634 {
1635 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1636 ps_op->u4_error_code |= IVE_ERR_OP_CTL_SET_SEI_CCV_STRUCT_SIZE_INCORRECT;
1637 return IV_FAIL;
1638 }
1639
1640 if((ps_ip->u1_sei_ccv_params_present_flag != 0) &&
1641 (ps_ip->u1_sei_ccv_params_present_flag != 1))
1642 {
1643 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1644 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1645 return IV_FAIL;
1646 }
1647
1648 if(1 == ps_ip->u1_sei_ccv_params_present_flag)
1649 {
1650 if((ps_ip->u1_ccv_cancel_flag != 0) && (ps_ip->u1_ccv_cancel_flag != 1))
1651 {
1652 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1653 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1654 return IV_FAIL;
1655 }
1656
1657 if(0 == ps_ip->u1_ccv_cancel_flag)
1658 {
1659 if((ps_ip->u1_ccv_persistence_flag != 0) &&
1660 (ps_ip->u1_ccv_persistence_flag != 1))
1661 {
1662 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1663 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1664 return IV_FAIL;
1665 }
1666 if((ps_ip->u1_ccv_primaries_present_flag != 0) &&
1667 (ps_ip->u1_ccv_primaries_present_flag != 1))
1668 {
1669 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1670 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1671 return IV_FAIL;
1672 }
1673 if((ps_ip->u1_ccv_min_luminance_value_present_flag != 0) &&
1674 (ps_ip->u1_ccv_min_luminance_value_present_flag != 1))
1675 {
1676 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1677 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1678 return IV_FAIL;
1679 }
1680 if((ps_ip->u1_ccv_max_luminance_value_present_flag != 0) &&
1681 (ps_ip->u1_ccv_max_luminance_value_present_flag != 1))
1682 {
1683 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1684 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1685 return IV_FAIL;
1686 }
1687 if((ps_ip->u1_ccv_avg_luminance_value_present_flag != 0) &&
1688 (ps_ip->u1_ccv_avg_luminance_value_present_flag != 1))
1689 {
1690 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1691 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1692 return IV_FAIL;
1693 }
1694 if((ps_ip->u1_ccv_primaries_present_flag == 0) &&
1695 (ps_ip->u1_ccv_min_luminance_value_present_flag == 0) &&
1696 (ps_ip->u1_ccv_max_luminance_value_present_flag == 0) &&
1697 (ps_ip->u1_ccv_avg_luminance_value_present_flag == 0))
1698 {
1699 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1700 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1701 return IV_FAIL;
1702 }
1703
1704 if((ps_ip->u1_ccv_reserved_zero_2bits != 0))
1705 {
1706 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1707 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1708 return IV_FAIL;
1709 }
1710
1711 if(1 == ps_ip->u1_ccv_primaries_present_flag)
1712 {
1713 for(i = 0; i < 3; i++)
1714 {
1715 if((ps_ip->ai4_ccv_primaries_x[i] >
1716 CCV_PRIMARIES_X_UPPER_LIMIT) ||
1717 (ps_ip->ai4_ccv_primaries_x[i] <
1718 CCV_PRIMARIES_X_LOWER_LIMIT))
1719 {
1720 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1721 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1722 return IV_FAIL;
1723 }
1724
1725 if((ps_ip->ai4_ccv_primaries_y[i] >
1726 CCV_PRIMARIES_Y_UPPER_LIMIT) ||
1727 (ps_ip->ai4_ccv_primaries_y[i] <
1728 CCV_PRIMARIES_Y_LOWER_LIMIT))
1729 {
1730 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1731 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1732 return IV_FAIL;
1733 }
1734 }
1735 }
1736
1737 if((1 == ps_ip->u1_ccv_min_luminance_value_present_flag) &&
1738 (1 == ps_ip->u1_ccv_avg_luminance_value_present_flag))
1739 {
1740 if((ps_ip->u4_ccv_avg_luminance_value <
1741 ps_ip->u4_ccv_min_luminance_value))
1742 {
1743 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1744 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1745 return IV_FAIL;
1746 }
1747 }
1748
1749 if((1 == ps_ip->u1_ccv_min_luminance_value_present_flag) &&
1750 (1 == ps_ip->u1_ccv_max_luminance_value_present_flag))
1751 {
1752 if((ps_ip->u4_ccv_max_luminance_value <
1753 ps_ip->u4_ccv_min_luminance_value))
1754 {
1755 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1756 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1757 return IV_FAIL;
1758 }
1759 }
1760 if((1 == ps_ip->u1_ccv_avg_luminance_value_present_flag) &&
1761 (1 == ps_ip->u1_ccv_max_luminance_value_present_flag))
1762 {
1763 if((ps_ip->u4_ccv_max_luminance_value <
1764 ps_ip->u4_ccv_avg_luminance_value))
1765 {
1766 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1767 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1768 return IV_FAIL;
1769 }
1770 }
1771 }
1772 }
1773
1774 break;
1775 }
1776 case ISVCE_CMD_CTL_SET_ENC_MODE:
1777 {
1778 isvce_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
1779 isvce_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
1780
1781 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_enc_mode_ip_t))
1782 {
1783 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1784 ps_op->s_ive_op.u4_error_code |=
1785 IVE_ERR_IP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
1786 return IV_FAIL;
1787 }
1788
1789 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_enc_mode_op_t))
1790 {
1791 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1792 ps_op->s_ive_op.u4_error_code |=
1793 IVE_ERR_OP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
1794 return IV_FAIL;
1795 }
1796
1797 if((ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_HEADER) &&
1798 (ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_PICTURE))
1799 {
1800 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1801 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_ENC_OPERATION_MODE;
1802 return IV_FAIL;
1803 }
1804
1805 break;
1806 }
1807 case ISVCE_CMD_CTL_SET_VBV_PARAMS:
1808 {
1809 isvce_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
1810 isvce_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
1811
1812 isvce_codec_t *ps_codec = (isvce_codec_t *) (ps_handle->pv_codec_handle);
1813
1814 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_vbv_params_ip_t))
1815 {
1816 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1817 ps_op->s_ive_op.u4_error_code |=
1818 IVE_ERR_IP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
1819 return IV_FAIL;
1820 }
1821
1822 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_vbv_params_op_t))
1823 {
1824 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1825 ps_op->s_ive_op.u4_error_code |=
1826 IVE_ERR_OP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
1827 return IV_FAIL;
1828 }
1829
1830 for(i = 0; i < ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers; i++)
1831 {
1832 if((ps_ip->pu4_vbv_buffer_delay[i] < DEFAULT_MIN_BUFFER_DELAY) ||
1833 (ps_ip->pu4_vbv_buffer_delay[i] > DEFAULT_MAX_BUFFER_DELAY))
1834 {
1835 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1836 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_BUFFER_DELAY;
1837 return IV_FAIL;
1838 }
1839 }
1840
1841 break;
1842 }
1843 case ISVCE_CMD_CTL_SET_AIR_PARAMS:
1844 {
1845 isvce_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
1846 isvce_ctl_set_air_params_op_t *ps_op = pv_api_op;
1847
1848 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_air_params_ip_t))
1849 {
1850 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1851 ps_op->s_ive_op.u4_error_code |=
1852 IVE_ERR_IP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
1853 return IV_FAIL;
1854 }
1855
1856 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_air_params_op_t))
1857 {
1858 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1859 ps_op->s_ive_op.u4_error_code |=
1860 IVE_ERR_OP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
1861 return IV_FAIL;
1862 }
1863
1864 if((ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_NONE) &&
1865 (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_CYCLIC) &&
1866 (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_RANDOM))
1867 {
1868 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1869 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_AIR_MODE;
1870 return IV_FAIL;
1871 }
1872
1873 if(ps_ip->s_ive_ip.u4_air_refresh_period == 0)
1874 {
1875 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1876 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_AIR_REFRESH_PERIOD;
1877 return IV_FAIL;
1878 }
1879
1880 break;
1881 }
1882 case ISVCE_CMD_CTL_SET_PROFILE_PARAMS:
1883 {
1884 isvce_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
1885 isvce_ctl_set_profile_params_op_t *ps_op = pv_api_op;
1886
1887 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_profile_params_ip_t))
1888 {
1889 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1890 ps_op->s_ive_op.u4_error_code |=
1891 IVE_ERR_IP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
1892 return IV_FAIL;
1893 }
1894
1895 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_profile_params_op_t))
1896 {
1897 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1898 ps_op->s_ive_op.u4_error_code |=
1899 IVE_ERR_OP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
1900 return IV_FAIL;
1901 }
1902
1903 if(ps_ip->s_ive_ip.e_profile != IV_PROFILE_BASE &&
1904 ps_ip->s_ive_ip.e_profile != IV_PROFILE_MAIN)
1905 {
1906 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1907 ps_op->s_ive_op.u4_error_code |= IH264E_PROFILE_NOT_SUPPORTED;
1908 return IV_FAIL;
1909 }
1910
1911 if(ps_ip->s_ive_ip.u4_entropy_coding_mode > 1)
1912 {
1913 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1914 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_ENTROPY_CODING_MODE;
1915 return IV_FAIL;
1916 }
1917
1918 break;
1919 }
1920 default:
1921 {
1922 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
1923 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_SUB_CMD;
1924 return IV_FAIL;
1925 }
1926 }
1927
1928 break;
1929 }
1930 default:
1931 {
1932 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
1933 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
1934 return IV_FAIL;
1935 }
1936 }
1937
1938 return IV_SUCCESS;
1939 }
1940
1941 /**
1942 *******************************************************************************
1943 *
1944 * @brief
1945 * Sets default encoder config parameters
1946 *
1947 * @par Description:
1948 * Sets default dynamic parameters. Will be called in isvce_init() to ensure
1949 * that even if set_params is not called, codec continues to work
1950 *
1951 * @param[in] ps_cfg
1952 * Pointer to encoder config params
1953 *
1954 * @returns error status
1955 *
1956 * @remarks none
1957 *
1958 *******************************************************************************
1959 */
isvce_set_default_params(isvce_cfg_params_t * ps_cfg)1960 static WORD32 isvce_set_default_params(isvce_cfg_params_t *ps_cfg)
1961 {
1962 WORD32 ret = IV_SUCCESS;
1963 WORD32 i;
1964
1965 ps_cfg->u4_max_wd = MAX_WD;
1966 ps_cfg->u4_max_ht = MAX_HT;
1967 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
1968 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
1969 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
1970 ps_cfg->e_inp_color_fmt = IV_YUV_420SP_UV;
1971 ps_cfg->u4_enable_recon = DEFAULT_RECON_ENABLE;
1972 ps_cfg->e_recon_color_fmt = IV_YUV_420P;
1973 ps_cfg->u4_enc_speed_preset = IVE_FASTEST;
1974 ps_cfg->e_rc_mode = DEFAULT_RC;
1975 ps_cfg->u4_max_framerate = DEFAULT_MAX_FRAMERATE;
1976 ps_cfg->u4_num_bframes = DEFAULT_MAX_NUM_BFRAMES;
1977 ps_cfg->e_content_type = IV_PROGRESSIVE;
1978 ps_cfg->u4_max_srch_rng_x = DEFAULT_MAX_SRCH_RANGE_X;
1979 ps_cfg->u4_max_srch_rng_y = DEFAULT_MAX_SRCH_RANGE_Y;
1980 ps_cfg->e_slice_mode = IVE_SLICE_MODE_NONE;
1981 ps_cfg->u4_slice_param = DEFAULT_SLICE_PARAM;
1982 ps_cfg->e_arch = isvce_default_arch();
1983 ps_cfg->e_soc = SOC_GENERIC;
1984 ps_cfg->u4_disp_wd = MAX_WD;
1985 ps_cfg->u4_disp_ht = MAX_HT;
1986 ps_cfg->u4_wd = MAX_WD;
1987 ps_cfg->u4_ht = MAX_HT;
1988 ps_cfg->u4_src_frame_rate = DEFAULT_SRC_FRAME_RATE;
1989 ps_cfg->u4_tgt_frame_rate = DEFAULT_TGT_FRAME_RATE;
1990 ps_cfg->e_frame_type = IV_NA_FRAME;
1991 ps_cfg->e_enc_mode = IVE_ENC_MODE_DEFAULT;
1992 ps_cfg->e_air_mode = DEFAULT_AIR_MODE;
1993 ps_cfg->u4_air_refresh_period = DEFAULT_AIR_REFRESH_PERIOD;
1994 ps_cfg->u4_num_cores = DEFAULT_NUM_CORES;
1995 ps_cfg->u4_me_speed_preset = DEFAULT_ME_SPEED_PRESET;
1996 ps_cfg->u4_enable_hpel = DEFAULT_HPEL;
1997 ps_cfg->u4_enable_qpel = DEFAULT_QPEL;
1998 ps_cfg->u4_enable_intra_4x4 = DEFAULT_I4;
1999 ps_cfg->u4_enable_intra_8x8 = DEFAULT_I8;
2000 ps_cfg->u4_enable_intra_16x16 = DEFAULT_I16;
2001 ps_cfg->u4_enable_fast_sad = DEFAULT_ENABLE_FAST_SAD;
2002 ps_cfg->u4_enable_satqd = DEFAULT_ENABLE_SATQD;
2003 ps_cfg->i4_min_sad = (ps_cfg->u4_enable_satqd == DEFAULT_ENABLE_SATQD)
2004 ? DEFAULT_MIN_SAD_ENABLE
2005 : DEFAULT_MIN_SAD_DISABLE;
2006 ps_cfg->u4_srch_rng_x = DEFAULT_SRCH_RNG_X;
2007 ps_cfg->u4_srch_rng_y = DEFAULT_SRCH_RNG_Y;
2008 ps_cfg->u4_i_frm_interval = DEFAULT_I_INTERVAL;
2009 ps_cfg->u4_idr_frm_interval = DEFAULT_IDR_INTERVAL;
2010 ps_cfg->u4_disable_deblock_level = DEFAULT_DISABLE_DEBLK_LEVEL;
2011 ps_cfg->e_profile = DEFAULT_PROFILE;
2012 ps_cfg->u4_timestamp_low = 0;
2013 ps_cfg->u4_timestamp_high = 0;
2014 ps_cfg->u4_is_valid = 1;
2015 ps_cfg->e_cmd = ISVCE_CMD_CT_NA;
2016 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
2017 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
2018 ps_cfg->u4_entropy_coding_mode = CAVLC;
2019 ps_cfg->u4_weighted_prediction = 0;
2020 ps_cfg->u4_pic_info_type = 0;
2021 ps_cfg->u4_isvce_mb_info_type = 0;
2022 ps_cfg->s_vui.u1_video_signal_type_present_flag = 1;
2023 ps_cfg->s_vui.u1_colour_description_present_flag = 1;
2024
2025 ps_cfg->b_nalu_info_export_enable = false;
2026
2027 for(i = 0; i < MAX_NUM_SPATIAL_LAYERS; i++)
2028 {
2029 ps_cfg->au4_i_qp_max[i] = MAX_H264_QP;
2030 ps_cfg->au4_i_qp_min[i] = MIN_H264_QP;
2031 ps_cfg->au4_i_qp[i] = DEFAULT_I_QP;
2032 ps_cfg->au4_p_qp_max[i] = MAX_H264_QP;
2033 ps_cfg->au4_p_qp_min[i] = MIN_H264_QP;
2034 ps_cfg->au4_p_qp[i] = DEFAULT_P_QP;
2035 ps_cfg->au4_b_qp_max[i] = MAX_H264_QP;
2036 ps_cfg->au4_b_qp_min[i] = MIN_H264_QP;
2037 ps_cfg->au4_b_qp[i] = DEFAULT_B_QP;
2038 }
2039
2040 ps_cfg->s_svc_params.d_spatial_res_ratio = 2.0;
2041 ps_cfg->s_svc_params.u1_num_spatial_layers = 1;
2042 ps_cfg->s_svc_params.u1_num_temporal_layers = 1;
2043
2044 return ret;
2045 }
2046
2047 /**
2048 *******************************************************************************
2049 *
2050 * @brief
2051 * Initialize encoder context. This will be called by init_mem_rec and during
2052 * codec reset
2053 *
2054 * @par Description:
2055 * Initializes the context
2056 *
2057 * @param[in] ps_codec
2058 * Codec context pointer
2059 *
2060 * @returns error status
2061 *
2062 * @remarks none
2063 *
2064 *******************************************************************************
2065 */
isvce_init(isvce_codec_t * ps_codec)2066 static WORD32 isvce_init(isvce_codec_t *ps_codec)
2067 {
2068 /* enc config param set */
2069 isvce_cfg_params_t *ps_cfg = &(ps_codec->s_cfg);
2070
2071 UWORD32 i;
2072
2073 /* coded pic count */
2074 ps_codec->i4_poc = 0;
2075
2076 /* Number of API calls to encode are made */
2077 ps_codec->i4_encode_api_call_cnt = -1;
2078
2079 /* Indicates no header has been generated yet */
2080 ps_codec->u4_header_generated = 0;
2081
2082 /* Number of pictures encoded */
2083 ps_codec->i4_pic_cnt = -1;
2084
2085 /* Number of threads created */
2086 ps_codec->i4_proc_thread_cnt = 0;
2087
2088 /* ctl mutex init */
2089 ithread_mutex_init(ps_codec->pv_ctl_mutex);
2090
2091 /* Set encoder chroma format */
2092 ps_codec->e_codec_color_format =
2093 (ps_cfg->e_inp_color_fmt == IV_YUV_420SP_VU) ? IV_YUV_420SP_VU : IV_YUV_420SP_UV;
2094
2095 /* Number of continuous frames where deblocking was disabled */
2096 ps_codec->u4_disable_deblock_level_cnt = 0;
2097
2098 /* frame num */
2099 ps_codec->i4_frame_num = 0;
2100
2101 /* set the current frame type to I frame, since we are going to start
2102 * encoding*/
2103 ps_codec->force_curr_frame_type = IV_NA_FRAME;
2104
2105 /* idr_pic_id */
2106 ps_codec->i4_idr_pic_id = -1;
2107
2108 /* Flush mode */
2109 ps_codec->i4_flush_mode = 0;
2110
2111 /* Encode header mode */
2112 ps_codec->i4_header_mode = 0;
2113
2114 /* Encode generate header */
2115 ps_codec->i4_gen_header = 0;
2116
2117 /* To signal successful completion of init */
2118 ps_codec->i4_init_done = 1;
2119
2120 /* To signal that at least one picture was decoded */
2121 ps_codec->i4_first_pic_done = 0;
2122
2123 /* Reset Codec */
2124 ps_codec->i4_reset_flag = 0;
2125
2126 /* Current error code */
2127 ps_codec->i4_error_code = IH264E_SUCCESS;
2128
2129 /* threshold residue */
2130 ps_codec->u4_thres_resi = 1;
2131
2132 /* inter gating enable */
2133 ps_codec->u4_inter_gate = 0;
2134
2135 /* entropy mutex init */
2136 ithread_mutex_init(ps_codec->pv_entropy_mutex);
2137
2138 /* Process thread created status */
2139 memset(ps_codec->ai4_process_thread_created, 0, sizeof(ps_codec->ai4_process_thread_created));
2140
2141 /* Number of MBs processed together */
2142 ps_codec->i4_proc_nmb = 8;
2143
2144 /* Previous POC msb */
2145 ps_codec->i4_prev_poc_msb = 0;
2146
2147 /* Previous POC lsb */
2148 ps_codec->i4_prev_poc_lsb = -1;
2149
2150 /* max Previous POC lsb */
2151 ps_codec->i4_max_prev_poc_lsb = -1;
2152
2153 /* sps, pps status */
2154 {
2155 sps_t *ps_sps = ps_codec->ps_sps_base;
2156 pps_t *ps_pps = ps_codec->ps_pps_base;
2157
2158 for(i = 0; i < MAX_SPS_CNT; i++)
2159 {
2160 ps_sps->i1_sps_valid = 0;
2161 ps_sps++;
2162 }
2163
2164 for(i = 0; i < MAX_PPS_CNT; i++)
2165 {
2166 ps_pps->i1_pps_valid = 0;
2167 ps_pps++;
2168 }
2169 }
2170
2171 {
2172 WORD32 max_mb_rows;
2173 UWORD32 u4_ht, u4_wd;
2174
2175 isvce_get_svc_compliant_dimensions(ps_cfg->s_svc_params.u1_num_spatial_layers,
2176 ps_cfg->s_svc_params.d_spatial_res_ratio, ps_cfg->u4_wd,
2177 ps_cfg->u4_ht, &u4_wd, &u4_ht);
2178
2179 /* frame dimensions */
2180 u4_ht = ALIGN16(u4_ht);
2181 max_mb_rows = u4_ht / MB_SIZE;
2182
2183 {
2184 WORD32 clz;
2185
2186 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
2187
2188 /* Use next power of two number of entries*/
2189 clz = CLZ(num_jobs);
2190 num_jobs = 1 << (32 - clz);
2191
2192 /* init process jobq */
2193 ps_codec->pv_proc_jobq =
2194 ih264_list_init(ps_codec->pv_proc_jobq_buf, ps_codec->i4_proc_jobq_buf_size,
2195 num_jobs, sizeof(job_t), 10);
2196 RETURN_IF((ps_codec->pv_proc_jobq == NULL), IV_FAIL);
2197 ih264_list_reset(ps_codec->pv_proc_jobq);
2198
2199 /* init entropy jobq */
2200 ps_codec->pv_entropy_jobq =
2201 ih264_list_init(ps_codec->pv_entropy_jobq_buf, ps_codec->i4_entropy_jobq_buf_size,
2202 num_jobs, sizeof(job_t), 10);
2203 RETURN_IF((ps_codec->pv_entropy_jobq == NULL), IV_FAIL);
2204 ih264_list_reset(ps_codec->pv_entropy_jobq);
2205 }
2206 }
2207
2208 /* Update the jobq context to all the threads */
2209 for(i = 0; i < MAX_PROCESS_CTXT; i++)
2210 {
2211 ps_codec->as_process[i].pv_proc_jobq = ps_codec->pv_proc_jobq;
2212 ps_codec->as_process[i].pv_entropy_jobq = ps_codec->pv_entropy_jobq;
2213
2214 /* i4_id always stays between 0 and MAX_PROCESS_THREADS */
2215 ps_codec->as_process[i].i4_id = i % MAX_PROCESS_THREADS;
2216 ps_codec->as_process[i].ps_codec = ps_codec;
2217
2218 ps_codec->as_process[i].s_entropy.pv_proc_jobq = ps_codec->pv_proc_jobq;
2219 ps_codec->as_process[i].s_entropy.pv_entropy_jobq = ps_codec->pv_entropy_jobq;
2220 ps_codec->as_process[i].s_entropy.i4_abs_pic_order_cnt = -1;
2221 }
2222
2223 /* Initialize MV Bank buffer manager */
2224 ps_codec->pv_svc_au_data_store_mgr =
2225 ih264_buf_mgr_init(ps_codec->pv_svc_au_data_store_mgr_base);
2226
2227 /* Initialize Picture buffer manager for reference buffers*/
2228 ps_codec->pv_ref_buf_mgr = ih264_buf_mgr_init(ps_codec->pv_ref_buf_mgr_base);
2229
2230 /* Initialize Picture buffer manager for input buffers*/
2231 ps_codec->pv_inp_buf_mgr = ih264_buf_mgr_init(ps_codec->pv_inp_buf_mgr_base);
2232
2233 /* Initialize buffer manager for output buffers*/
2234 ps_codec->pv_out_buf_mgr = ih264_buf_mgr_init(ps_codec->pv_out_buf_mgr_base);
2235
2236 /* buffer cnt in buffer manager */
2237 ps_codec->i4_inp_buf_cnt = 0;
2238 ps_codec->i4_out_buf_cnt = 0;
2239 ps_codec->i4_ref_buf_cnt = 0;
2240
2241 ps_codec->ps_pic_buf = ps_codec->ps_pic_buf_base;
2242 memset(ps_codec->ps_pic_buf, 0, BUF_MGR_MAX_CNT * sizeof(svc_au_buf_t));
2243
2244 for(i = 0; i < BUF_MGR_MAX_CNT; i++)
2245 {
2246 isvce_svc_au_buf_init(&((svc_au_buf_t *) ps_codec->ps_pic_buf)[i], &ps_cfg->s_svc_params);
2247 }
2248
2249 /* Initialize dpb manager */
2250 ih264_dpb_mgr_init((dpb_mgr_t *) ps_codec->pv_dpb_mgr);
2251
2252 memset(ps_codec->as_ref_set, 0, sizeof(ps_codec->as_ref_set));
2253 for(i = 0; i < (sizeof(ps_codec->as_ref_set) / sizeof(ps_codec->as_ref_set[0])); i++)
2254 {
2255 ps_codec->as_ref_set[i].i4_pic_cnt = -1;
2256 }
2257
2258 /* fn ptr init */
2259 isvce_init_function_ptr(ps_codec);
2260
2261 /* reset status flags */
2262 for(i = 0; i < MAX_CTXT_SETS; i++)
2263 {
2264 ps_codec->au4_entropy_thread_active[i] = 0;
2265 ps_codec->ai4_pic_cnt[i] = -1;
2266
2267 ps_codec->s_rate_control.pre_encode_skip[i] = 0;
2268 ps_codec->s_rate_control.post_encode_skip[i] = 0;
2269 }
2270
2271 for(i = 0; i < ps_cfg->s_svc_params.u1_num_spatial_layers; i++)
2272 {
2273 ps_codec->s_rate_control.ai4_num_intra_in_prev_frame[i] = 0;
2274 ps_codec->s_rate_control.ai4_avg_activity[i] = 0;
2275 }
2276
2277 ps_codec->i4_max_num_reference_frames =
2278 MIN((gas_ih264_lvl_tbl[ih264e_get_lvl_idx(ps_codec->s_cfg.u4_max_level)].u4_max_dpb_size /
2279 (ps_codec->s_cfg.i4_wd_mbs * ps_codec->s_cfg.i4_ht_mbs)),
2280 16);
2281
2282 return IV_SUCCESS;
2283 }
2284
2285 /**
2286 *******************************************************************************
2287 *
2288 * @brief
2289 * Gets number of memory records required by the codec
2290 *
2291 * @par Description:
2292 * Gets codec memory requirements
2293 *
2294 * @param[in] pv_api_ip
2295 * Pointer to input argument structure
2296 *
2297 * @param[out] pv_api_op
2298 * Pointer to output argument structure
2299 *
2300 * @returns status
2301 *
2302 * @remarks
2303 *
2304 *******************************************************************************
2305 */
isvce_get_num_rec(void * pv_api_ip,void * pv_api_op)2306 static WORD32 isvce_get_num_rec(void *pv_api_ip, void *pv_api_op)
2307 {
2308 /* api call I/O structures */
2309 isvce_num_mem_rec_op_t *ps_op = pv_api_op;
2310
2311 UNUSED(pv_api_ip);
2312
2313 ps_op->s_ive_op.u4_num_mem_rec = ISVCE_MEM_REC_CNT;
2314
2315 return IV_SUCCESS;
2316 }
2317
2318 /**
2319 *******************************************************************************
2320 *
2321 * @brief
2322 * Fills memory records of the codec
2323 *
2324 * @par Description:
2325 * Fills codec memory requirements
2326 *
2327 * @param[in] pv_api_ip
2328 * Pointer to input argument structure
2329 *
2330 * @param[out] pv_api_op
2331 * Pointer to output argument structure
2332 *
2333 * @returns error status
2334 *
2335 * @remarks none
2336 *
2337 *******************************************************************************
2338 */
isvce_fill_num_mem_rec(void * pv_api_ip,void * pv_api_op)2339 static WORD32 isvce_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op)
2340 {
2341 isvce_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
2342 isvce_fill_mem_rec_op_t *ps_op = pv_api_op;
2343
2344 WORD32 level;
2345 WORD32 num_reorder_frames;
2346 WORD32 num_ref_frames;
2347
2348 WORD32 no_of_mem_rec;
2349 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
2350
2351 WORD32 max_wd_luma, max_ht_luma;
2352 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
2353 UWORD32 u4_wd, u4_ht;
2354
2355 WORD32 i;
2356
2357 IV_STATUS_T status = IV_SUCCESS;
2358
2359 num_reorder_frames = ps_ip->s_ive_ip.u4_max_reorder_cnt;
2360 num_ref_frames = ps_ip->s_ive_ip.u4_max_ref_cnt;
2361
2362 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
2363 no_of_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
2364
2365 isvce_get_svc_compliant_dimensions(ps_ip->s_svc_inp_params.u1_num_spatial_layers,
2366 ps_ip->s_svc_inp_params.d_spatial_res_ratio, ps_ip->u4_wd,
2367 ps_ip->u4_ht, &u4_wd, &u4_ht);
2368
2369 /* frame dimensions */
2370 max_ht_luma = ALIGN16(u4_ht);
2371 max_wd_luma = ALIGN16(u4_wd);
2372 max_mb_rows = max_ht_luma / MB_SIZE;
2373 max_mb_cols = max_wd_luma / MB_SIZE;
2374 max_mb_cnt = max_mb_rows * max_mb_cols;
2375
2376 /* profile / level info */
2377 level = ih264e_get_min_level(max_ht_luma, max_wd_luma);
2378
2379 /* Validate params */
2380 ps_op->s_ive_op.u4_error_code |= isvce_svc_au_props_validate(
2381 &ps_ip->s_svc_inp_params, ps_ip->u4_wd, ps_ip->u4_ht, u4_wd, u4_ht);
2382
2383 if(ps_op->s_ive_op.u4_error_code != IV_SUCCESS)
2384 {
2385 return IV_FAIL;
2386 }
2387
2388 if((level < MIN_LEVEL) || (level > MAX_LEVEL))
2389 {
2390 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
2391 level = MAX_LEVEL;
2392 }
2393
2394 if(num_ref_frames > MAX_REF_CNT)
2395 {
2396 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
2397 num_ref_frames = MAX_REF_CNT;
2398 }
2399
2400 if(num_reorder_frames > MAX_REF_CNT)
2401 {
2402 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
2403 num_reorder_frames = MAX_REF_CNT;
2404 }
2405
2406 /* Set all memory records as persistent and alignment as 128 by default */
2407 ps_mem_rec = ps_mem_rec_base;
2408 for(i = 0; i < no_of_mem_rec; i++)
2409 {
2410 ps_mem_rec->u4_mem_alignment = 128;
2411 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2412 ps_mem_rec++;
2413 }
2414
2415 /************************************************************************
2416 * Request memory for h264 encoder handle *
2417 ***********************************************************************/
2418 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_IV_OBJ];
2419 {
2420 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
2421 }
2422 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_IV_OBJ, ps_mem_rec->u4_mem_size);
2423
2424 /************************************************************************
2425 * Request memory for h264 encoder context *
2426 ***********************************************************************/
2427 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CODEC];
2428 {
2429 ps_mem_rec->u4_mem_size = sizeof(isvce_codec_t);
2430 }
2431 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_CODEC, ps_mem_rec->u4_mem_size);
2432
2433 /************************************************************************
2434 * Request memory for CABAC context *
2435 ***********************************************************************/
2436 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CABAC];
2437 {
2438 ps_mem_rec->u4_mem_size = sizeof(isvce_cabac_ctxt_t);
2439 }
2440 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_CABAC, ps_mem_rec->u4_mem_size);
2441
2442 /************************************************************************
2443 * Request memory for CABAC MB info *
2444 ***********************************************************************/
2445 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CABAC_MB_INFO];
2446 {
2447 ps_mem_rec->u4_mem_size = ((max_mb_cols + 1) + 1) * sizeof(isvce_mb_info_ctxt_t);
2448 }
2449 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_CABAC_MB_INFO, ps_mem_rec->u4_mem_size);
2450
2451 /************************************************************************
2452 * Request memory for entropy context *
2453 * In multi core encoding, each row is assumed to be launched on a *
2454 * thread. The rows below can only start after its neighbors are coded *
2455 * The status of an mb coded/uncoded is signaled via entropy map. *
2456 * 1. One word32 to store skip run cnt *
2457 * 2. mb entropy map (mb status entropy coded/uncoded). The size*
2458 * of the entropy map is max mb cols. Further allocate one *
2459 * more additional row to evade checking for row -1. *
2460 * 3. size of bit stream buffer to store bit stream ctxt. *
2461 * 4. Entropy coding is dependent on nnz coefficient count for *
2462 * the neighbor blocks. It is sufficient to maintain one row *
2463 * worth of nnz as entropy for lower row waits on entropy map*
2464 ************************************************************************/
2465 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ENTROPY];
2466 {
2467 /* total size of the mem record */
2468 WORD32 total_size = 0;
2469
2470 /* size of skip mb run */
2471 total_size += sizeof(WORD32);
2472 total_size = ALIGN8(total_size);
2473
2474 /* size in bytes to store entropy status of an entire frame */
2475 total_size += (max_mb_cols * max_mb_rows);
2476 /* add an additional 1 row of bytes to evade the special case of row 0 */
2477 total_size += max_mb_cols;
2478 total_size = ALIGN128(total_size);
2479
2480 /* size of bit stream buffer */
2481 total_size += sizeof(bitstrm_t);
2482 total_size = ALIGN128(total_size);
2483
2484 #if ENABLE_RE_ENC_AS_SKIP
2485 total_size += sizeof(bitstrm_t);
2486 total_size = ALIGN128(total_size);
2487 #endif
2488
2489 /* top nnz luma */
2490 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
2491 total_size = ALIGN128(total_size);
2492
2493 /* top nnz cbcr */
2494 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
2495 total_size = ALIGN128(total_size);
2496
2497 /* ps_mb_qp_ctxt */
2498 total_size += ALIGN128(sizeof(mb_qp_ctxt_t));
2499
2500 /* total size per each proc ctxt */
2501 total_size *= MAX_CTXT_SETS;
2502
2503 ps_mem_rec->u4_mem_size = total_size;
2504 }
2505 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_ENTROPY, ps_mem_rec->u4_mem_size);
2506
2507 /************************************************************************
2508 * The residue coefficients that needs to be entropy coded are packed *
2509 * at a buffer space by the proc threads. The entropy thread shall *
2510 * read from the buffer space, unpack them and encode the same. The *
2511 * buffer space required to pack a row of mbs are as follows. *
2512 * Assuming transform_8x8_flag is disabled, *
2513 * In the worst case, 1 mb contains 1 dc 4x4 luma sub block, followed *
2514 * by 16 ac 4x4 luma sub blocks, 2 dc chroma 2x2 sub blocks, followed *
2515 * by 8 ac 4x4 chroma sub blocks. *
2516 * For the sake of simplicity we assume that all sub blocks are of *
2517 * type 4x4. The packing of each 4x4 is depicted by the structure *
2518 * tu_sblk_coeff_data_t *
2519 ************************************************************************/
2520 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MB_COEFF_DATA];
2521 {
2522 /* temp var */
2523 WORD32 size = 0;
2524
2525 /* size of coeff data of 1 mb */
2526 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
2527
2528 /* size of coeff data of 1 row of mb's */
2529 size *= max_mb_cols;
2530
2531 /* align to avoid any false sharing across threads */
2532 size = ALIGN64(size);
2533
2534 /* size for one full frame */
2535 size *= max_mb_rows;
2536
2537 /* size of each proc buffer set (ping, pong) */
2538 size *= MAX_CTXT_SETS;
2539
2540 ps_mem_rec->u4_mem_size = size;
2541 }
2542 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_MB_COEFF_DATA, ps_mem_rec->u4_mem_size);
2543
2544 /************************************************************************
2545 * while encoding an mb, the mb header data is signaled to the entropy*
2546 * thread by writing to a buffer space. the size of header data per mb *
2547 * is assumed to be 40 bytes *
2548 * TODO: revisit this inference *
2549 ************************************************************************/
2550 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MB_HEADER_DATA];
2551 {
2552 /* temp var */
2553 WORD32 size;
2554
2555 /* size per MB */
2556 size = sizeof(isvce_mb_hdr_t);
2557
2558 /* size for 1 row of mbs */
2559 size = size * max_mb_cols;
2560
2561 /* align to avoid any false sharing across threads */
2562 size = ALIGN64(size);
2563
2564 /* size for one full frame */
2565 size *= max_mb_rows;
2566
2567 /* size of each proc buffer set (ping, pong) */
2568 size *= MAX_CTXT_SETS;
2569
2570 ps_mem_rec->u4_mem_size = size;
2571 }
2572 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_MB_HEADER_DATA, ps_mem_rec->u4_mem_size);
2573
2574 /************************************************************************
2575 * While encoding inter slices, to compute the cost of encoding an mb *
2576 * with the mv's at hand, we employ the expression cost = sad + lambda *
2577 * x mv_bits. Here mv_bits is the total number of bits taken to represe*
2578 * nt the mv in the stream. The mv bits for all the possible mv are *
2579 * stored in the look up table. The mem record for this look up table *
2580 * is given below. *
2581 ************************************************************************/
2582 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MVBITS];
2583 {
2584 /* max srch range x */
2585 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
2586
2587 /* max srch range y */
2588 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
2589
2590 /* max srch range */
2591 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
2592
2593 /* due to subpel */
2594 u4_max_srch_range <<= 2;
2595
2596 /* due to mv on either direction */
2597 u4_max_srch_range = (u4_max_srch_range << 1);
2598
2599 /* due to pred mv + zero */
2600 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
2601
2602 u4_max_srch_range = ALIGN128(u4_max_srch_range);
2603
2604 ps_mem_rec->u4_mem_size = u4_max_srch_range;
2605 }
2606 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_MVBITS, ps_mem_rec->u4_mem_size);
2607
2608 /************************************************************************
2609 * Request memory for SPS *
2610 ***********************************************************************/
2611 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SPS];
2612 {
2613 ps_mem_rec->u4_mem_size = MAX_SPS_CNT * sizeof(sps_t);
2614 }
2615 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_SPS, ps_mem_rec->u4_mem_size);
2616
2617 /************************************************************************
2618 * Request memory for PPS *
2619 ***********************************************************************/
2620 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PPS];
2621 {
2622 ps_mem_rec->u4_mem_size = MAX_PPS_CNT * sizeof(pps_t);
2623 }
2624 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_PPS, ps_mem_rec->u4_mem_size);
2625
2626 /************************************************************************
2627 * Request memory for SVC NALU Extension *
2628 ************************************************************************/
2629 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SVC_NALU_EXT];
2630 {
2631 /* 2 implies allocation for NAL_PREFIX and NAL_CODED_SLICE_EXTENSION */
2632 ps_mem_rec->u4_mem_size =
2633 2 * MAX_CTXT_SETS * SVC_MAX_SLICE_HDR_CNT * sizeof(svc_nalu_ext_t);
2634 }
2635 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_SVC_NALU_EXT, ps_mem_rec->u4_mem_size);
2636
2637 /************************************************************************
2638 * Request memory for subset SPS *
2639 ************************************************************************/
2640 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SUBSET_SPS];
2641 {
2642 ps_mem_rec->u4_mem_size =
2643 MAX_SPS_CNT * ps_ip->s_svc_inp_params.u1_num_spatial_layers * sizeof(subset_sps_t);
2644 }
2645 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_SUBSET_SPS, ps_mem_rec->u4_mem_size);
2646
2647 /************************************************************************
2648 * Request memory for Slice Header *
2649 ***********************************************************************/
2650 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SLICE_HDR];
2651 {
2652 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS * SVC_MAX_SLICE_HDR_CNT * sizeof(slice_header_t);
2653 }
2654 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_SLICE_HDR, ps_mem_rec->u4_mem_size);
2655
2656 /************************************************************************
2657 * Request memory for SVC Slice Header *
2658 ***********************************************************************/
2659 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SVC_SLICE_HDR];
2660 {
2661 ps_mem_rec->u4_mem_size =
2662 MAX_CTXT_SETS * SVC_MAX_SLICE_HDR_CNT * sizeof(svc_slice_header_t);
2663 }
2664 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_SVC_SLICE_HDR, ps_mem_rec->u4_mem_size);
2665
2666 /************************************************************************
2667 * Request memory for Adaptive Intra Refresh *
2668 ***********************************************************************/
2669 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_AIR_MAP];
2670 {
2671 /* total size of the mem record */
2672 WORD32 total_size = 0;
2673
2674 /* intra coded map */
2675 total_size += max_mb_cnt;
2676 total_size *= MAX_CTXT_SETS;
2677
2678 /* mb refresh map */
2679 total_size += sizeof(UWORD16) * max_mb_cnt;
2680
2681 /* alignment */
2682 total_size = ALIGN128(total_size);
2683
2684 ps_mem_rec->u4_mem_size = total_size;
2685 }
2686 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_AIR_MAP, ps_mem_rec->u4_mem_size);
2687
2688 /************************************************************************
2689 * In multi slice encoding, this memory record helps tracking the start*
2690 * of slice with reference to mb. *
2691 * MEM RECORD for holding *
2692 * 1. mb slice map *
2693 ************************************************************************/
2694 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SLICE_MAP];
2695 {
2696 /* total size of the mem record */
2697 WORD32 total_size = 0;
2698
2699 /* size in bytes to slice index of all mbs of a frame */
2700 total_size = ALIGN64(max_mb_cnt);
2701
2702 /* isvce_update_proc_ctxt can overread by 1 at the end */
2703 total_size += 1;
2704
2705 /* total size per each proc ctxt */
2706 total_size *= MAX_CTXT_SETS;
2707 ps_mem_rec->u4_mem_size = total_size;
2708 }
2709 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_SLICE_MAP, ps_mem_rec->u4_mem_size);
2710
2711 /************************************************************************
2712 * Request memory to hold thread handles for each processing thread *
2713 ************************************************************************/
2714 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_THREAD_HANDLE];
2715 {
2716 WORD32 handle_size = ithread_get_handle_size();
2717
2718 ps_mem_rec->u4_mem_size = MAX_PROCESS_THREADS * handle_size;
2719 }
2720 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_THREAD_HANDLE, ps_mem_rec->u4_mem_size);
2721
2722 /************************************************************************
2723 * Request memory to hold mutex for control calls *
2724 ************************************************************************/
2725 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CTL_MUTEX];
2726 {
2727 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
2728 }
2729 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_CTL_MUTEX, ps_mem_rec->u4_mem_size);
2730
2731 /************************************************************************
2732 * Request memory to hold mutex for entropy calls *
2733 ************************************************************************/
2734 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ENTROPY_MUTEX];
2735 {
2736 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
2737 }
2738 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_ENTROPY_MUTEX, ps_mem_rec->u4_mem_size);
2739
2740 /************************************************************************
2741 * Request memory to hold process jobs *
2742 ***********************************************************************/
2743 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PROC_JOBQ];
2744 {
2745 /* One process job per row of MBs */
2746 /* Allocate for two pictures, so that wrap around can be handled easily */
2747 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
2748
2749 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
2750
2751 ps_mem_rec->u4_mem_size = job_queue_size;
2752 }
2753 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_PROC_JOBQ, ps_mem_rec->u4_mem_size);
2754
2755 /************************************************************************
2756 * Request memory to hold entropy jobs *
2757 ***********************************************************************/
2758 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ENTROPY_JOBQ];
2759 {
2760 /* One process job per row of MBs */
2761 /* Allocate for two pictures, so that wrap around can be handled easily */
2762 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
2763
2764 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
2765
2766 ps_mem_rec->u4_mem_size = job_queue_size;
2767 }
2768 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_ENTROPY_JOBQ, ps_mem_rec->u4_mem_size);
2769
2770 /************************************************************************
2771 * In multi core encoding, each row is assumed to be launched on a *
2772 * thread. The rows below can only start after its neighbors are coded *
2773 * The status of an mb coded/uncoded is signaled via proc map. *
2774 * MEM RECORD for holding *
2775 * 1. mb proc map (mb status core coded/uncoded) *
2776 ************************************************************************/
2777 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PROC_MAP];
2778 {
2779 /* total size of the mem record */
2780 WORD32 total_size = 0;
2781
2782 /* size in bytes to mb core coding status of an entire frame */
2783 total_size = max_mb_cnt;
2784
2785 /* add an additional 1 row of bytes to evade the special case of row 0 */
2786 total_size += max_mb_cols;
2787
2788 /* total size per each proc ctxt */
2789 total_size *= MAX_CTXT_SETS;
2790 ps_mem_rec->u4_mem_size = total_size;
2791 }
2792 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_PROC_MAP, ps_mem_rec->u4_mem_size);
2793
2794 /************************************************************************
2795 * mem record for holding a particular MB is deblocked or not *
2796 * 1. mb deblk map (mb status deblocked/not deblocked) *
2797 ************************************************************************/
2798 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_DBLK_MAP];
2799 {
2800 /* total size of the mem record */
2801 WORD32 total_size = 0;
2802
2803 /* size in bytes to mb core coding status of an entire frame */
2804 total_size = max_mb_cnt;
2805
2806 /* add an additional 1 row of bytes to evade the special case of row 0 */
2807 total_size += max_mb_cols;
2808
2809 total_size = ALIGN64(total_size);
2810
2811 /* total size per each proc ctxt */
2812 total_size *= MAX_CTXT_SETS;
2813 ps_mem_rec->u4_mem_size = total_size;
2814 }
2815 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_DBLK_MAP, ps_mem_rec->u4_mem_size);
2816
2817 /************************************************************************
2818 * mem record for holding a particular MB's me is done or not *
2819 * 1. mb me map *
2820 ************************************************************************/
2821 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ME_MAP];
2822 {
2823 /* total size of the mem record */
2824 WORD32 total_size = 0;
2825
2826 /* size in bytes to mb core coding status of an entire frame */
2827 total_size = max_mb_cnt;
2828
2829 /* add an additional 1 row of bytes to evade the special case of row 0 */
2830 total_size += max_mb_cols;
2831
2832 /* total size per each proc ctxt */
2833 total_size *= MAX_CTXT_SETS;
2834
2835 ps_mem_rec->u4_mem_size = total_size;
2836 }
2837 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_ME_MAP, ps_mem_rec->u4_mem_size);
2838
2839 /************************************************************************
2840 * size for holding dpb manager context *
2841 ************************************************************************/
2842 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_DPB_MGR];
2843 {
2844 ps_mem_rec->u4_mem_size = sizeof(dpb_mgr_t);
2845 }
2846 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_DPB_MGR, ps_mem_rec->u4_mem_size);
2847
2848 /************************************************************************
2849 * luma or chroma core coding involves mb estimation, error computation*
2850 * between the estimated singnal and the actual signal, transform the *
2851 * error, quantize the error, then inverse transform and inverse quant *
2852 * ize the residue and add the result back to estimated signal. *
2853 * To perform all these, a set of temporary buffers are needed. *
2854 * MEM RECORD for holding scratch buffers *
2855 * 1. prediction buffer used during mb mode analysis *
2856 * 2 temp. reference buffer when intra 4x4 with rdopt on is *
2857 * enabled *
2858 * - when intra 4x4 is enabled, rdopt is on, to store the *
2859 * reconstructed values and use them later this temp. buffer *
2860 * is used. *
2861 * 3. prediction buffer used during intra mode analysis *
2862 * 4. prediction buffer used during intra 16x16 plane mode *
2863 * analysis
2864 * 5. prediction buffer used during intra chroma mode analysis *
2865 * 6. prediction buffer used during intra chroma 16x16 plane *
2866 * mode analysis
2867 * 7. forward transform output buffer *
2868 * - to store the error between estimated and the actual inp *
2869 * ut and to store the fwd transformed quantized output *
2870 * 8. forward transform output buffer *
2871 * - when intra 4x4 is enabled, rdopt is on, to store the *
2872 * fwd transform values and use them later this temp. buffer *
2873 * is used. *
2874 * 9. temporary buffer for inverse transform *
2875 * - temporary buffer used in inverse transform and inverse *
2876 * quantization *
2877 * A. Buffers for holding half_x , half_y and half_xy planes *
2878 ************************************************************************/
2879 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PROC_SCRATCH];
2880 {
2881 WORD32 total_size = 0;
2882 WORD32 i4_tmp_size;
2883
2884 /* size to hold prediction buffer */
2885 total_size += sizeof(UWORD8) * 16 * 16;
2886 total_size = ALIGN64(total_size);
2887
2888 /* size to hold recon for intra 4x4 buffer */
2889 total_size += sizeof(UWORD8) * 16 * 16;
2890 total_size = ALIGN64(total_size);
2891
2892 /* prediction buffer intra 16x16 */
2893 total_size += sizeof(UWORD8) * 16 * 16;
2894 total_size = ALIGN64(total_size);
2895
2896 /* prediction buffer intra 16x16 plane*/
2897 total_size += sizeof(UWORD8) * 16 * 16;
2898 total_size = ALIGN64(total_size);
2899
2900 /* prediction buffer intra chroma*/
2901 total_size += sizeof(UWORD8) * 16 * 8;
2902 total_size = ALIGN64(total_size);
2903
2904 /* prediction buffer intra chroma plane*/
2905 total_size += sizeof(UWORD8) * 16 * 8;
2906 total_size = ALIGN64(total_size);
2907
2908 /* size to hold fwd transform output */
2909 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
2910 total_size = ALIGN64(total_size);
2911
2912 /* size to hold fwd transform output */
2913 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
2914 total_size = ALIGN64(total_size);
2915
2916 /* size to hold temporary data during inverse transform */
2917 total_size += sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
2918 total_size = ALIGN64(total_size);
2919
2920 /* Buffers for holding half_x , half_y and half_xy planes */
2921 i4_tmp_size = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
2922 total_size += (ALIGN64(i4_tmp_size) * SUBPEL_BUFF_CNT);
2923
2924 /* Allocate for each process thread */
2925 total_size *= MAX_PROCESS_CTXT;
2926
2927 ps_mem_rec->u4_mem_size = total_size;
2928 }
2929 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_PROC_SCRATCH, ps_mem_rec->u4_mem_size);
2930
2931 /************************************************************************
2932 * When transform_8x8_flag is disabled, the size of a sub block is *
2933 * 4x4 and when the transform_8x8_flag is enabled the size of the sub *
2934 * block is 8x8. The threshold matrix and the forward scaling list *
2935 * is of the size of the sub block. *
2936 * MEM RECORD for holding *
2937 * 1. quantization parameters for plane y, cb, cr *
2938 * - threshold matrix for quantization *
2939 * - forward weight matrix *
2940 * - satqd threshold matrix *
2941 ************************************************************************/
2942 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_QUANT_PARAM];
2943 {
2944 /* total size of the mem record */
2945 WORD32 total_size = 0;
2946
2947 /* quantization parameter list for planes y,cb and cr */
2948 total_size += ALIGN64(sizeof(quant_params_t)) * 3;
2949
2950 /* size of threshold matrix for quantization
2951 * (assuming the transform_8x8_flag is disabled).
2952 * for all 3 planes */
2953 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
2954
2955 /* size of forward weight matrix for quantization
2956 * (assuming the transform_8x8_flag is disabled).
2957 * for all 3 planes */
2958 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
2959
2960 /* Size for SATDQ threshold matrix for palnes y, cb and cr */
2961 total_size += ALIGN64(sizeof(UWORD16) * 9) * 3;
2962
2963 total_size = ALIGN128(total_size);
2964
2965 /* total size per each proc thread */
2966 total_size *= MAX_PROCESS_CTXT;
2967
2968 ps_mem_rec->u4_mem_size = total_size;
2969 }
2970 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_QUANT_PARAM, ps_mem_rec->u4_mem_size);
2971
2972 /************************************************************************
2973 * While computing blocking strength for the current mb, the csbp, mb *
2974 * type for the neighboring mbs are necessary. memtab for storing top *
2975 * row mbtype and csbp is evaluated here. *
2976 * *
2977 * when encoding intra 4x4 or intra 8x8 the submb types are estimated *
2978 * and sent. The estimation is dependent on neighbor mbs. For this *
2979 * store the top row sub mb types for intra mbs *
2980 * *
2981 * During motion vector prediction, the curr mb mv is predicted from *
2982 * neigbors left, top, top right and sometimes top left depending on *
2983 * the availability. The top and top right content is accessed from *
2984 * the memtab specified below. *
2985 ************************************************************************/
2986 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_TOP_ROW_SYN_INFO];
2987 {
2988 UWORD32 total_size = isvce_get_svc_nbr_info_buf_size(
2989 ps_ip->s_svc_inp_params.u1_num_spatial_layers,
2990 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
2991
2992 total_size = ALIGN128(total_size);
2993 ps_mem_rec->u4_mem_size = total_size;
2994 }
2995 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_TOP_ROW_SYN_INFO, ps_mem_rec->u4_mem_size);
2996
2997 /************************************************************************
2998 * When transform_8x8_flag is disabled, the mb is partitioned into *
2999 * 4 sub blocks. This corresponds to 1 vertical left edge and 1 *
3000 * vertical inner edge, 1 horizontal top edge and 1 horizontal *
3001 * inner edge per mb. Further, When transform_8x8_flag is enabled, *
3002 * the mb is partitioned in to 16 sub blocks. This corresponds to *
3003 * 1 vertical left edge and 3 vertical inner edges, 1 horizontal top *
3004 * edge and 3 horizontal inner edges per mb. *
3005 * MEM RECORD for holding *
3006 * 1. vertical edge blocking strength *
3007 * 2. horizontal edge blocking strength *
3008 * 3. mb qp *
3009 * all are frame level *
3010 ************************************************************************/
3011 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_BS_QP];
3012 {
3013 /* total size of the mem record */
3014 WORD32 total_size = 0;
3015
3016 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of
3017 * every mb*/
3018 WORD32 vert_bs_size, horz_bs_size, qp_size;
3019
3020 /* vertical edge bs = total number of vertical edges * number of bytes per
3021 * each edge */
3022 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
3023 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing
3024 * bs */
3025 vert_bs_size = 2 * ALIGN64(max_mb_cnt * 4 * 4);
3026
3027 /* horizontal edge bs = total number of horizontal edges * number of bytes
3028 * per each edge */
3029 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
3030 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing
3031 * bs */
3032 horz_bs_size = 2 * ALIGN64(max_mb_cnt * 4 * 4);
3033
3034 /* qp of each mb requires 1 byte */
3035 qp_size = ALIGN64(max_mb_cnt);
3036
3037 /* total size */
3038 total_size = vert_bs_size + horz_bs_size + qp_size;
3039
3040 /* total size per each proc ctxt */
3041 total_size *= MAX_CTXT_SETS;
3042
3043 ps_mem_rec->u4_mem_size = total_size;
3044 }
3045 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_BS_QP, ps_mem_rec->u4_mem_size);
3046
3047 /************************************************************************
3048 * size for holding input pic buf *
3049 ************************************************************************/
3050 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_INP_PIC];
3051 {
3052 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3053 }
3054 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_INP_PIC, ps_mem_rec->u4_mem_size);
3055
3056 /************************************************************************
3057 * size for holding putput pic buf *
3058 ************************************************************************/
3059 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_OUT];
3060 {
3061 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3062 }
3063 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_OUT, ps_mem_rec->u4_mem_size);
3064
3065 /************************************************************************
3066 * Size for color space conversion *
3067 ************************************************************************/
3068 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CSC];
3069 {
3070 /* We need a total a memory for a single frame of 420 sp, ie
3071 * (wd * ht) for luma and (wd * ht / 2) for chroma*/
3072 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS * ((3 * max_ht_luma * max_wd_luma) >> 1);
3073 /* Allocate an extra row, since inverse transform functions for
3074 * chroma access(only read, not used) few extra bytes due to
3075 * interleaved input
3076 */
3077 ps_mem_rec->u4_mem_size += max_wd_luma;
3078 }
3079 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_CSC, ps_mem_rec->u4_mem_size);
3080
3081 /************************************************************************
3082 * Size for holding pic_buf_t for each reference picture *
3083 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
3084 * MAX_DPB_SIZE or max_dpb_size for following reasons *
3085 * max_dpb_size will be based on max_wd and max_ht *
3086 * For higher max_wd and max_ht this number will be smaller than *
3087 * MAX_DPB_SIZE But during actual initialization number of buffers *
3088 * allocated can be more. *
3089 * *
3090 * Also to handle display depth application can allocate more than *
3091 * what codec asks for in case of non-shared mode *
3092 * Since this is only a structure allocation and not actual buffer *
3093 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
3094 ************************************************************************/
3095 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_REF_PIC];
3096 {
3097 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3098 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(svc_au_buf_t);
3099
3100 /************************************************************************
3101 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
3102 * is set to maximum number of luma samples allowed at the given level. *
3103 * This is done to ensure that any stream with width and height lesser *
3104 * than max_wd and max_ht is supported. Number of buffers required can *
3105 * be greater for lower width and heights at a given level and this *
3106 * increased number of buffers might require more memory than what *
3107 * max_wd and max_ht buffer would have required. Number of buffers is *
3108 * doubled in order to return one frame at a time instead of sending *
3109 * multiple outputs during dpb full case. Also note one extra buffer is *
3110 * allocted to store current picture. *
3111 * *
3112 * Half-pel planes for each reference buffer are allocated along with *
3113 * the reference buffer. So each reference buffer is 4 times the *
3114 * required size. This way buffer management for the half-pel planes is *
3115 * easier and while using the half-pel planes in MC, an offset can be *
3116 * used from a single pointer *
3117 ***********************************************************************/
3118 ps_mem_rec->u4_mem_size +=
3119 HPEL_PLANES_CNT * isvce_get_total_svc_au_buf_size(&ps_ip->s_svc_inp_params,
3120 u4_wd * u4_ht, level, PAD_WD, PAD_HT,
3121 num_ref_frames, num_reorder_frames);
3122 }
3123 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_REF_PIC, ps_mem_rec->u4_mem_size);
3124
3125 /************************************************************************
3126 * Size for holding svc_au_data_t for each MV Bank. *
3127 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
3128 * MAX_DPB_SIZE or max_dpb_size for following reasons *
3129 * max_dpb_size will be based on max_wd and max_ht *
3130 * For higher max_wd and max_ht this number will be smaller than *
3131 * MAX_DPB_SIZE But during actual initialization number of buffers *
3132 * allocated can be more. *
3133 * *
3134 * One extra MV Bank is needed to hold current pics MV bank. *
3135 * Since this is only a structure allocation and not actual buffer *
3136 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
3137 ************************************************************************/
3138 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MVBANK];
3139 {
3140 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3141
3142 /************************************************************************
3143 * Allocate for pu_map, isvce_enc_pu_t and pic_pu_idx for each MV bank *
3144 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
3145 * is set to maximum number of luma samples allowed at the given level. *
3146 * This is done to ensure that any stream with width and height lesser *
3147 * than max_wd and max_ht is supported. Number of buffers required can *
3148 * be greater for lower width and heights at a given level and this *
3149 * increased number of buffers might require more memory than what *
3150 * max_wd and max_ht buffer would have required Also note one extra *
3151 * buffer is allocated to store current pictures MV bank. *
3152 ***********************************************************************/
3153
3154 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(svc_au_data_t);
3155
3156 ps_mem_rec->u4_mem_size +=
3157 (num_ref_frames + num_reorder_frames + ps_ip->s_svc_inp_params.u1_num_temporal_layers +
3158 MAX_CTXT_SETS) *
3159 isvce_get_total_svc_au_data_size(u4_wd * u4_ht,
3160 ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3161 ps_ip->s_svc_inp_params.d_spatial_res_ratio);
3162 }
3163 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_MVBANK, ps_mem_rec->u4_mem_size);
3164
3165 /************************************************************************
3166 * Request memory to hold mem recs to be returned during retrieve call *
3167 ************************************************************************/
3168 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_BACKUP];
3169 {
3170 ps_mem_rec->u4_mem_size = ISVCE_MEM_REC_CNT * sizeof(iv_mem_rec_t);
3171 }
3172 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_BACKUP, ps_mem_rec->u4_mem_size);
3173
3174 /************************************************************************
3175 * size for memory required by NMB info structs and buffer for storing *
3176 * half pel plane *
3177 ************************************************************************/
3178 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MB_INFO_NMB];
3179 {
3180 /* Additional 4 bytes to allow use of '_mm_loadl_epi64' */
3181 ps_mem_rec->u4_mem_size =
3182 MAX_PROCESS_CTXT * max_mb_cols *
3183 (sizeof(isvce_mb_info_nmb_t) + (MB_SIZE * MB_SIZE + 4) * sizeof(UWORD8));
3184 }
3185 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_MB_INFO_NMB, ps_mem_rec->u4_mem_size);
3186
3187 /* Buffers for storing SVC Spatial data */
3188 {
3189 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_SPAT_INP];
3190
3191 ps_mem_rec->u4_mem_size =
3192 isvce_get_svc_inp_buf_size(ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3193 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3194
3195 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_SPAT_INP, ps_mem_rec->u4_mem_size);
3196 }
3197
3198 /* Buffer for storing Downscaler data */
3199 {
3200 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_DOWN_SCALER];
3201
3202 ps_mem_rec->u4_mem_size = isvce_get_downscaler_data_size(
3203 ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3204 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3205
3206 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_DOWN_SCALER, ps_mem_rec->u4_mem_size);
3207 }
3208
3209 {
3210 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_ILP_DATA];
3211
3212 ps_mem_rec->u4_mem_size =
3213 isvce_get_svc_ilp_buf_size(ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3214 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3215
3216 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_ILP_DATA, ps_mem_rec->u4_mem_size);
3217 }
3218
3219 {
3220 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_ILP_MV_CTXT];
3221
3222 ps_mem_rec->u4_mem_size =
3223 isvce_get_ilp_mv_ctxt_size(ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3224 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3225
3226 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_ILP_MV_CTXT, ps_mem_rec->u4_mem_size);
3227 }
3228
3229 {
3230 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_RES_PRED_CTXT];
3231
3232 ps_mem_rec->u4_mem_size = isvce_get_svc_res_pred_ctxt_size(
3233 ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3234 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3235
3236 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_RES_PRED_CTXT,
3237 ps_mem_rec->u4_mem_size);
3238 }
3239
3240 {
3241 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_INTRA_PRED_CTXT];
3242
3243 ps_mem_rec->u4_mem_size = isvce_get_svc_intra_pred_ctxt_size(
3244 ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3245 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3246
3247 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_INTRA_PRED_CTXT,
3248 ps_mem_rec->u4_mem_size);
3249 }
3250
3251 {
3252 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_RC_UTILS_CTXT];
3253
3254 ps_mem_rec->u4_mem_size = isvce_get_rc_utils_data_size();
3255
3256 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_RC_UTILS_CTXT,
3257 ps_mem_rec->u4_mem_size);
3258 }
3259
3260 {
3261 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_SUB_PIC_RC_CTXT];
3262
3263 ps_mem_rec->u4_mem_size = isvce_get_sub_pic_rc_ctxt_size(
3264 ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3265 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3266
3267 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_SUB_PIC_RC_CTXT,
3268 ps_mem_rec->u4_mem_size);
3269 }
3270
3271 #if ENABLE_MODE_STAT_VISUALISER
3272 {
3273 ps_mem_rec = &ps_mem_rec_base[MEM_MODE_STAT_VISUALISER_BUF];
3274
3275 ps_mem_rec->u4_mem_size = isvce_get_msv_ctxt_size(u4_wd, u4_ht);
3276
3277 DEBUG("\nMemory record Id %d = %d \n", MEM_MODE_STAT_VISUALISER_BUF,
3278 ps_mem_rec->u4_mem_size);
3279 }
3280 #endif
3281
3282 /************************************************************************
3283 * RC mem records *
3284 ************************************************************************/
3285 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_RC];
3286 {
3287 isvce_get_rate_control_mem_tab(NULL, ps_mem_rec, FILL_MEMTAB);
3288 }
3289 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_RC, ps_mem_rec->u4_mem_size);
3290
3291 /* Each memtab size is aligned to next multiple of 128 bytes */
3292 /* This is to ensure all the memtabs start at different cache lines */
3293 ps_mem_rec = ps_mem_rec_base;
3294 for(i = 0; i < ISVCE_MEM_REC_CNT; i++)
3295 {
3296 ps_mem_rec->u4_mem_size = ALIGN128(ps_mem_rec->u4_mem_size);
3297 ps_mem_rec++;
3298 }
3299
3300 ps_op->s_ive_op.u4_num_mem_rec = ISVCE_MEM_REC_CNT;
3301
3302 DEBUG("Num mem recs in fill call : %d\n", ps_op->s_ive_op.u4_num_mem_rec);
3303
3304 return (status);
3305 }
3306
3307 /**
3308 *******************************************************************************
3309 *
3310 * @brief
3311 * Initializes from mem records passed to the codec
3312 *
3313 * @par Description:
3314 * Initializes pointers based on mem records passed
3315 *
3316 * @param[in] ps_codec_obj
3317 * Pointer to codec object at API level
3318 *
3319 * @param[in] pv_api_ip
3320 * Pointer to input argument structure
3321 *
3322 * @param[out] pv_api_op
3323 * Pointer to output argument structure
3324 *
3325 * @returns error status
3326 *
3327 * @remarks none
3328 *
3329 *******************************************************************************
3330 */
isvce_init_mem_rec(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)3331 static WORD32 isvce_init_mem_rec(iv_obj_t *ps_codec_obj, void *pv_api_ip, void *pv_api_op)
3332 {
3333 /* api call I/O structures */
3334 isvce_init_ip_t *ps_ip = pv_api_ip;
3335 isvce_init_op_t *ps_op = pv_api_op;
3336
3337 /* mem records */
3338 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
3339
3340 /* codec variables */
3341 isvce_codec_t *ps_codec;
3342 isvce_cabac_ctxt_t *ps_cabac;
3343 isvce_mb_info_ctxt_t *ps_mb_map_ctxt_inc;
3344
3345 isvce_cfg_params_t *ps_cfg;
3346
3347 /* frame dimensions */
3348 WORD32 max_wd_luma, max_ht_luma;
3349 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
3350
3351 /* temp var */
3352 WORD32 i, j;
3353 WORD32 status = IV_SUCCESS;
3354
3355 /* mem records */
3356 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
3357
3358 /* memset all allocated memory, except the first one. First buffer (i.e. i == MEM_REC_IV_OBJ)
3359 is initialized by application before calling this init function */
3360 for(i = ISVCE_MEM_REC_CODEC; i < ISVCE_MEM_REC_CNT; i++)
3361 {
3362 ps_mem_rec = &ps_mem_rec_base[i];
3363 memset(ps_mem_rec->pv_base, 0, ps_mem_rec->u4_mem_size);
3364 }
3365
3366 /* Init mem records */
3367 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CODEC];
3368 {
3369 ps_codec_obj->pv_codec_handle = ps_mem_rec->pv_base;
3370 ps_codec = (isvce_codec_t *) (ps_codec_obj->pv_codec_handle);
3371 }
3372 /* Init mem records_cabac ctxt */
3373 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CABAC];
3374 {
3375 ps_cabac = (isvce_cabac_ctxt_t *) (ps_mem_rec->pv_base);
3376 }
3377
3378 /* Init mem records mb info array for CABAC */
3379 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CABAC_MB_INFO];
3380 {
3381 ps_mb_map_ctxt_inc = (isvce_mb_info_ctxt_t *) (ps_mem_rec->pv_base);
3382 }
3383
3384 /* Note this memset can not be done in init() call, since init will called
3385 during reset as well. And calling this during reset will mean all pointers
3386 need to reinitialized */
3387 memset(ps_codec, 0, sizeof(isvce_codec_t));
3388 memset(ps_cabac, 0, sizeof(isvce_cabac_ctxt_t));
3389
3390 /* Set default Config Params */
3391 ps_cfg = &ps_codec->s_cfg;
3392 isvce_set_default_params(ps_cfg);
3393
3394 /* get new input dimensions that satisfy the SVC and libavc constraints
3395 constraint 1) All layers of SVC should have dimensions that are a multiple of
3396 16 constraint 2) Dimension of Li layer = dimension of Li-1 layer * scaling
3397 factor*/
3398
3399 isvce_get_svc_compliant_dimensions(ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3400 ps_ip->s_svc_inp_params.d_spatial_res_ratio, ps_ip->u4_wd,
3401 ps_ip->u4_ht, &ps_cfg->u4_wd, &ps_cfg->u4_ht);
3402
3403 /* Update config params as per input */
3404 ps_cfg->u4_max_wd = ps_cfg->u4_disp_wd = ALIGN16(ps_cfg->u4_wd);
3405 ps_cfg->u4_max_ht = ps_cfg->u4_disp_ht = ALIGN16(ps_cfg->u4_ht);
3406 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
3407 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
3408 ps_cfg->u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
3409 ps_cfg->u4_max_reorder_cnt = ps_ip->s_ive_ip.u4_max_reorder_cnt;
3410 ps_cfg->u4_max_level = ps_ip->s_ive_ip.u4_max_level;
3411 ps_cfg->e_inp_color_fmt = ps_ip->s_ive_ip.e_inp_color_fmt;
3412 ps_cfg->e_recon_color_fmt = ps_ip->s_ive_ip.e_recon_color_fmt;
3413 ps_cfg->u4_max_framerate = ps_ip->s_ive_ip.u4_max_framerate;
3414 for(i = 0; i < ps_ip->s_svc_inp_params.u1_num_spatial_layers; i++)
3415 {
3416 ps_cfg->au4_max_bitrate[i] = ps_ip->pu4_max_bitrate[i];
3417 }
3418 ps_cfg->u4_num_bframes = ps_ip->s_ive_ip.u4_num_bframes;
3419 ps_cfg->e_content_type = ps_ip->s_ive_ip.e_content_type;
3420 ps_cfg->u4_max_srch_rng_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
3421 ps_cfg->u4_max_srch_rng_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
3422 ps_cfg->e_slice_mode = ps_ip->s_ive_ip.e_slice_mode;
3423 ps_cfg->u4_slice_param = ps_ip->s_ive_ip.u4_slice_param;
3424 ps_cfg->e_arch = ps_ip->s_ive_ip.e_arch;
3425 ps_cfg->e_soc = ps_ip->s_ive_ip.e_soc;
3426 ps_cfg->u4_enable_recon = ps_ip->s_ive_ip.u4_enable_recon;
3427 ps_cfg->e_rc_mode = ps_ip->s_ive_ip.e_rc_mode;
3428 ps_cfg->u4_disable_vui = ps_ip->b_use_default_vui;
3429
3430 ps_cfg->s_svc_params.u1_num_temporal_layers = ps_ip->s_svc_inp_params.u1_num_temporal_layers;
3431
3432 ps_cfg->s_svc_params.u1_num_spatial_layers = ps_ip->s_svc_inp_params.u1_num_spatial_layers;
3433
3434 ps_cfg->s_svc_params.d_spatial_res_ratio = ps_ip->s_svc_inp_params.d_spatial_res_ratio;
3435
3436 ps_cfg->b_nalu_info_export_enable = ps_ip->b_nalu_info_export_enable;
3437
3438 /* frame dimensions */
3439 max_ht_luma = ALIGN16(ps_cfg->u4_ht);
3440 max_wd_luma = ALIGN16(ps_cfg->u4_wd);
3441 max_mb_rows = max_ht_luma / MB_SIZE;
3442 max_mb_cols = max_wd_luma / MB_SIZE;
3443 max_mb_cnt = max_mb_rows * max_mb_cols;
3444
3445 /* Validate params */
3446 ps_op->s_ive_op.u4_error_code |= isvce_svc_inp_params_validate(ps_ip, ps_cfg);
3447
3448 if(ps_op->s_ive_op.u4_error_code != IV_SUCCESS)
3449 {
3450 return IV_FAIL;
3451 }
3452
3453 #if defined(X86)
3454 if((ps_cfg->e_arch != ARCH_X86_GENERIC) && (ps_cfg->e_arch != ARCH_X86_SSSE3) &&
3455 (ps_cfg->e_arch != ARCH_X86_SSE42))
3456 {
3457 ps_cfg->e_arch = ARCH_X86_SSE42;
3458 }
3459 #else
3460 if((ps_cfg->e_arch == ARCH_X86_GENERIC) || (ps_cfg->e_arch == ARCH_X86_SSSE3) ||
3461 (ps_cfg->e_arch == ARCH_X86_SSE42))
3462 {
3463 #if defined(DISABLE_NEON)
3464 ps_cfg->e_arch = ARCH_ARM_NONEON;
3465 #elif defined(ARMV8)
3466 ps_cfg->e_arch = ARCH_ARM_V8_NEON;
3467 #else
3468 ps_cfg->e_arch = ARCH_ARM_A7;
3469 #endif
3470 }
3471 #endif
3472
3473 if((ps_ip->s_ive_ip.u4_max_level < MIN_LEVEL) || (ps_ip->s_ive_ip.u4_max_level > MAX_LEVEL))
3474 {
3475 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
3476 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
3477 }
3478
3479 if(ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_CNT)
3480 {
3481 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
3482 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
3483 }
3484
3485 if(ps_ip->s_ive_ip.u4_max_reorder_cnt > MAX_REF_CNT)
3486 {
3487 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
3488 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
3489 }
3490
3491 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_BACKUP];
3492 {
3493 ps_codec->ps_mem_rec_backup = (iv_mem_rec_t *) ps_mem_rec->pv_base;
3494
3495 memcpy(ps_codec->ps_mem_rec_backup, ps_mem_rec_base,
3496 ISVCE_MEM_REC_CNT * sizeof(iv_mem_rec_t));
3497 }
3498
3499 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ENTROPY];
3500 {
3501 /* temp var */
3502 WORD32 size = 0, offset;
3503
3504 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3505 {
3506 if(i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
3507 {
3508 /* base ptr */
3509 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3510
3511 /* reset size */
3512 size = 0;
3513
3514 /* skip mb run */
3515 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run = (WORD32 *) (pu1_buf + size);
3516 size += sizeof(WORD32);
3517 size = ALIGN8(size);
3518
3519 /* entropy map */
3520 ps_codec->as_process[i].s_entropy.pu1_entropy_map =
3521 (UWORD8 *) (pu1_buf + size + max_mb_cols);
3522 /* size in bytes to store entropy status of an entire frame */
3523 size += (max_mb_cols * max_mb_rows);
3524 /* add an additional 1 row of bytes to evade the special case of row 0
3525 */
3526 size += max_mb_cols;
3527 size = ALIGN128(size);
3528
3529 /* bit stream ptr */
3530 ps_codec->as_process[i].s_entropy.ps_bitstrm = (bitstrm_t *) (pu1_buf + size);
3531 size += sizeof(ps_codec->as_process[i].s_entropy.ps_bitstrm[0]);
3532 size = ALIGN128(size);
3533
3534 #if ENABLE_RE_ENC_AS_SKIP
3535 ps_codec->as_process[i].s_entropy.ps_bitstrm_after_slice_hdr =
3536 (bitstrm_t *) (pu1_buf + size);
3537 size += sizeof(ps_codec->as_process[i].s_entropy.ps_bitstrm_after_slice_hdr[0]);
3538 size = ALIGN128(size);
3539 #endif
3540
3541 /* nnz luma */
3542 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma = (UWORD8(*)[4])(pu1_buf + size);
3543 size += (max_mb_cols * 4 * sizeof(UWORD8));
3544 size = ALIGN128(size);
3545
3546 /* nnz chroma */
3547 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr = (UWORD8(*)[4])(pu1_buf + size);
3548 size += (max_mb_cols * 4 * sizeof(UWORD8));
3549 size = ALIGN128(size);
3550
3551 /* ps_mb_qp_ctxt */
3552 ps_codec->as_process[i].s_entropy.ps_mb_qp_ctxt = (mb_qp_ctxt_t *) (pu1_buf + size);
3553 size += ALIGN128(sizeof(ps_codec->as_process[i].s_entropy.ps_mb_qp_ctxt[0]));
3554
3555 offset = size;
3556
3557 /* cabac Context */
3558 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac;
3559 }
3560 else
3561 {
3562 /* base ptr */
3563 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3564
3565 /* reset size */
3566 size = offset;
3567
3568 /* skip mb run */
3569 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run = (WORD32 *) (pu1_buf + size);
3570 size += sizeof(WORD32);
3571 size = ALIGN8(size);
3572
3573 /* entropy map */
3574 ps_codec->as_process[i].s_entropy.pu1_entropy_map =
3575 (UWORD8 *) (pu1_buf + size + max_mb_cols);
3576 /* size in bytes to store entropy status of an entire frame */
3577 size += (max_mb_cols * max_mb_rows);
3578 /* add an additional 1 row of bytes to evade the special case of row 0
3579 */
3580 size += max_mb_cols;
3581 size = ALIGN128(size);
3582
3583 /* bit stream ptr */
3584 ps_codec->as_process[i].s_entropy.ps_bitstrm = (bitstrm_t *) (pu1_buf + size);
3585 size += sizeof(ps_codec->as_process[i].s_entropy.ps_bitstrm[0]);
3586 size = ALIGN128(size);
3587
3588 #if ENABLE_RE_ENC_AS_SKIP
3589 ps_codec->as_process[i].s_entropy.ps_bitstrm_after_slice_hdr =
3590 (bitstrm_t *) (pu1_buf + size);
3591 size += sizeof(ps_codec->as_process[i].s_entropy.ps_bitstrm_after_slice_hdr[0]);
3592 size = ALIGN128(size);
3593 #endif
3594
3595 /* nnz luma */
3596 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma =
3597 (UWORD8(*)[4])(UWORD8(*)[4])(pu1_buf + size);
3598 size += (max_mb_cols * 4 * sizeof(UWORD8));
3599 size = ALIGN128(size);
3600
3601 /* nnz chroma */
3602 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr = (UWORD8(*)[4])(pu1_buf + size);
3603 size += (max_mb_cols * 4 * sizeof(UWORD8));
3604 size = ALIGN128(size);
3605
3606 /* ps_mb_qp_ctxt */
3607 ps_codec->as_process[i].s_entropy.ps_mb_qp_ctxt = (mb_qp_ctxt_t *) (pu1_buf + size);
3608 size = ALIGN128(sizeof(ps_codec->as_process[i].s_entropy.ps_mb_qp_ctxt[0]));
3609
3610 /* cabac Context */
3611 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac;
3612 }
3613 }
3614 ps_codec->as_process[0].s_entropy.ps_cabac->ps_mb_map_ctxt_inc_base = ps_mb_map_ctxt_inc;
3615 }
3616
3617 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MB_COEFF_DATA];
3618 {
3619 /* temp var */
3620 WORD32 size = 0, size_of_row;
3621 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3622
3623 /* size of coeff data of 1 mb */
3624 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
3625
3626 /* size of coeff data of 1 row of mb's */
3627 size *= max_mb_cols;
3628
3629 /* align to avoid false sharing */
3630 size = ALIGN64(size);
3631 size_of_row = size;
3632
3633 /* size for one full frame */
3634 size *= max_mb_rows;
3635
3636 ps_codec->u4_size_coeff_data = size_of_row;
3637
3638 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3639 {
3640 if(i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
3641 {
3642 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf;
3643 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data = pu1_buf;
3644 }
3645 else
3646 {
3647 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf + size;
3648 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data = pu1_buf + size;
3649 }
3650 }
3651 }
3652
3653 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MB_HEADER_DATA];
3654 {
3655 /* temp var */
3656 WORD32 size, size_of_row;
3657 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3658
3659 /* size of header data of 1 mb */
3660 size = sizeof(isvce_mb_hdr_t);
3661
3662 /* size for 1 row of mbs */
3663 size = size * max_mb_cols;
3664
3665 /* align to avoid any false sharing across threads */
3666 size = ALIGN64(size);
3667 size_of_row = size;
3668
3669 /* size for one full frame */
3670 size *= max_mb_rows;
3671
3672 ps_codec->u4_size_header_data = size_of_row;
3673
3674 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3675 {
3676 if(i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
3677 {
3678 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf;
3679 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data = pu1_buf;
3680 }
3681 else
3682 {
3683 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf + size;
3684 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data = pu1_buf + size;
3685 }
3686 }
3687 }
3688
3689 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MVBITS];
3690 {
3691 /* max srch range x */
3692 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
3693
3694 /* max srch range y */
3695 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
3696
3697 /* max srch range */
3698 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
3699
3700 /* temp var */
3701 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3702
3703 /* due to subpel */
3704 u4_max_srch_range <<= 2;
3705
3706 // /* due to mv on either direction */
3707 // u4_max_srch_range = (u4_max_srch_range << 1);
3708
3709 /* due to pred mv + zero */
3710 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
3711
3712 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3713 {
3714 /* me ctxt */
3715 isvce_me_ctxt_t *ps_mem_ctxt = &(ps_codec->as_process[i].s_me_ctxt);
3716
3717 /* init at zero mv */
3718 ps_mem_ctxt->pu1_mv_bits = pu1_buf + u4_max_srch_range;
3719 }
3720 }
3721
3722 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SPS];
3723 {
3724 ps_codec->ps_sps_base = (sps_t *) ps_mem_rec->pv_base;
3725 }
3726
3727 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PPS];
3728 {
3729 ps_codec->ps_pps_base = (pps_t *) ps_mem_rec->pv_base;
3730 }
3731
3732 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SVC_NALU_EXT];
3733 {
3734 ps_codec->ps_svc_nalu_ext_base = ps_mem_rec->pv_base;
3735
3736 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3737 {
3738 if(i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
3739 {
3740 ps_codec->as_process[i].ps_svc_nalu_ext_base = ps_mem_rec->pv_base;
3741 }
3742 else
3743 {
3744 WORD32 size = SVC_MAX_SLICE_HDR_CNT * sizeof(slice_header_t);
3745 void *pv_buf = (UWORD8 *) ps_mem_rec->pv_base + size;
3746
3747 ps_codec->as_process[i].ps_svc_nalu_ext_base = pv_buf;
3748 }
3749 }
3750 }
3751
3752 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SUBSET_SPS];
3753 {
3754 ps_codec->ps_subset_sps_base = ps_mem_rec->pv_base;
3755 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3756 {
3757 ps_codec->as_process[i].ps_subset_sps_base = ps_mem_rec->pv_base;
3758 }
3759 }
3760 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SLICE_HDR];
3761 {
3762 ps_codec->ps_slice_hdr_base = ps_mem_rec->pv_base;
3763
3764 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3765 {
3766 if(i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
3767 {
3768 ps_codec->as_process[i].ps_slice_hdr_base = ps_mem_rec->pv_base;
3769 }
3770 else
3771 {
3772 /* temp var */
3773 WORD32 size = SVC_MAX_SLICE_HDR_CNT * sizeof(slice_header_t);
3774 void *pv_buf = (UWORD8 *) ps_mem_rec->pv_base + size;
3775
3776 ps_codec->as_process[i].ps_slice_hdr_base = pv_buf;
3777 }
3778 }
3779 }
3780
3781 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SVC_SLICE_HDR];
3782 {
3783 ps_codec->ps_svc_slice_hdr_base = ps_mem_rec->pv_base;
3784
3785 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3786 {
3787 ps_codec->as_process[i].ps_svc_slice_hdr_base = ps_mem_rec->pv_base;
3788 }
3789 }
3790
3791 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_AIR_MAP];
3792 {
3793 /* temp var */
3794 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3795
3796 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3797 {
3798 if(i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
3799 {
3800 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf;
3801 }
3802 else
3803 {
3804 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf + max_mb_cnt;
3805 }
3806 }
3807
3808 ps_codec->pu2_intr_rfrsh_map = (UWORD16 *) (pu1_buf + max_mb_cnt * MAX_CTXT_SETS);
3809 }
3810
3811 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SLICE_MAP];
3812 {
3813 /* pointer to storage space */
3814 UWORD8 *pu1_buf_ping, *pu1_buf_pong;
3815
3816 /* init pointer */
3817 pu1_buf_ping = ps_mem_rec->pv_base;
3818 pu1_buf_pong = pu1_buf_ping + ALIGN64(max_mb_cnt);
3819
3820 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3821 {
3822 if(i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
3823 {
3824 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_ping;
3825 }
3826 else
3827 {
3828 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_pong;
3829 }
3830 }
3831 }
3832
3833 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_THREAD_HANDLE];
3834 {
3835 WORD32 handle_size = ithread_get_handle_size();
3836
3837 for(i = 0; i < MAX_PROCESS_THREADS; i++)
3838 {
3839 ps_codec->apv_proc_thread_handle[i] =
3840 (UWORD8 *) ps_mem_rec->pv_base + (i * handle_size);
3841 }
3842 }
3843
3844 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CTL_MUTEX];
3845 {
3846 ps_codec->pv_ctl_mutex = ps_mem_rec->pv_base;
3847 }
3848
3849 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ENTROPY_MUTEX];
3850 {
3851 ps_codec->pv_entropy_mutex = ps_mem_rec->pv_base;
3852 }
3853
3854 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PROC_JOBQ];
3855 {
3856 ps_codec->pv_proc_jobq_buf = ps_mem_rec->pv_base;
3857 ps_codec->i4_proc_jobq_buf_size = ps_mem_rec->u4_mem_size;
3858 }
3859
3860 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ENTROPY_JOBQ];
3861 {
3862 ps_codec->pv_entropy_jobq_buf = ps_mem_rec->pv_base;
3863 ps_codec->i4_entropy_jobq_buf_size = ps_mem_rec->u4_mem_size;
3864 }
3865
3866 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PROC_MAP];
3867 {
3868 /* pointer to storage space */
3869 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3870
3871 /* total size of the mem record */
3872 WORD32 total_size = 0;
3873
3874 /* size in bytes to mb core coding status of an entire frame */
3875 total_size = max_mb_cnt;
3876
3877 /* add an additional 1 row of bytes to evade the special case of row 0 */
3878 total_size += max_mb_cols;
3879
3880 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3881 {
3882 if(i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
3883 {
3884 ps_codec->as_process[i].pu1_proc_map = pu1_buf + max_mb_cols;
3885 }
3886 else
3887 {
3888 ps_codec->as_process[i].pu1_proc_map = pu1_buf + total_size + max_mb_cols;
3889 }
3890 }
3891 }
3892
3893 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_DBLK_MAP];
3894 {
3895 /* pointer to storage space */
3896 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3897
3898 /* total size of the mem record */
3899 WORD32 total_size = 0;
3900
3901 /* size in bytes to mb core coding status of an entire frame */
3902 total_size = max_mb_cnt;
3903
3904 /* add an additional 1 row of bytes to evade the special case of row 0 */
3905 total_size += max_mb_cols;
3906
3907 /*Align the memory offsets*/
3908 total_size = ALIGN64(total_size);
3909
3910 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3911 {
3912 if(i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
3913 {
3914 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + max_mb_cols;
3915 }
3916 else
3917 {
3918 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + total_size + max_mb_cols;
3919 }
3920 }
3921 }
3922
3923 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ME_MAP];
3924 {
3925 /* pointer to storage space */
3926 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
3927
3928 /* total size of the mem record */
3929 WORD32 total_size = 0;
3930
3931 /* size in bytes to mb core coding status of an entire frame */
3932 total_size = max_mb_cnt;
3933
3934 /* add an additional 1 row of bytes to evade the special case of row 0 */
3935 total_size += max_mb_cols;
3936
3937 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3938 {
3939 if(i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
3940 {
3941 ps_codec->as_process[i].pu1_me_map = pu1_buf + max_mb_cols;
3942 }
3943 else
3944 {
3945 ps_codec->as_process[i].pu1_me_map = pu1_buf + total_size + max_mb_cols;
3946 }
3947 }
3948 }
3949
3950 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_DPB_MGR];
3951 {
3952 ps_codec->pv_dpb_mgr = ps_mem_rec->pv_base;
3953 }
3954
3955 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PROC_SCRATCH];
3956 {
3957 /* pointer to storage space */
3958 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
3959
3960 /* size of pred buffer, fwd transform output, temp buffer for inv tra */
3961 WORD32 size_pred_luma, size_pred_chroma, size_fwd, size_inv, size_hp;
3962
3963 /* temp var */
3964 WORD32 size = 0;
3965
3966 /* size to hold intra/inter prediction buffer */
3967 size_pred_luma = sizeof(UWORD8) * 16 * 16;
3968 size_pred_chroma = sizeof(UWORD8) * 8 * 16;
3969
3970 /* size to hold fwd transform output */
3971 size_fwd = sizeof(WORD16) * SIZE_TRANS_BUFF;
3972
3973 /* size to hold temporary data during inverse transform */
3974 size_inv = sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
3975
3976 /* size to hold half pel plane buffers */
3977 size_hp = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
3978
3979 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3980 {
3981 /* prediction buffer */
3982 ps_codec->as_process[i].pu1_pred_mb = (void *) (pu1_buf + size);
3983 ps_codec->as_process[i].i4_pred_strd = 16;
3984 size += size_pred_luma;
3985 size = ALIGN64(size);
3986
3987 /* prediction buffer */
3988 ps_codec->as_process[i].pu1_ref_mb_intra_4x4 = (void *) (pu1_buf + size);
3989 size += size_pred_luma;
3990 size = ALIGN64(size);
3991
3992 /* prediction buffer intra 16x16 */
3993 ps_codec->as_process[i].pu1_pred_mb_intra_16x16 = (void *) (pu1_buf + size);
3994 size += size_pred_luma;
3995 size = ALIGN64(size);
3996
3997 /* prediction buffer intra 16x16 plane*/
3998 ps_codec->as_process[i].pu1_pred_mb_intra_16x16_plane = (void *) (pu1_buf + size);
3999 size += size_pred_luma;
4000 size = ALIGN64(size);
4001
4002 /* prediction buffer intra chroma*/
4003 ps_codec->as_process[i].pu1_pred_mb_intra_chroma = (void *) (pu1_buf + size);
4004 size += size_pred_chroma;
4005 size = ALIGN64(size);
4006
4007 /* prediction buffer intra chroma plane*/
4008 ps_codec->as_process[i].pu1_pred_mb_intra_chroma_plane = (void *) (pu1_buf + size);
4009 size += size_pred_chroma;
4010 size = ALIGN64(size);
4011
4012 /* Fwd transform output */
4013 ps_codec->as_process[i].pi2_res_buf = (void *) (pu1_buf + size);
4014 ps_codec->as_process[i].i4_res_strd = 16;
4015 size += size_fwd;
4016 size = ALIGN64(size);
4017
4018 /* Fwd transform output */
4019 ps_codec->as_process[i].pi2_res_buf_intra_4x4 = (void *) (pu1_buf + size);
4020 size += size_fwd;
4021 size = ALIGN64(size);
4022
4023 /* scratch buffer used during inverse transform */
4024 ps_codec->as_process[i].pv_scratch_buff = (void *) (pu1_buf + size);
4025 size += size_inv;
4026 size = ALIGN64(size);
4027
4028 for(j = 0; j < SUBPEL_BUFF_CNT; j++)
4029 {
4030 ps_codec->as_process[i].apu1_subpel_buffs[j] = (pu1_buf + size);
4031 size += ALIGN64(size_hp);
4032 }
4033 }
4034 }
4035
4036 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_QUANT_PARAM];
4037 {
4038 /* pointer to storage space */
4039 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4040
4041 /* size of qp, threshold matrix, fwd scaling list for one plane */
4042 WORD32 size_quant_param, size_thres_mat, size_fwd_weight_mat, size_satqd_weight_mat;
4043
4044 /* temp var */
4045 WORD32 total_size = 0;
4046
4047 /* size of quantization parameter list of 1 plane */
4048 size_quant_param = ALIGN64(sizeof(quant_params_t));
4049
4050 /* size of threshold matrix for quantization
4051 * (assuming the transform_8x8_flag is disabled).
4052 * for 1 plane */
4053 size_thres_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
4054
4055 /* size of forward weight matrix for quantization
4056 * (assuming the transform_8x8_flag is disabled).
4057 * for 1 plane */
4058 size_fwd_weight_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
4059
4060 /* size of SATQD matrix*/
4061 size_satqd_weight_mat = ALIGN64(sizeof(UWORD16) * 9);
4062
4063 for(i = 0; i < MAX_PROCESS_CTXT; i++)
4064 {
4065 quant_params_t **ps_qp_params = ps_codec->as_process[i].ps_qp_params;
4066
4067 /* quantization param structure */
4068 ps_qp_params[0] = (quant_params_t *) (pu1_buf + total_size);
4069 total_size = total_size + size_quant_param;
4070 ps_qp_params[1] = (quant_params_t *) (pu1_buf + total_size);
4071 total_size = total_size + size_quant_param;
4072 ps_qp_params[2] = (quant_params_t *) (pu1_buf + total_size);
4073 total_size = total_size + size_quant_param;
4074
4075 /* threshold matrix for quantization */
4076 ps_qp_params[0]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4077 total_size = total_size + size_thres_mat;
4078 ps_qp_params[1]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4079 total_size = total_size + size_thres_mat;
4080 ps_qp_params[2]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4081 total_size = total_size + size_thres_mat;
4082
4083 /* fwd weight matrix */
4084 ps_qp_params[0]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4085 total_size = total_size + size_fwd_weight_mat;
4086 ps_qp_params[1]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4087 total_size = total_size + size_fwd_weight_mat;
4088 ps_qp_params[2]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4089 total_size = total_size + size_fwd_weight_mat;
4090
4091 /* threshold matrix for SATQD */
4092 ps_qp_params[0]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4093 total_size = total_size + size_satqd_weight_mat;
4094 ps_qp_params[1]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4095 total_size = total_size + size_satqd_weight_mat;
4096 ps_qp_params[2]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4097 total_size = total_size + size_satqd_weight_mat;
4098
4099 total_size = ALIGN128(total_size);
4100 }
4101 }
4102
4103 isvce_svc_nbr_info_buf_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_REC_TOP_ROW_SYN_INFO]);
4104
4105 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_BS_QP];
4106 {
4107 UWORD8 *pu1_buf_ping;
4108
4109 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of
4110 * every mb*/
4111 WORD32 vert_bs_size, horz_bs_size, qp_size;
4112
4113 /* vertical edge bs = total number of vertical edges * number of bytes per
4114 * each edge */
4115 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
4116 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing
4117 * bs */
4118 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
4119
4120 /* horizontal edge bs = total number of horizontal edges * number of bytes
4121 * per each edge */
4122 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
4123 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing
4124 * bs */
4125 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
4126
4127 /* qp of each mb requires 1 byte */
4128 qp_size = ALIGN64(max_mb_cnt);
4129
4130 for(i = 0; i < MAX_PROCESS_CTXT; i++)
4131 {
4132 pu1_buf_ping = (UWORD8 *) ps_mem_rec->pv_base;
4133
4134 /* vertical edge bs storage space */
4135 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs =
4136 (UWORD32 *) pu1_buf_ping;
4137 pu1_buf_ping += vert_bs_size;
4138
4139 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_intra_base_vert_bs =
4140 (UWORD32 *) pu1_buf_ping;
4141 pu1_buf_ping += vert_bs_size;
4142
4143 /* horizontal edge bs storage space */
4144 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs =
4145 (UWORD32 *) pu1_buf_ping;
4146 pu1_buf_ping += horz_bs_size;
4147
4148 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_intra_base_horz_bs =
4149 (UWORD32 *) pu1_buf_ping;
4150 pu1_buf_ping += horz_bs_size;
4151
4152 /* qp */
4153 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp = (UWORD8 *) pu1_buf_ping;
4154 pu1_buf_ping += qp_size;
4155 }
4156 }
4157
4158 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_INP_PIC];
4159 {
4160 ps_codec->pv_inp_buf_mgr_base = ps_mem_rec->pv_base;
4161 }
4162
4163 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_OUT];
4164 {
4165 ps_codec->pv_out_buf_mgr_base = ps_mem_rec->pv_base;
4166 }
4167
4168 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CSC];
4169 {
4170 ps_codec->pu1_y_csc_buf_base = ps_mem_rec->pv_base;
4171 ps_codec->pu1_uv_csc_buf_base =
4172 (UWORD8 *) ps_mem_rec->pv_base + (max_ht_luma * max_wd_luma);
4173 }
4174
4175 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_REF_PIC];
4176 {
4177 /* size of buf mgr struct */
4178 WORD32 size = ih264_buf_mgr_size();
4179
4180 /* temp var */
4181 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4182
4183 /* pic buffer mgr */
4184 ps_codec->pv_ref_buf_mgr_base = pu1_buf;
4185
4186 /* picture bank */
4187 ps_codec->ps_pic_buf_base = (svc_au_buf_t *) (pu1_buf + size);
4188 ps_codec->i4_total_pic_buf_size = ps_mem_rec->u4_mem_size - size;
4189 }
4190
4191 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MVBANK];
4192 {
4193 /* size of buf mgr struct */
4194 WORD32 size = ih264_buf_mgr_size();
4195
4196 /* temp var */
4197 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4198
4199 /* mv buffer mgr */
4200 ps_codec->pv_svc_au_data_store_mgr_base = pu1_buf;
4201
4202 /* mv bank */
4203 ps_codec->ps_svc_au_data_base = (svc_au_data_t *) (pu1_buf + size);
4204 ps_codec->i4_svc_au_data_size = ps_mem_rec->u4_mem_size - size;
4205 }
4206
4207 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MB_INFO_NMB];
4208 {
4209 /* temp var */
4210 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4211
4212 /* size of nmb ctxt */
4213 WORD32 size = max_mb_cols * sizeof(isvce_mb_info_nmb_t);
4214
4215 WORD32 nmb_cntr, subpel_buf_size;
4216
4217 /* init nmb info structure pointer in all proc ctxts */
4218 for(i = 0; i < MAX_PROCESS_CTXT; i++)
4219 {
4220 ps_codec->as_process[i].ps_nmb_info = (isvce_mb_info_nmb_t *) (pu1_buf);
4221
4222 pu1_buf += size;
4223 }
4224
4225 /* Additional 4 bytes to allow use of '_mm_loadl_epi64' */
4226 subpel_buf_size = (MB_SIZE * MB_SIZE + 4) * sizeof(UWORD8);
4227
4228 /* adjusting pointers for nmb halfpel buffer */
4229 for(i = 0; i < MAX_PROCESS_CTXT; i++)
4230 {
4231 isvce_mb_info_nmb_t *ps_mb_info_nmb = &ps_codec->as_process[i].ps_nmb_info[0];
4232
4233 for(nmb_cntr = 0; nmb_cntr < max_mb_cols; nmb_cntr++)
4234 {
4235 ps_mb_info_nmb[nmb_cntr].pu1_best_sub_pel_buf = pu1_buf;
4236
4237 pu1_buf = pu1_buf + subpel_buf_size;
4238
4239 ps_mb_info_nmb[nmb_cntr].u4_bst_spel_buf_strd = MB_SIZE;
4240 }
4241 }
4242 }
4243
4244 isvce_svc_inp_buf_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_SVC_SPAT_INP]);
4245
4246 isvce_initialize_downscaler(&ps_codec->s_scaler, &ps_mem_rec_base[ISVCE_MEM_DOWN_SCALER],
4247 ps_codec->s_cfg.s_svc_params.d_spatial_res_ratio,
4248 ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers,
4249 ps_codec->s_cfg.u4_wd, ps_codec->s_cfg.u4_ht,
4250 ps_codec->s_cfg.e_arch);
4251
4252 isvce_svc_ilp_buf_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_SVC_ILP_DATA]);
4253
4254 isvce_ilp_mv_ctxt_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_SVC_ILP_MV_CTXT]);
4255
4256 isvce_svc_res_pred_ctxt_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_SVC_RES_PRED_CTXT]);
4257
4258 isvce_intra_pred_ctxt_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_SVC_INTRA_PRED_CTXT]);
4259
4260 isvce_rc_utils_init(&ps_codec->s_rate_control.s_rc_utils,
4261 &ps_mem_rec_base[ISVCE_MEM_SVC_RC_UTILS_CTXT], ps_codec->s_cfg.e_arch);
4262
4263 #if ENABLE_MODE_STAT_VISUALISER
4264 isvce_msv_ctxt_init(ps_codec, &ps_mem_rec_base[MEM_MODE_STAT_VISUALISER_BUF]);
4265 #endif
4266
4267 isvce_get_rate_control_mem_tab(&ps_codec->s_rate_control, &ps_mem_rec_base[ISVCE_MEM_REC_RC],
4268 USE_BASE);
4269
4270 isvce_sub_pic_rc_ctxt_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_SVC_SUB_PIC_RC_CTXT]);
4271
4272 status = isvce_init(ps_codec);
4273
4274 return status;
4275 }
4276
4277 /**
4278 *******************************************************************************
4279 *
4280 * @brief
4281 * Retrieves mem records passed to the codec
4282 *
4283 * @par Description:
4284 * Retrieves mem recs passed during init
4285 *
4286 * @param[in] ps_codec_obj
4287 * Pointer to codec object at API level
4288 *
4289 * @param[in] pv_api_ip
4290 * Pointer to input argument structure
4291 *
4292 * @param[out] pv_api_op
4293 * Pointer to output argument structure
4294 *
4295 * @returns error status
4296 *
4297 * @remarks none
4298 *
4299 *******************************************************************************
4300 */
isvce_retrieve_memrec(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)4301 static WORD32 isvce_retrieve_memrec(iv_obj_t *ps_codec_obj, void *pv_api_ip, void *pv_api_op)
4302 {
4303 isvce_codec_t *ps_codec = (isvce_codec_t *) ps_codec_obj->pv_codec_handle;
4304
4305 /* ctrl call I/O structures */
4306 isvce_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
4307 isvce_retrieve_mem_rec_op_t *ps_op = pv_api_op;
4308
4309 if(ps_codec->i4_init_done != 1)
4310 {
4311 ps_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
4312 ps_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
4313 return IV_FAIL;
4314 }
4315
4316 /* join threads upon at end of sequence */
4317 isvce_join_threads(ps_codec);
4318
4319 /* collect list of memory records used by the encoder library */
4320 memcpy(ps_ip->s_ive_ip.ps_mem_rec, ps_codec->ps_mem_rec_backup,
4321 ISVCE_MEM_REC_CNT * (sizeof(iv_mem_rec_t)));
4322 ps_op->s_ive_op.u4_num_mem_rec_filled = ISVCE_MEM_REC_CNT;
4323
4324 /* clean up mutex memory */
4325 ih264_list_free(ps_codec->pv_entropy_jobq);
4326 ih264_list_free(ps_codec->pv_proc_jobq);
4327 ithread_mutex_destroy(ps_codec->pv_ctl_mutex);
4328 ithread_mutex_destroy(ps_codec->pv_entropy_mutex);
4329
4330 ih264_buf_mgr_free((buf_mgr_t *) ps_codec->pv_svc_au_data_store_mgr);
4331 ih264_buf_mgr_free((buf_mgr_t *) ps_codec->pv_ref_buf_mgr);
4332 ih264_buf_mgr_free((buf_mgr_t *) ps_codec->pv_inp_buf_mgr);
4333 ih264_buf_mgr_free((buf_mgr_t *) ps_codec->pv_out_buf_mgr);
4334
4335 #if ENABLE_MODE_STAT_VISUALISER
4336 isvce_msv_ctxt_delete(ps_codec->ps_mode_stat_visualiser);
4337 #endif
4338
4339 isvce_sub_pic_rc_ctxt_delete(ps_codec->as_process->ps_sub_pic_rc_ctxt);
4340
4341 return IV_SUCCESS;
4342 }
4343
4344 /**
4345 *******************************************************************************
4346 *
4347 * @brief
4348 * Sets the encoder in flush mode.
4349 *
4350 * @par Description:
4351 * Sets the encoder in flush mode
4352 *
4353 * @param[in] ps_codec_obj
4354 * Pointer to codec object at API level
4355 *
4356 * @param[in] pv_api_ip
4357 * Pointer to input argument structure
4358 *
4359 * @param[out] pv_api_op
4360 * Pointer to output argument structure
4361 *
4362 * @returns error status
4363 *
4364 * @remarks This call has no real effect on encoder
4365 *
4366 *******************************************************************************
4367 */
isvce_set_flush_mode(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)4368 static WORD32 isvce_set_flush_mode(iv_obj_t *ps_codec_obj, void *pv_api_ip, void *pv_api_op)
4369 {
4370 /* codec ctxt */
4371 isvce_codec_t *ps_codec = (isvce_codec_t *) ps_codec_obj->pv_codec_handle;
4372
4373 /* ctrl call I/O structures */
4374 isvce_ctl_flush_op_t *ps_ctl_op = pv_api_op;
4375
4376 UNUSED(pv_api_ip);
4377
4378 ps_ctl_op->s_ive_op.u4_error_code = 0;
4379
4380 /* signal flush frame control call */
4381 ps_codec->i4_flush_mode = 1;
4382
4383 return IV_SUCCESS;
4384 }
4385
4386 /**
4387 *******************************************************************************
4388 *
4389 * @brief
4390 * Gets encoder buffer requirements
4391 *
4392 * @par Description:
4393 * Gets the encoder buffer requirements. Basing on max width and max height
4394 * configuration settings, this routine, computes the sizes of necessary input,
4395 * output buffers returns this info to callee.
4396 *
4397 * @param[in] ps_codec_obj
4398 * Pointer to codec object at API level
4399 *
4400 * @param[in] pv_api_ip
4401 * Pointer to input argument structure
4402 *
4403 * @param[out] pv_api_op
4404 * Pointer to output argument structure
4405 *
4406 * @returns error status
4407 *
4408 * @remarks none
4409 *
4410 *******************************************************************************
4411 */
isvce_get_buf_info(void * pv_codec_handle,void * pv_api_ip,void * pv_api_op)4412 static WORD32 isvce_get_buf_info(void *pv_codec_handle, void *pv_api_ip, void *pv_api_op)
4413 {
4414 WORD32 i;
4415 UWORD32 wd, ht;
4416
4417 isvce_codec_t *ps_codec = (isvce_codec_t *) pv_codec_handle;
4418 isvce_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
4419 isvce_ctl_getbufinfo_op_t *ps_op = pv_api_op;
4420
4421 isvce_get_svc_compliant_dimensions(ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers,
4422 ps_codec->s_cfg.s_svc_params.d_spatial_res_ratio,
4423 ALIGN16(ps_ip->s_ive_ip.u4_max_wd),
4424 ALIGN16(ps_ip->s_ive_ip.u4_max_ht), &wd, &ht);
4425
4426 ps_op->s_ive_op.u4_error_code = 0;
4427
4428 /* Number of components in input buffers required for codec &
4429 * Minimum sizes of each component in input buffer required */
4430 if(ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420P)
4431 {
4432 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420_COMP;
4433
4434 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
4435 ps_op->s_ive_op.au4_min_in_buf_size[1] = (wd >> 1) * (ht >> 1);
4436 ps_op->s_ive_op.au4_min_in_buf_size[2] = (wd >> 1) * (ht >> 1);
4437 }
4438 else if(ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_422ILE)
4439 {
4440 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_422ILE_COMP;
4441
4442 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
4443 ps_op->s_ive_op.au4_min_in_buf_size[1] = ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4444 }
4445 else if(ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGB_565)
4446 {
4447 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGB565_COMP;
4448
4449 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
4450 ps_op->s_ive_op.au4_min_in_buf_size[1] = ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4451 }
4452 else if(ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGBA_8888)
4453 {
4454 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGBA8888_COMP;
4455
4456 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 4;
4457 ps_op->s_ive_op.au4_min_in_buf_size[1] = ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4458 }
4459 else if((ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_UV) ||
4460 (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_VU))
4461 {
4462 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420SP_COMP;
4463
4464 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
4465 ps_op->s_ive_op.au4_min_in_buf_size[1] = wd * (ht >> 1);
4466 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4467 }
4468
4469 /* Number of components in output buffers required for codec &
4470 * Minimum sizes of each component in output buffer required */
4471 ps_op->s_ive_op.u4_out_comp_cnt = MIN_BITS_BUFS_COMP;
4472
4473 for(i = 0; i < (WORD32) ps_op->s_ive_op.u4_out_comp_cnt; i++)
4474 {
4475 ps_op->s_ive_op.au4_min_out_buf_size[i] =
4476 isvce_get_min_outbuf_size(wd, ht, ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers);
4477 }
4478
4479 ps_op->u4_rec_comp_cnt = MIN_RAW_BUFS_420_COMP;
4480 ps_op->au4_min_rec_buf_size[0] = wd * ht;
4481 ps_op->au4_min_rec_buf_size[1] = (wd >> 1) * (ht >> 1);
4482 ps_op->au4_min_rec_buf_size[2] = (wd >> 1) * (ht >> 1);
4483
4484 if(ps_codec->s_cfg.b_nalu_info_export_enable)
4485 {
4486 ps_op->u4_min_nalu_info_buf_size =
4487 isvce_get_nalu_info_buf_size(ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers);
4488 }
4489 else
4490 {
4491 ps_op->u4_min_nalu_info_buf_size = 0;
4492 }
4493
4494 ps_op->s_ive_op.u4_min_inp_bufs = MIN_INP_BUFS;
4495 ps_op->s_ive_op.u4_min_out_bufs = MIN_OUT_BUFS;
4496 ps_op->u4_min_rec_bufs = MIN_OUT_BUFS;
4497 ps_op->u4_min_nalu_info_bufs = MIN_OUT_BUFS;
4498
4499 return IV_SUCCESS;
4500 }
4501
4502 /**
4503 *******************************************************************************
4504 *
4505 * @brief
4506 * Sets the picture dimensions
4507 *
4508 * @par Description:
4509 * Sets width, height, display width, display height and strides
4510 *
4511 * @param[in] pv_api_ip
4512 * Pointer to input argument structure
4513 *
4514 * @param[out] pv_api_op
4515 * Pointer to output argument structure
4516 *
4517 * @param[out] ps_cfg
4518 * Pointer to config structure to be updated
4519 *
4520 * @returns error status
4521 *
4522 * @remarks none
4523 *
4524 *******************************************************************************
4525 */
isvce_set_dimensions(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4526 static IV_STATUS_T isvce_set_dimensions(void *pv_api_ip, void *pv_api_op,
4527 isvce_cfg_params_t *ps_cfg)
4528 {
4529 isvce_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
4530 isvce_ctl_set_dimensions_op_t *ps_op = pv_api_op;
4531
4532 ps_op->s_ive_op.u4_error_code = 0;
4533
4534 isvce_get_svc_compliant_dimensions(
4535 ps_cfg->s_svc_params.u1_num_spatial_layers, ps_cfg->s_svc_params.d_spatial_res_ratio,
4536 ps_ip->s_ive_ip.u4_wd, ps_ip->s_ive_ip.u4_ht, &ps_cfg->u4_wd, &ps_cfg->u4_ht);
4537
4538 ASSERT(0 == (ps_cfg->u4_wd % MB_SIZE));
4539 ASSERT(0 == (ps_cfg->u4_ht % MB_SIZE));
4540
4541 ps_cfg->i4_wd_mbs = ps_cfg->u4_wd / MB_SIZE;
4542 ps_cfg->i4_ht_mbs = ps_cfg->u4_ht / MB_SIZE;
4543 ps_cfg->u4_disp_wd = ps_cfg->u4_wd;
4544 ps_cfg->u4_disp_ht = ps_cfg->u4_ht;
4545
4546 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4547 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4548
4549 return IV_SUCCESS;
4550 }
4551
4552 /**
4553 *******************************************************************************
4554 *
4555 * @brief
4556 * Provide dimensions used for encoding
4557 *
4558 * @param[in] pv_api_ip
4559 * Pointer to input argument structure
4560 *
4561 * @param[out] pv_api_op
4562 * Pointer to output argument structure
4563 *
4564 * @param[out] ps_cfg
4565 * Pointer to config structure
4566 *
4567 * @returns error status
4568 *
4569 * @remarks none
4570 *
4571 *******************************************************************************
4572 */
isvce_get_enc_frame_dimensions(isvce_ctl_get_enc_dimensions_ip_t * ps_ip,isvce_ctl_get_enc_dimensions_op_t * ps_op,isvce_cfg_params_t * ps_cfg)4573 static IV_STATUS_T isvce_get_enc_frame_dimensions(isvce_ctl_get_enc_dimensions_ip_t *ps_ip,
4574 isvce_ctl_get_enc_dimensions_op_t *ps_op,
4575 isvce_cfg_params_t *ps_cfg)
4576 {
4577 ps_op->u4_error_code = IVE_ERR_NONE;
4578
4579 isvce_get_svc_compliant_dimensions(ps_cfg->s_svc_params.u1_num_spatial_layers,
4580 ps_cfg->s_svc_params.d_spatial_res_ratio,
4581 ps_ip->u4_inp_frame_wd, ps_ip->u4_inp_frame_ht,
4582 &ps_op->u4_enc_frame_wd, &ps_op->u4_enc_frame_ht);
4583
4584 ASSERT(ps_cfg->u4_wd == ps_op->u4_enc_frame_wd);
4585 ASSERT(ps_cfg->u4_ht == ps_op->u4_enc_frame_ht);
4586
4587 return IV_SUCCESS;
4588 }
4589
4590 /**
4591 *******************************************************************************
4592 *
4593 * @brief
4594 * Sets source and target frame rates
4595 *
4596 * @par Description:
4597 * Sets source and target frame rates
4598 *
4599 * @param[in] pv_api_ip
4600 * Pointer to input argument structure
4601 *
4602 * @param[out] pv_api_op
4603 * Pointer to output argument structure
4604 *
4605 * @param[out] ps_cfg
4606 * Pointer to config structure to be updated
4607 *
4608 * @returns error status
4609 *
4610 * @remarks none
4611 *
4612 *******************************************************************************
4613 */
isvce_set_frame_rate(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4614 static IV_STATUS_T isvce_set_frame_rate(void *pv_api_ip, void *pv_api_op,
4615 isvce_cfg_params_t *ps_cfg)
4616 {
4617 /* ctrl call I/O structures */
4618 isvce_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
4619 isvce_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
4620
4621 ps_op->s_ive_op.u4_error_code = 0;
4622
4623 ps_cfg->u4_src_frame_rate = ps_ip->s_ive_ip.u4_src_frame_rate;
4624 ps_cfg->u4_tgt_frame_rate = ps_ip->s_ive_ip.u4_tgt_frame_rate;
4625
4626 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4627 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4628
4629 return IV_SUCCESS;
4630 }
4631
4632 /**
4633 *******************************************************************************
4634 *
4635 * @brief
4636 * Sets target bit rate
4637 *
4638 * @par Description:
4639 * Sets target bit rate
4640 *
4641 * @param[in] pv_api_ip
4642 * Pointer to input argument structure
4643 *
4644 * @param[out] pv_api_op
4645 * Pointer to output argument structure
4646 *
4647 * @param[out] ps_cfg
4648 * Pointer to config structure to be updated
4649 *
4650 * @returns error status
4651 *
4652 * @remarks none
4653 *
4654 *******************************************************************************
4655 */
isvce_set_bit_rate(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4656 static IV_STATUS_T isvce_set_bit_rate(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4657 {
4658 /* ctrl call I/O structures */
4659 isvce_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
4660 isvce_ctl_set_bitrate_op_t *ps_op = pv_api_op;
4661 WORD8 i;
4662
4663 ps_op->s_ive_op.u4_error_code = 0;
4664
4665 for(i = 0; i < ps_cfg->s_svc_params.u1_num_spatial_layers; i++)
4666 {
4667 ps_cfg->au4_target_bitrate[i] = ps_ip->pu4_target_bitrate[i];
4668 }
4669
4670 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4671 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4672
4673 return IV_SUCCESS;
4674 }
4675
4676 /**
4677 *******************************************************************************
4678 *
4679 * @brief
4680 * Sets frame type
4681 *
4682 * @par Description:
4683 * Sets frame type
4684 *
4685 * @param[in] pv_api_ip
4686 * Pointer to input argument structure
4687 *
4688 * @param[out] pv_api_op
4689 * Pointer to output argument structure
4690 *
4691 * @param[out] ps_cfg
4692 * Pointer to config structure to be updated
4693 *
4694 * @returns error status
4695 *
4696 * @remarks not a sticky tag
4697 *
4698 *******************************************************************************
4699 */
isvce_set_frame_type(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4700 static IV_STATUS_T isvce_set_frame_type(void *pv_api_ip, void *pv_api_op,
4701 isvce_cfg_params_t *ps_cfg)
4702 {
4703 /* ctrl call I/O structures */
4704 isvce_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
4705 isvce_ctl_set_frame_type_op_t *ps_op = pv_api_op;
4706
4707 ps_op->s_ive_op.u4_error_code = 0;
4708
4709 ps_cfg->e_frame_type = ps_ip->s_ive_ip.e_frame_type;
4710
4711 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4712 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4713
4714 return IV_SUCCESS;
4715 }
4716
4717 /**
4718 *******************************************************************************
4719 *
4720 * @brief
4721 * Sets quantization params
4722 *
4723 * @par Description:
4724 * Sets the max, min and default qp for I frame, P frame and B frame
4725 *
4726 * @param[in] pv_api_ip
4727 * Pointer to input argument structure
4728 *
4729 * @param[out] pv_api_op
4730 * Pointer to output argument structure
4731 *
4732 * @param[out] ps_cfg
4733 * Pointer to config structure to be updated
4734 *
4735 * @returns error status
4736 *
4737 * @remarks none
4738 *
4739 *******************************************************************************
4740 */
isvce_set_qp(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4741 static IV_STATUS_T isvce_set_qp(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4742 {
4743 /* ctrl call I/O structures */
4744 isvce_ctl_set_qp_ip_t *ps_set_qp_ip = pv_api_ip;
4745 isvce_ctl_set_qp_op_t *ps_set_qp_op = pv_api_op;
4746 WORD8 i;
4747
4748 ps_set_qp_op->s_ive_op.u4_error_code = 0;
4749
4750 for(i = 0; i < ps_cfg->s_svc_params.u1_num_spatial_layers; i++)
4751 {
4752 ps_cfg->au4_i_qp_max[i] =
4753 CLIP3(MIN_H264_QP, MAX_H264_QP, (WORD32) ps_set_qp_ip->pu4_i_qp_max[i]);
4754 ps_cfg->au4_i_qp_min[i] =
4755 CLIP3(MIN_H264_QP, MAX_H264_QP, (WORD32) ps_set_qp_ip->pu4_i_qp_min[i]);
4756 ps_cfg->au4_i_qp[i] = CLIP3(ps_set_qp_ip->pu4_i_qp_min[i], ps_set_qp_ip->pu4_i_qp_max[i],
4757 ps_set_qp_ip->pu4_i_qp[i]);
4758 ps_cfg->au4_i_qp_max[i] =
4759 CLIP3(MIN_H264_QP, MAX_H264_QP, (WORD32) ps_set_qp_ip->pu4_i_qp_max[i]);
4760 ps_cfg->au4_i_qp_min[i] =
4761 CLIP3(MIN_H264_QP, MAX_H264_QP, (WORD32) ps_set_qp_ip->pu4_i_qp_min[i]);
4762 ps_cfg->au4_i_qp[i] = CLIP3(ps_set_qp_ip->pu4_i_qp_min[i], ps_set_qp_ip->pu4_i_qp_max[i],
4763 ps_set_qp_ip->pu4_i_qp[i]);
4764 ps_cfg->au4_i_qp_max[i] =
4765 CLIP3(MIN_H264_QP, MAX_H264_QP, (WORD32) ps_set_qp_ip->pu4_i_qp_max[i]);
4766 ps_cfg->au4_i_qp_min[i] =
4767 CLIP3(MIN_H264_QP, MAX_H264_QP, (WORD32) ps_set_qp_ip->pu4_i_qp_min[i]);
4768 ps_cfg->au4_i_qp[i] = CLIP3(ps_set_qp_ip->pu4_i_qp_min[i], ps_set_qp_ip->pu4_i_qp_max[i],
4769 ps_set_qp_ip->pu4_i_qp[i]);
4770 }
4771
4772 ps_cfg->u4_timestamp_high = ps_set_qp_ip->s_ive_ip.u4_timestamp_high;
4773 ps_cfg->u4_timestamp_low = ps_set_qp_ip->s_ive_ip.u4_timestamp_low;
4774
4775 return IV_SUCCESS;
4776 }
4777
4778 /**
4779 *******************************************************************************
4780 *
4781 * @brief
4782 * Sets encoding mode
4783 *
4784 * @par Description:
4785 * Sets encoding mode
4786 *
4787 * @param[in] pv_api_ip
4788 * Pointer to input argument structure
4789 *
4790 * @param[out] pv_api_op
4791 * Pointer to output argument structure
4792 *
4793 * @param[out] ps_cfg
4794 * Pointer to config structure to be updated
4795 *
4796 * @returns error status
4797 *
4798 * @remarks none
4799 *
4800 *******************************************************************************
4801 */
isvce_set_enc_mode(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4802 static IV_STATUS_T isvce_set_enc_mode(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4803 {
4804 /* ctrl call I/O structures */
4805 isvce_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
4806 isvce_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
4807
4808 ps_op->s_ive_op.u4_error_code = 0;
4809
4810 ps_cfg->e_enc_mode = ps_ip->s_ive_ip.e_enc_mode;
4811
4812 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4813 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4814
4815 return IV_SUCCESS;
4816 }
4817
4818 /**
4819 *******************************************************************************
4820 *
4821 * @brief
4822 * Sets vbv parameters
4823 *
4824 * @par Description:
4825 * Sets vbv parameters
4826 *
4827 * @param[in] pv_api_ip
4828 * Pointer to input argument structure
4829 *
4830 * @param[out] pv_api_op
4831 * Pointer to output argument structure
4832 *
4833 * @param[out] ps_cfg
4834 * Pointer to config structure to be updated
4835 *
4836 * @returns error status
4837 *
4838 * @remarks none
4839 *
4840 *******************************************************************************
4841 */
isvce_set_vbv_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4842 static IV_STATUS_T isvce_set_vbv_params(void *pv_api_ip, void *pv_api_op,
4843 isvce_cfg_params_t *ps_cfg)
4844 {
4845 /* ctrl call I/O structures */
4846 isvce_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
4847 isvce_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
4848 WORD8 i;
4849
4850 ps_op->s_ive_op.u4_error_code = 0;
4851
4852 for(i = 0; i < ps_cfg->s_svc_params.u1_num_spatial_layers; i++)
4853 {
4854 ps_cfg->au4_vbv_buffer_delay[i] = ps_ip->pu4_vbv_buffer_delay[i];
4855 }
4856
4857 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4858 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4859
4860 return IV_SUCCESS;
4861 }
4862
4863 /**
4864 *******************************************************************************
4865 *
4866 * @brief
4867 * Sets AIR parameters
4868 *
4869 * @par Description:
4870 * Sets AIR parameters
4871 *
4872 * @param[in] pv_api_ip
4873 * Pointer to input argument structure
4874 *
4875 * @param[out] pv_api_op
4876 * Pointer to output argument structure
4877 *
4878 * @param[out] ps_cfg
4879 * Pointer to config structure to be updated
4880 *
4881 * @returns error status
4882 *
4883 * @remarks none
4884 *
4885 *******************************************************************************
4886 */
isvc_set_air_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4887 static IV_STATUS_T isvc_set_air_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4888 {
4889 /* ctrl call I/O structures */
4890 isvce_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
4891 isvce_ctl_set_air_params_op_t *ps_op = pv_api_op;
4892
4893 ps_op->s_ive_op.u4_error_code = 0;
4894
4895 ps_cfg->e_air_mode = ps_ip->s_ive_ip.e_air_mode;
4896 ps_cfg->u4_air_refresh_period = ps_ip->s_ive_ip.u4_air_refresh_period;
4897
4898 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4899 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4900
4901 return IV_SUCCESS;
4902 }
4903
4904 /**
4905 *******************************************************************************
4906 *
4907 * @brief
4908 * Sets motion estimation parameters
4909 *
4910 * @par Description:
4911 * Sets motion estimation parameters
4912 *
4913 * @param[in] pv_api_ip
4914 * Pointer to input argument structure
4915 *
4916 * @param[out] pv_api_op
4917 * Pointer to output argument structure
4918 *
4919 * @param[out] ps_cfg
4920 * Pointer to config structure to be updated
4921 *
4922 * @returns error status
4923 *
4924 * @remarks none
4925 *
4926 *******************************************************************************
4927 */
isvc_set_me_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4928 static IV_STATUS_T isvc_set_me_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4929 {
4930 /* ctrl call I/O structures */
4931 isvce_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
4932 isvce_ctl_set_me_params_op_t *ps_op = pv_api_op;
4933
4934 ps_op->s_ive_op.u4_error_code = 0;
4935
4936 ps_cfg->u4_enable_hpel = ps_ip->s_ive_ip.u4_enable_hpel;
4937 ps_cfg->u4_enable_qpel = ps_ip->s_ive_ip.u4_enable_qpel;
4938 ps_cfg->u4_enable_fast_sad = ps_ip->s_ive_ip.u4_enable_fast_sad;
4939 ps_cfg->u4_enable_alt_ref = ps_ip->s_ive_ip.u4_enable_alt_ref;
4940 ps_cfg->u4_srch_rng_x = ps_ip->s_ive_ip.u4_srch_rng_x;
4941 ps_cfg->u4_srch_rng_y = ps_ip->s_ive_ip.u4_srch_rng_y;
4942 ps_cfg->u4_me_speed_preset = ps_ip->s_ive_ip.u4_me_speed_preset;
4943
4944 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4945 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4946
4947 return IV_SUCCESS;
4948 }
4949
4950 /**
4951 *******************************************************************************
4952 *
4953 * @brief
4954 * Sets Intra/Inter Prediction estimation parameters
4955 *
4956 * @par Description:
4957 * Sets Intra/Inter Prediction estimation parameters
4958 *
4959 * @param[in] pv_api_ip
4960 * Pointer to input argument structure
4961 *
4962 * @param[out] pv_api_op
4963 * Pointer to output argument structure
4964 *
4965 * @param[out] ps_cfg
4966 * Pointer to config structure to be updated
4967 *
4968 * @returns error status
4969 *
4970 * @remarks none
4971 *
4972 *******************************************************************************
4973 */
isvc_set_ipe_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4974 static IV_STATUS_T isvc_set_ipe_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4975 {
4976 /* ctrl call I/O structures */
4977 isvce_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
4978 isvce_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
4979
4980 ps_op->s_ive_op.u4_error_code = 0;
4981
4982 ps_cfg->u4_enable_intra_4x4 = ps_ip->s_ive_ip.u4_enable_intra_4x4;
4983 ps_cfg->u4_enc_speed_preset = ps_ip->s_ive_ip.u4_enc_speed_preset;
4984
4985 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4986 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4987
4988 return IV_SUCCESS;
4989 }
4990
4991 /**
4992 *******************************************************************************
4993 *
4994 * @brief
4995 * Sets GOP parameters
4996 *
4997 * @par Description:
4998 * Sets GOP parameters
4999 *
5000 * @param[in] pv_api_ip
5001 * Pointer to input argument structure
5002 *
5003 * @param[out] pv_api_op
5004 * Pointer to output argument structure
5005 *
5006 * @param[out] ps_cfg
5007 * Pointer to config structure to be updated
5008 *
5009 * @returns error status
5010 *
5011 * @remarks none
5012 *
5013 *******************************************************************************
5014 */
isvc_set_gop_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5015 static IV_STATUS_T isvc_set_gop_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
5016 {
5017 /* ctrl call I/O structures */
5018 isvce_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
5019 isvce_ctl_set_gop_params_op_t *ps_op = pv_api_op;
5020
5021 ps_op->s_ive_op.u4_error_code = 0;
5022
5023 ps_cfg->u4_i_frm_interval = ps_ip->s_ive_ip.u4_i_frm_interval;
5024 ps_cfg->u4_idr_frm_interval = ps_ip->s_ive_ip.u4_idr_frm_interval;
5025
5026 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5027 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5028
5029 return IV_SUCCESS;
5030 }
5031
5032 /**
5033 *******************************************************************************
5034 *
5035 * @brief
5036 * Sets profile parameters
5037 *
5038 * @par Description:
5039 * Sets profile parameters
5040 *
5041 * @param[in] pv_api_ip
5042 * Pointer to input argument structure
5043 *
5044 * @param[out] pv_api_op
5045 * Pointer to output argument structure
5046 *
5047 * @param[out] ps_cfg
5048 * Pointer to config structure to be updated
5049 *
5050 * @returns error status
5051 *
5052 * @remarks none
5053 *
5054 *******************************************************************************
5055 */
isvc_set_profile_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5056 static IV_STATUS_T isvc_set_profile_params(void *pv_api_ip, void *pv_api_op,
5057 isvce_cfg_params_t *ps_cfg)
5058 {
5059 /* ctrl call I/O structures */
5060 isvce_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
5061 isvce_ctl_set_profile_params_op_t *ps_op = pv_api_op;
5062
5063 ps_op->s_ive_op.u4_error_code = 0;
5064
5065 ps_cfg->e_profile = ps_ip->s_ive_ip.e_profile;
5066
5067 ps_cfg->u4_entropy_coding_mode = ps_ip->s_ive_ip.u4_entropy_coding_mode;
5068
5069 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5070 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5071
5072 return IV_SUCCESS;
5073 }
5074
5075 /**
5076 *******************************************************************************
5077 *
5078 * @brief
5079 * Sets disable deblock level
5080 *
5081 * @par Description:
5082 * Sets disable deblock level. Level 0 means no disabling and level 4 means
5083 * disable completely. 1, 2, 3 are intermediate levels that control amount
5084 * of deblocking done.
5085 *
5086 * @param[in] ps_codec_obj
5087 * Pointer to codec object at API level
5088 *
5089 * @param[in] pv_api_ip
5090 * Pointer to input argument structure
5091 *
5092 * @param[out] pv_api_op
5093 * Pointer to output argument structure
5094 *
5095 * @returns error status
5096 *
5097 * @remarks none
5098 *
5099 *******************************************************************************
5100 */
isvc_set_deblock_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5101 static WORD32 isvc_set_deblock_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
5102 {
5103 /* ctrl call I/O structures */
5104 isvce_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
5105 isvce_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
5106
5107 ps_op->s_ive_op.u4_error_code = 0;
5108
5109 ps_cfg->u4_disable_deblock_level = ps_ip->s_ive_ip.u4_disable_deblock_level;
5110
5111 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5112 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5113
5114 return IV_SUCCESS;
5115 }
5116 /**
5117 *******************************************************************************
5118 *
5119 * @brief
5120 * Sets vui params
5121 *
5122 * @par Description:
5123 * Video usability information
5124 *
5125 * @param[in] pv_api_ip
5126 * Pointer to input argument structure
5127 *
5128 * @param[out] pv_api_op
5129 * Pointer to output argument structure
5130 *
5131 * @param[out] ps_cfg
5132 * Pointer to config structure to be updated
5133 *
5134 * @returns error status
5135 *
5136 * @remarks none
5137 *
5138 *******************************************************************************
5139 */
isvce_set_vui_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5140 static WORD32 isvce_set_vui_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
5141 {
5142 /* ctrl call I/O structures */
5143 isvce_vui_ip_t *ps_ip = pv_api_ip;
5144 isvce_vui_op_t *ps_op = pv_api_op;
5145 vui_t *ps_vui = &ps_cfg->s_vui;
5146
5147 ps_op->u4_error_code = 0;
5148
5149 ps_vui->u1_aspect_ratio_info_present_flag = ps_ip->u1_aspect_ratio_info_present_flag;
5150 ps_vui->u1_aspect_ratio_idc = ps_ip->u1_aspect_ratio_idc;
5151 ps_vui->u2_sar_width = ps_ip->u2_sar_width;
5152 ps_vui->u2_sar_height = ps_ip->u2_sar_height;
5153 ps_vui->u1_overscan_info_present_flag = ps_ip->u1_overscan_info_present_flag;
5154 ps_vui->u1_overscan_appropriate_flag = ps_ip->u1_overscan_appropriate_flag;
5155 ps_vui->u1_video_signal_type_present_flag = ps_ip->u1_video_signal_type_present_flag;
5156 ps_vui->u1_video_format = ps_ip->u1_video_format;
5157 ps_vui->u1_video_full_range_flag = ps_ip->u1_video_full_range_flag;
5158 ps_vui->u1_colour_description_present_flag = ps_ip->u1_colour_description_present_flag;
5159 ps_vui->u1_colour_primaries = ps_ip->u1_colour_primaries;
5160 ps_vui->u1_transfer_characteristics = ps_ip->u1_transfer_characteristics;
5161 ps_vui->u1_matrix_coefficients = ps_ip->u1_matrix_coefficients;
5162 ps_vui->u1_chroma_loc_info_present_flag = ps_ip->u1_chroma_loc_info_present_flag;
5163 ps_vui->u1_chroma_sample_loc_type_top_field = ps_ip->u1_chroma_sample_loc_type_top_field;
5164 ps_vui->u1_chroma_sample_loc_type_bottom_field = ps_ip->u1_chroma_sample_loc_type_bottom_field;
5165 ps_vui->u1_vui_timing_info_present_flag = ps_ip->u1_vui_timing_info_present_flag;
5166 ps_vui->u4_vui_num_units_in_tick = ps_ip->u4_vui_num_units_in_tick;
5167 ps_vui->u4_vui_time_scale = ps_ip->u4_vui_time_scale;
5168 ps_vui->u1_fixed_frame_rate_flag = ps_ip->u1_fixed_frame_rate_flag;
5169 ps_vui->u1_nal_hrd_parameters_present_flag = ps_ip->u1_nal_hrd_parameters_present_flag;
5170 ps_vui->u1_vcl_hrd_parameters_present_flag = ps_ip->u1_vcl_hrd_parameters_present_flag;
5171 ps_vui->u1_low_delay_hrd_flag = ps_ip->u1_low_delay_hrd_flag;
5172 ps_vui->u1_pic_struct_present_flag = ps_ip->u1_pic_struct_present_flag;
5173 ps_vui->u1_bitstream_restriction_flag = ps_ip->u1_bitstream_restriction_flag;
5174 ps_vui->u1_motion_vectors_over_pic_boundaries_flag =
5175 ps_ip->u1_motion_vectors_over_pic_boundaries_flag;
5176 ps_vui->u1_max_bytes_per_pic_denom = ps_ip->u1_max_bytes_per_pic_denom;
5177 ps_vui->u1_max_bits_per_mb_denom = ps_ip->u1_max_bits_per_mb_denom;
5178 ps_vui->u1_log2_max_mv_length_horizontal = ps_ip->u1_log2_max_mv_length_horizontal;
5179 ps_vui->u1_log2_max_mv_length_vertical = ps_ip->u1_log2_max_mv_length_vertical;
5180 ps_vui->u1_num_reorder_frames = ps_ip->u1_num_reorder_frames;
5181 ps_vui->u1_max_dec_frame_buffering = ps_ip->u1_max_dec_frame_buffering;
5182
5183 return IV_SUCCESS;
5184 }
5185
5186 /**
5187 *******************************************************************************
5188 *
5189 * @brief
5190 * Sets Mastering display color volume sei params
5191 *
5192 * @par Description:
5193 * Supplemental enhancement information
5194 *
5195 * @param[in] pv_api_ip
5196 * Pointer to input argument structure
5197 *
5198 * @param[out] pv_api_op
5199 * Pointer to output argument structure
5200 *
5201 * @param[out] ps_cfg
5202 * Pointer to config structure to be updated
5203 *
5204 * @return error status
5205 *
5206 * @remarks none
5207 *
5208 *******************************************************************************
5209 */
isvce_set_sei_mdcv_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5210 static WORD32 isvce_set_sei_mdcv_params(void *pv_api_ip, void *pv_api_op,
5211 isvce_cfg_params_t *ps_cfg)
5212 {
5213 WORD32 i4_count;
5214 /* ctrl call I/O structures */
5215 isvce_ctl_set_sei_mdcv_params_ip_t *ps_ip = pv_api_ip;
5216 isvce_ctl_set_sei_mdcv_params_op_t *ps_op = pv_api_op;
5217 sei_params_t *ps_sei = &ps_cfg->s_sei;
5218
5219 ps_op->u4_error_code = 0;
5220
5221 ps_sei->u1_sei_mdcv_params_present_flag = ps_ip->u1_sei_mdcv_params_present_flag;
5222 for(i4_count = 0; i4_count < NUM_SEI_MDCV_PRIMARIES; i4_count++)
5223 {
5224 ps_sei->s_sei_mdcv_params.au2_display_primaries_x[i4_count] =
5225 ps_ip->au2_display_primaries_x[i4_count];
5226 ps_sei->s_sei_mdcv_params.au2_display_primaries_y[i4_count] =
5227 ps_ip->au2_display_primaries_y[i4_count];
5228 }
5229
5230 ps_sei->s_sei_mdcv_params.u2_white_point_x = ps_ip->u2_white_point_x;
5231 ps_sei->s_sei_mdcv_params.u2_white_point_y = ps_ip->u2_white_point_y;
5232 ps_sei->s_sei_mdcv_params.u4_max_display_mastering_luminance =
5233 ps_ip->u4_max_display_mastering_luminance;
5234 ps_sei->s_sei_mdcv_params.u4_min_display_mastering_luminance =
5235 ps_ip->u4_min_display_mastering_luminance;
5236
5237 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5238 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5239
5240 return IV_SUCCESS;
5241 }
5242
5243 /**
5244 *******************************************************************************
5245 *
5246 * @brief
5247 * Sets content light level sei params
5248 *
5249 * @par Description:
5250 * Supplemental enhancement information
5251 *
5252 * @param[in] pv_api_ip
5253 * Pointer to input argument structure
5254 *
5255 * @param[out] pv_api_op
5256 * Pointer to output argument structure
5257 *
5258 * @param[out] ps_cfg
5259 * Pointer to config structure to be updated
5260 *
5261 * @return error status
5262 *
5263 * @remarks none
5264 *
5265 *******************************************************************************
5266 */
isvce_set_sei_cll_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5267 static WORD32 isvce_set_sei_cll_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
5268 {
5269 /* ctrl call I/O structures */
5270 isvce_ctl_set_sei_cll_params_ip_t *ps_ip = pv_api_ip;
5271 isvce_ctl_set_sei_cll_params_op_t *ps_op = pv_api_op;
5272 sei_params_t *ps_sei = &ps_cfg->s_sei;
5273
5274 ps_op->u4_error_code = 0;
5275
5276 ps_sei->u1_sei_cll_params_present_flag = ps_ip->u1_sei_cll_params_present_flag;
5277
5278 ps_sei->s_sei_cll_params.u2_max_content_light_level = ps_ip->u2_max_content_light_level;
5279 ps_sei->s_sei_cll_params.u2_max_pic_average_light_level = ps_ip->u2_max_pic_average_light_level;
5280
5281 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5282 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5283
5284 return IV_SUCCESS;
5285 }
5286
5287 /**
5288 *******************************************************************************
5289 *
5290 * @brief
5291 * Sets ambient viewing environment sei params
5292 *
5293 * @par Description:
5294 * Supplemental enhancement information
5295 *
5296 * @param[in] pv_api_ip
5297 * Pointer to input argument structure
5298 *
5299 * @param[out] pv_api_op
5300 * Pointer to output argument structure
5301 *
5302 * @param[out] ps_cfg
5303 * Pointer to config structure to be updated
5304 *
5305 * @return error status
5306 *
5307 * @remarks none
5308 *
5309 *******************************************************************************
5310 */
isvce_set_sei_ave_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5311 static WORD32 isvce_set_sei_ave_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
5312 {
5313 /* ctrl call I/O structures */
5314 isvce_ctl_set_sei_ave_params_ip_t *ps_ip = pv_api_ip;
5315 isvce_ctl_set_sei_ave_params_op_t *ps_op = pv_api_op;
5316 sei_params_t *ps_sei = &ps_cfg->s_sei;
5317
5318 ps_op->u4_error_code = 0;
5319
5320 ps_sei->u1_sei_ave_params_present_flag = ps_ip->u1_sei_ave_params_present_flag;
5321
5322 ps_sei->s_sei_ave_params.u4_ambient_illuminance = ps_ip->u4_ambient_illuminance;
5323 ps_sei->s_sei_ave_params.u2_ambient_light_x = ps_ip->u2_ambient_light_x;
5324 ps_sei->s_sei_ave_params.u2_ambient_light_y = ps_ip->u2_ambient_light_y;
5325
5326 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5327 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5328
5329 return IV_SUCCESS;
5330 }
5331
5332 /**
5333 *******************************************************************************
5334 *
5335 * @brief
5336 * Sets content color volume sei params
5337 *
5338 * @par Description:
5339 * Supplemental enhancement information
5340 *
5341 * @param[in] pv_api_ip
5342 * Pointer to input argument structure
5343 *
5344 * @param[out] pv_api_op
5345 * Pointer to output argument structure
5346 *
5347 * @param[out] ps_cfg
5348 * Pointer to config structure to be updated
5349 *
5350 * @return error status
5351 *
5352 * @remarks none
5353 *
5354 *******************************************************************************
5355 */
isvce_set_sei_ccv_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5356 static WORD32 isvce_set_sei_ccv_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
5357 {
5358 WORD32 i4_count;
5359 /* ctrl call I/O structures */
5360 isvce_ctl_set_sei_ccv_params_ip_t *ps_ip = pv_api_ip;
5361 isvce_ctl_set_sei_ccv_params_op_t *ps_op = pv_api_op;
5362 sei_params_t *ps_sei = &ps_cfg->s_sei;
5363
5364 ps_op->u4_error_code = 0;
5365
5366 ps_sei->u1_sei_ccv_params_present_flag = ps_ip->u1_sei_ccv_params_present_flag;
5367
5368 ps_sei->s_sei_ccv_params.u1_ccv_cancel_flag = ps_ip->u1_ccv_cancel_flag;
5369 ps_sei->s_sei_ccv_params.u1_ccv_persistence_flag = ps_ip->u1_ccv_persistence_flag;
5370 ps_sei->s_sei_ccv_params.u1_ccv_primaries_present_flag = ps_ip->u1_ccv_primaries_present_flag;
5371 ps_sei->s_sei_ccv_params.u1_ccv_min_luminance_value_present_flag =
5372 ps_ip->u1_ccv_min_luminance_value_present_flag;
5373 ps_sei->s_sei_ccv_params.u1_ccv_max_luminance_value_present_flag =
5374 ps_ip->u1_ccv_max_luminance_value_present_flag;
5375 ps_sei->s_sei_ccv_params.u1_ccv_avg_luminance_value_present_flag =
5376 ps_ip->u1_ccv_avg_luminance_value_present_flag;
5377 ps_sei->s_sei_ccv_params.u1_ccv_reserved_zero_2bits = ps_ip->u1_ccv_reserved_zero_2bits;
5378
5379 for(i4_count = 0; i4_count < NUM_SEI_CCV_PRIMARIES; i4_count++)
5380 {
5381 ps_sei->s_sei_ccv_params.ai4_ccv_primaries_x[i4_count] =
5382 ps_ip->ai4_ccv_primaries_x[i4_count];
5383 ps_sei->s_sei_ccv_params.ai4_ccv_primaries_y[i4_count] =
5384 ps_ip->ai4_ccv_primaries_y[i4_count];
5385 }
5386
5387 ps_sei->s_sei_ccv_params.u4_ccv_min_luminance_value = ps_ip->u4_ccv_min_luminance_value;
5388 ps_sei->s_sei_ccv_params.u4_ccv_max_luminance_value = ps_ip->u4_ccv_max_luminance_value;
5389 ps_sei->s_sei_ccv_params.u4_ccv_avg_luminance_value = ps_ip->u4_ccv_avg_luminance_value;
5390
5391 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5392 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5393
5394 return IV_SUCCESS;
5395 }
5396
5397 /**
5398 *******************************************************************************
5399 *
5400 * @brief
5401 * Sets number of cores
5402 *
5403 * @par Description:
5404 * Sets number of cores
5405 *
5406 * @param[in] ps_codec_obj
5407 * Pointer to codec object at API level
5408 *
5409 * @param[in] pv_api_ip
5410 * Pointer to input argument structure
5411 *
5412 * @param[out] pv_api_op
5413 * Pointer to output argument structure
5414 *
5415 * @returns error status
5416 *
5417 * @remarks The number of encoder threads is limited to MAX_PROCESS_THREADS
5418 *
5419 *******************************************************************************
5420 */
isvce_set_num_cores(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5421 static WORD32 isvce_set_num_cores(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
5422 {
5423 /* ctrl call I/O structures */
5424 isvce_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
5425 isvce_ctl_set_num_cores_op_t *ps_op = pv_api_op;
5426
5427 ps_op->s_ive_op.u4_error_code = 0;
5428
5429 ps_cfg->u4_num_cores = MIN(ps_ip->s_ive_ip.u4_num_cores, MAX_PROCESS_THREADS);
5430
5431 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5432 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5433
5434 return IV_SUCCESS;
5435 }
5436
5437 /**
5438 *******************************************************************************
5439 *
5440 * @brief
5441 * Resets encoder state
5442 *
5443 * @par Description:
5444 * Resets encoder state by calling isvce_init()
5445 *
5446 * @param[in] ps_codec_obj
5447 * Pointer to codec object at API level
5448 *
5449 * @param[in] pv_api_ip
5450 * Pointer to input argument structure
5451 *
5452 * @param[out] pv_api_op
5453 * Pointer to output argument structure
5454 *
5455 * @returns error status
5456 *
5457 * @remarks none
5458 *
5459 *******************************************************************************
5460 */
isvce_reset(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)5461 static WORD32 isvce_reset(iv_obj_t *ps_codec_obj, void *pv_api_ip, void *pv_api_op)
5462 {
5463 /* codec ctxt */
5464 isvce_codec_t *ps_codec = (isvce_codec_t *) (ps_codec_obj->pv_codec_handle);
5465
5466 /* ctrl call I/O structures */
5467 isvce_ctl_reset_op_t *ps_op = pv_api_op;
5468
5469 UNUSED(pv_api_ip);
5470
5471 ps_op->s_ive_op.u4_error_code = 0;
5472
5473 if(ps_codec != NULL)
5474 {
5475 isvce_init(ps_codec);
5476 }
5477 else
5478 {
5479 ps_op->s_ive_op.u4_error_code = IH264E_INIT_NOT_DONE;
5480 }
5481
5482 return IV_SUCCESS;
5483 }
5484
isvce_ctl_set_error_code(void * pv_api_op,ISVCE_CONTROL_API_COMMAND_TYPE_T e_sub_cmd)5485 static void isvce_ctl_set_error_code(void *pv_api_op, ISVCE_CONTROL_API_COMMAND_TYPE_T e_sub_cmd)
5486 {
5487 switch(e_sub_cmd)
5488 {
5489 case ISVCE_CMD_CTL_SET_DIMENSIONS:
5490 {
5491 ((isvce_ctl_set_dimensions_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5492 1 << IVE_FATALERROR;
5493 ((isvce_ctl_set_dimensions_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5494 IH264E_INIT_NOT_DONE;
5495
5496 break;
5497 }
5498 case ISVCE_CMD_CTL_SET_FRAMERATE:
5499 {
5500 ((isvce_ctl_set_frame_rate_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5501 1 << IVE_FATALERROR;
5502 ((isvce_ctl_set_frame_rate_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5503 IH264E_INIT_NOT_DONE;
5504
5505 break;
5506 }
5507 case ISVCE_CMD_CTL_SET_BITRATE:
5508 {
5509 ((isvce_ctl_set_bitrate_op_t *) pv_api_op)->s_ive_op.u4_error_code |= 1
5510 << IVE_FATALERROR;
5511 ((isvce_ctl_set_bitrate_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5512 IH264E_INIT_NOT_DONE;
5513
5514 break;
5515 }
5516 case ISVCE_CMD_CTL_SET_FRAMETYPE:
5517 {
5518 ((isvce_ctl_set_frame_type_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5519 1 << IVE_FATALERROR;
5520 ((isvce_ctl_set_frame_type_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5521 IH264E_INIT_NOT_DONE;
5522
5523 break;
5524 }
5525 case ISVCE_CMD_CTL_SET_QP:
5526 {
5527 ((isvce_ctl_set_qp_op_t *) pv_api_op)->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
5528 ((isvce_ctl_set_qp_op_t *) pv_api_op)->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
5529
5530 break;
5531 }
5532 case ISVCE_CMD_CTL_SET_ENC_MODE:
5533 {
5534 ((isvce_ctl_set_enc_mode_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5535 1 << IVE_FATALERROR;
5536 ((isvce_ctl_set_enc_mode_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5537 IH264E_INIT_NOT_DONE;
5538
5539 break;
5540 }
5541 case ISVCE_CMD_CTL_SET_VBV_PARAMS:
5542 {
5543 ((isvce_ctl_set_vbv_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5544 1 << IVE_FATALERROR;
5545 ((isvce_ctl_set_vbv_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5546 IH264E_INIT_NOT_DONE;
5547
5548 break;
5549 }
5550 case ISVCE_CMD_CTL_SET_AIR_PARAMS:
5551 {
5552 ((isvce_ctl_set_air_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5553 1 << IVE_FATALERROR;
5554 ((isvce_ctl_set_air_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5555 IH264E_INIT_NOT_DONE;
5556
5557 break;
5558 }
5559 case ISVCE_CMD_CTL_SET_ME_PARAMS:
5560 {
5561 ((isvce_ctl_set_me_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5562 1 << IVE_FATALERROR;
5563 ((isvce_ctl_set_me_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5564 IH264E_INIT_NOT_DONE;
5565
5566 break;
5567 }
5568 case ISVCE_CMD_CTL_SET_IPE_PARAMS:
5569 {
5570 ((isvce_ctl_set_ipe_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5571 1 << IVE_FATALERROR;
5572 ((isvce_ctl_set_ipe_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5573 IH264E_INIT_NOT_DONE;
5574
5575 break;
5576 }
5577 case ISVCE_CMD_CTL_SET_GOP_PARAMS:
5578 {
5579 ((isvce_ctl_set_gop_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5580 1 << IVE_FATALERROR;
5581 ((isvce_ctl_set_gop_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5582 IH264E_INIT_NOT_DONE;
5583
5584 break;
5585 }
5586 case ISVCE_CMD_CTL_SET_PROFILE_PARAMS:
5587 {
5588 ((isvce_ctl_set_profile_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5589 1 << IVE_FATALERROR;
5590 ((isvce_ctl_set_profile_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5591 IH264E_INIT_NOT_DONE;
5592
5593 break;
5594 }
5595 case ISVCE_CMD_CTL_SET_DEBLOCK_PARAMS:
5596 {
5597 ((isvce_ctl_set_deblock_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5598 1 << IVE_FATALERROR;
5599 ((isvce_ctl_set_deblock_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5600 IH264E_INIT_NOT_DONE;
5601
5602 break;
5603 }
5604 case ISVCE_CMD_CTL_SET_VUI_PARAMS:
5605 {
5606 ((isvce_vui_op_t *) pv_api_op)->u4_error_code |= 1 << IVE_FATALERROR;
5607 ((isvce_vui_op_t *) pv_api_op)->u4_error_code |= IH264E_INIT_NOT_DONE;
5608
5609 break;
5610 }
5611 case ISVCE_CMD_CTL_SET_SEI_MDCV_PARAMS:
5612 {
5613 ((isvce_ctl_set_sei_mdcv_params_op_t *) pv_api_op)->u4_error_code |= 1
5614 << IVE_FATALERROR;
5615 ((isvce_ctl_set_sei_mdcv_params_op_t *) pv_api_op)->u4_error_code |=
5616 IH264E_INIT_NOT_DONE;
5617
5618 break;
5619 }
5620 case ISVCE_CMD_CTL_SET_SEI_CLL_PARAMS:
5621 {
5622 ((isvce_ctl_set_sei_cll_params_op_t *) pv_api_op)->u4_error_code |= 1 << IVE_FATALERROR;
5623 ((isvce_ctl_set_sei_cll_params_op_t *) pv_api_op)->u4_error_code |=
5624 IH264E_INIT_NOT_DONE;
5625
5626 break;
5627 }
5628 case ISVCE_CMD_CTL_SET_SEI_AVE_PARAMS:
5629 {
5630 ((isvce_ctl_set_sei_ave_params_op_t *) pv_api_op)->u4_error_code |= 1 << IVE_FATALERROR;
5631 ((isvce_ctl_set_sei_ave_params_op_t *) pv_api_op)->u4_error_code |=
5632 IH264E_INIT_NOT_DONE;
5633
5634 break;
5635 }
5636 case ISVCE_CMD_CTL_SET_SEI_CCV_PARAMS:
5637 {
5638 ((isvce_ctl_set_sei_ccv_params_op_t *) pv_api_op)->u4_error_code |= 1 << IVE_FATALERROR;
5639 ((isvce_ctl_set_sei_ccv_params_op_t *) pv_api_op)->u4_error_code |=
5640 IH264E_INIT_NOT_DONE;
5641
5642 break;
5643 }
5644 case ISVCE_CMD_CTL_RESET:
5645 {
5646 ((isvce_ctl_reset_op_t *) pv_api_op)->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
5647 ((isvce_ctl_reset_op_t *) pv_api_op)->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
5648
5649 break;
5650 }
5651 case ISVCE_CMD_CTL_SETDEFAULT:
5652 {
5653 ((isvce_ctl_setdefault_op_t *) pv_api_op)->s_ive_op.u4_error_code |= 1
5654 << IVE_FATALERROR;
5655 ((isvce_ctl_setdefault_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5656 IH264E_INIT_NOT_DONE;
5657
5658 break;
5659 }
5660 case ISVCE_CMD_CTL_FLUSH:
5661 {
5662 ((isvce_ctl_flush_op_t *) pv_api_op)->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
5663 ((isvce_ctl_flush_op_t *) pv_api_op)->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
5664
5665 break;
5666 }
5667 case ISVCE_CMD_CTL_GETBUFINFO:
5668 {
5669 ((isvce_ctl_getbufinfo_op_t *) pv_api_op)->s_ive_op.u4_error_code |= 1
5670 << IVE_FATALERROR;
5671 ((isvce_ctl_getbufinfo_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5672 IH264E_INIT_NOT_DONE;
5673
5674 break;
5675 }
5676 case ISVCE_CMD_CTL_GETVERSION:
5677 {
5678 ((isvce_ctl_getversioninfo_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5679 1 << IVE_FATALERROR;
5680 ((isvce_ctl_getversioninfo_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5681 IH264E_INIT_NOT_DONE;
5682
5683 break;
5684 }
5685 case ISVCE_CMD_CTL_SET_NUM_CORES:
5686 {
5687 ((isvce_ctl_set_num_cores_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5688 1 << IVE_FATALERROR;
5689 ((isvce_ctl_set_num_cores_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5690 IH264E_INIT_NOT_DONE;
5691
5692 break;
5693 }
5694 case ISVCE_CMD_CTL_GET_ENC_FRAME_DIMENSIONS:
5695 {
5696 ((isvce_ctl_get_enc_dimensions_op_t *) pv_api_op)->u4_error_code |= 1 << IVE_FATALERROR;
5697 ((isvce_ctl_get_enc_dimensions_op_t *) pv_api_op)->u4_error_code |=
5698 IH264E_INIT_NOT_DONE;
5699
5700 break;
5701 }
5702 default:
5703 {
5704 ASSERT(0);
5705 }
5706 }
5707 }
5708
5709 /**
5710 *******************************************************************************
5711 *
5712 * @brief
5713 * Codec control call
5714 *
5715 * @par Description:
5716 * Codec control call which in turn calls appropriate calls based on
5717 *sub-command
5718 *
5719 * @param[in] ps_codec_obj
5720 * Pointer to codec object at API level
5721 *
5722 * @param[in] pv_api_ip
5723 * Pointer to input argument structure
5724 *
5725 * @param[out] pv_api_op
5726 * Pointer to output argument structure
5727 *
5728 * @returns error status
5729 *
5730 * @remarks none
5731 *
5732 *******************************************************************************
5733 */
isvce_ctl(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op,ISVCE_CONTROL_API_COMMAND_TYPE_T e_ctl_cmd)5734 static WORD32 isvce_ctl(iv_obj_t *ps_codec_obj, void *pv_api_ip, void *pv_api_op,
5735 ISVCE_CONTROL_API_COMMAND_TYPE_T e_ctl_cmd)
5736 {
5737 WORD32 i;
5738
5739 isvce_codec_t *ps_codec = (isvce_codec_t *) ps_codec_obj->pv_codec_handle;
5740 isvce_cfg_params_t *ps_cfg = NULL;
5741
5742 IV_STATUS_T ret = IV_SUCCESS;
5743
5744 /* control call is for configuring encoding params, this is not to be called
5745 * before a successful init call */
5746 if(ps_codec->i4_init_done != 1)
5747 {
5748 isvce_ctl_set_error_code(pv_api_op, e_ctl_cmd);
5749
5750 return IV_FAIL;
5751 }
5752
5753 /* make it thread safe */
5754 ithread_mutex_lock(ps_codec->pv_ctl_mutex);
5755
5756 /* find a free config param set to hold current parameters */
5757 if(e_ctl_cmd != ISVCE_CMD_CTL_GET_ENC_FRAME_DIMENSIONS)
5758 {
5759 for(i = 0; i < MAX_ACTIVE_CONFIG_PARAMS; i++)
5760 {
5761 if(0 == ps_codec->as_cfg[i].u4_is_valid)
5762 {
5763 ps_cfg = &ps_codec->as_cfg[i];
5764 break;
5765 }
5766 }
5767
5768 /* If all are invalid, then start overwriting from the head config params */
5769 if(NULL == ps_cfg)
5770 {
5771 ps_cfg = &ps_codec->as_cfg[0];
5772 }
5773
5774 ps_cfg->u4_is_valid = 1;
5775
5776 ps_cfg->s_svc_params = ps_codec->s_cfg.s_svc_params;
5777 ps_cfg->e_cmd = e_ctl_cmd;
5778 }
5779
5780 switch(e_ctl_cmd)
5781 {
5782 case ISVCE_CMD_CTL_SET_DIMENSIONS:
5783 ret = isvce_set_dimensions(pv_api_ip, pv_api_op, ps_cfg);
5784 break;
5785
5786 case ISVCE_CMD_CTL_SET_FRAMERATE:
5787 ret = isvce_set_frame_rate(pv_api_ip, pv_api_op, ps_cfg);
5788 break;
5789
5790 case ISVCE_CMD_CTL_SET_BITRATE:
5791 ret = isvce_set_bit_rate(pv_api_ip, pv_api_op, ps_cfg);
5792 break;
5793
5794 case ISVCE_CMD_CTL_SET_FRAMETYPE:
5795 ret = isvce_set_frame_type(pv_api_ip, pv_api_op, ps_cfg);
5796 break;
5797
5798 case ISVCE_CMD_CTL_SET_QP:
5799 ret = isvce_set_qp(pv_api_ip, pv_api_op, ps_cfg);
5800 break;
5801
5802 case ISVCE_CMD_CTL_SET_ENC_MODE:
5803 ret = isvce_set_enc_mode(pv_api_ip, pv_api_op, ps_cfg);
5804 break;
5805
5806 case ISVCE_CMD_CTL_SET_VBV_PARAMS:
5807 ret = isvce_set_vbv_params(pv_api_ip, pv_api_op, ps_cfg);
5808 break;
5809
5810 case ISVCE_CMD_CTL_SET_AIR_PARAMS:
5811 ret = isvc_set_air_params(pv_api_ip, pv_api_op, ps_cfg);
5812 break;
5813
5814 case ISVCE_CMD_CTL_SET_ME_PARAMS:
5815 ret = isvc_set_me_params(pv_api_ip, pv_api_op, ps_cfg);
5816 break;
5817
5818 case ISVCE_CMD_CTL_SET_IPE_PARAMS:
5819 ret = isvc_set_ipe_params(pv_api_ip, pv_api_op, ps_cfg);
5820 break;
5821
5822 case ISVCE_CMD_CTL_SET_GOP_PARAMS:
5823 ret = isvc_set_gop_params(pv_api_ip, pv_api_op, ps_cfg);
5824 break;
5825
5826 case ISVCE_CMD_CTL_SET_PROFILE_PARAMS:
5827 ret = isvc_set_profile_params(pv_api_ip, pv_api_op, ps_cfg);
5828 break;
5829
5830 case ISVCE_CMD_CTL_SET_DEBLOCK_PARAMS:
5831 ret = isvc_set_deblock_params(pv_api_ip, pv_api_op, ps_cfg);
5832 break;
5833
5834 case ISVCE_CMD_CTL_SET_VUI_PARAMS:
5835 ret = isvce_set_vui_params(pv_api_ip, pv_api_op, ps_cfg);
5836 break;
5837
5838 case ISVCE_CMD_CTL_SET_SEI_MDCV_PARAMS:
5839 ret = isvce_set_sei_mdcv_params(pv_api_ip, pv_api_op, ps_cfg);
5840 break;
5841
5842 case ISVCE_CMD_CTL_SET_SEI_CLL_PARAMS:
5843 ret = isvce_set_sei_cll_params(pv_api_ip, pv_api_op, ps_cfg);
5844 break;
5845
5846 case ISVCE_CMD_CTL_SET_SEI_AVE_PARAMS:
5847 ret = isvce_set_sei_ave_params(pv_api_ip, pv_api_op, ps_cfg);
5848 break;
5849
5850 case ISVCE_CMD_CTL_SET_SEI_CCV_PARAMS:
5851 ret = isvce_set_sei_ccv_params(pv_api_ip, pv_api_op, ps_cfg);
5852 break;
5853
5854 case ISVCE_CMD_CTL_RESET:
5855
5856 /* invalidate config param struct as it is being served right away */
5857 ps_codec->as_cfg[i].u4_is_valid = 0;
5858
5859 ret = isvce_reset(ps_codec_obj, pv_api_ip, pv_api_op);
5860 break;
5861
5862 case ISVCE_CMD_CTL_SETDEFAULT:
5863 {
5864 /* ctrl call I/O structures */
5865 isvce_ctl_setdefault_op_t *ps_op = pv_api_op;
5866
5867 /* invalidate config param struct as it is being served right away */
5868 ps_codec->as_cfg[i].u4_is_valid = 0;
5869
5870 /* error status */
5871 ret = isvce_set_default_params(ps_cfg);
5872
5873 ps_op->s_ive_op.u4_error_code = ret;
5874
5875 break;
5876 }
5877
5878 case ISVCE_CMD_CTL_FLUSH:
5879
5880 /* invalidate config param struct as it is being served right away */
5881 ps_codec->as_cfg[i].u4_is_valid = 0;
5882
5883 ret = isvce_set_flush_mode(ps_codec_obj, pv_api_ip, pv_api_op);
5884 break;
5885
5886 case ISVCE_CMD_CTL_GETBUFINFO:
5887
5888 /* invalidate config param struct as it is being served right away */
5889 ps_codec->as_cfg[i].u4_is_valid = 0;
5890
5891 ret = isvce_get_buf_info(ps_codec_obj->pv_codec_handle, pv_api_ip, pv_api_op);
5892 break;
5893
5894 case ISVCE_CMD_CTL_GETVERSION:
5895 {
5896 /* ctrl call I/O structures */
5897 isvce_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
5898 isvce_ctl_getversioninfo_op_t *ps_op = pv_api_op;
5899
5900 /* invalidate config param struct as it is being served right away */
5901 ps_codec->as_cfg[i].u4_is_valid = 0;
5902
5903 /* error status */
5904 ps_op->s_ive_op.u4_error_code = IV_SUCCESS;
5905
5906 if(ps_ip->s_ive_ip.u4_version_bufsize <= 0)
5907 {
5908 ps_op->s_ive_op.u4_error_code = IH264E_CXA_VERS_BUF_INSUFFICIENT;
5909 ret = IV_FAIL;
5910 }
5911 else
5912 {
5913 ret = ih264e_get_version((CHAR *) ps_ip->s_ive_ip.pu1_version,
5914 ps_ip->s_ive_ip.u4_version_bufsize);
5915
5916 if(ret != IV_SUCCESS)
5917 {
5918 ps_op->s_ive_op.u4_error_code = IH264E_CXA_VERS_BUF_INSUFFICIENT;
5919 ret = IV_FAIL;
5920 }
5921 }
5922 break;
5923 }
5924
5925 case ISVCE_CMD_CTL_SET_NUM_CORES:
5926 ret = isvce_set_num_cores(pv_api_ip, pv_api_op, ps_cfg);
5927 break;
5928
5929 case ISVCE_CMD_CTL_GET_ENC_FRAME_DIMENSIONS:
5930 {
5931 ps_cfg = NULL;
5932
5933 for(i = 0; i < MAX_ACTIVE_CONFIG_PARAMS; i++)
5934 {
5935 if(ps_codec->as_cfg[i].u4_is_valid &&
5936 (ps_codec->as_cfg[i].e_cmd == ISVCE_CMD_CTL_SET_DIMENSIONS))
5937 {
5938 ps_cfg = &ps_codec->as_cfg[i];
5939
5940 break;
5941 }
5942 }
5943
5944 if(NULL == ps_cfg)
5945 {
5946 ((isvce_ctl_get_enc_dimensions_op_t *) pv_api_op)->u4_error_code |=
5947 1 << IVE_FATALERROR;
5948 ((isvce_ctl_get_enc_dimensions_op_t *) pv_api_op)->u4_error_code |=
5949 IH264E_WIDTH_NOT_SUPPORTED;
5950 ((isvce_ctl_get_enc_dimensions_op_t *) pv_api_op)->u4_error_code |=
5951 IH264E_HEIGHT_NOT_SUPPORTED;
5952
5953 return IV_FAIL;
5954 }
5955
5956 ret = isvce_get_enc_frame_dimensions((isvce_ctl_get_enc_dimensions_ip_t *) pv_api_ip,
5957 (isvce_ctl_get_enc_dimensions_op_t *) pv_api_op,
5958 ps_cfg);
5959
5960 break;
5961 }
5962
5963 default:
5964 /* invalidate config param struct as it is being served right away */
5965 ps_codec->as_cfg[i].u4_is_valid = 0;
5966
5967 DEBUG("Warning !! unrecognized control api command \n");
5968 break;
5969 }
5970
5971 ithread_mutex_unlock(ps_codec->pv_ctl_mutex);
5972
5973 return ret;
5974 }
5975
5976 /**
5977 *******************************************************************************
5978 *
5979 * @brief
5980 * Codec entry point function. All the function calls to the codec are done
5981 * using this function with different values specified in command
5982 *
5983 * @par Description:
5984 * Arguments are tested for validity and then based on the command
5985 * appropriate function is called
5986 *
5987 * @param[in] ps_handle
5988 * API level handle for codec
5989 *
5990 * @param[in] pv_api_ip
5991 * Input argument structure
5992 *
5993 * @param[out] pv_api_op
5994 * Output argument structure
5995 *
5996 * @returns error_status
5997 *
5998 * @remarks
5999 *
6000 *******************************************************************************
6001 */
isvce_api_function(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op,isvce_api_cmds_t * ps_iv_api_cmds)6002 IV_STATUS_T isvce_api_function(iv_obj_t *ps_handle, void *pv_api_ip, void *pv_api_op,
6003 isvce_api_cmds_t *ps_iv_api_cmds)
6004 {
6005 IV_STATUS_T e_status;
6006 WORD32 ret;
6007
6008 ISVCE_API_COMMAND_TYPE_T e_cmd = ps_iv_api_cmds->e_cmd;
6009 ISVCE_CONTROL_API_COMMAND_TYPE_T e_ctl_cmd = ps_iv_api_cmds->e_ctl_cmd;
6010
6011 /* validate input / output structures */
6012 e_status = api_check_struct_sanity(ps_handle, pv_api_ip, pv_api_op, ps_iv_api_cmds);
6013
6014 if(e_status != IV_SUCCESS)
6015 {
6016 DEBUG("error code = %d\n", *((UWORD32 *) pv_api_op + 1));
6017 return IV_FAIL;
6018 }
6019
6020 switch(e_cmd)
6021 {
6022 case ISVCE_CMD_GET_NUM_MEM_REC:
6023 ret = isvce_get_num_rec(pv_api_ip, pv_api_op);
6024 break;
6025
6026 case ISVCE_CMD_FILL_NUM_MEM_REC:
6027 ret = isvce_fill_num_mem_rec(pv_api_ip, pv_api_op);
6028 break;
6029
6030 case ISVCE_CMD_INIT:
6031 ret = isvce_init_mem_rec(ps_handle, pv_api_ip, pv_api_op);
6032 break;
6033
6034 case ISVCE_CMD_RETRIEVE_MEMREC:
6035 ret = isvce_retrieve_memrec(ps_handle, pv_api_ip, pv_api_op);
6036 break;
6037
6038 case ISVCE_CMD_VIDEO_CTL:
6039 ret = isvce_ctl(ps_handle, pv_api_ip, pv_api_op, e_ctl_cmd);
6040 break;
6041
6042 case ISVCE_CMD_VIDEO_ENCODE:
6043 ret = isvce_encode(ps_handle, pv_api_ip, pv_api_op);
6044 break;
6045
6046 default:
6047 ret = IV_FAIL;
6048 break;
6049 }
6050
6051 return (IV_STATUS_T) ret;
6052 }
6053