1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20 /*****************************************************************************/
21 /* */
22 /* File Name : decoder_api_main.c */
23 /* */
24 /* Description : Functions which recieve the API call from user */
25 /* */
26 /* List of Functions : <List the functions defined in this file> */
27 /* */
28 /* Issues / Problems : None */
29 /* */
30 /* Revision History : */
31 /* */
32 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
33 /* 30 05 2007 Rajneesh Creation */
34 /* */
35 /*****************************************************************************/
36
37 /*****************************************************************************/
38 /* File Includes */
39 /*****************************************************************************/
40
41 /* System include files */
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <stddef.h>
45 #include <string.h>
46
47 /* User include files */
48 #include "iv_datatypedef.h"
49 #include "iv.h"
50 #include "ivd.h"
51 #include "ithread.h"
52
53 #include "impeg2_job_queue.h"
54 #include "impeg2_macros.h"
55 #include "impeg2_buf_mgr.h"
56 #include "impeg2_disp_mgr.h"
57 #include "impeg2_defs.h"
58 #include "impeg2_platform_macros.h"
59 #include "impeg2_inter_pred.h"
60 #include "impeg2_idct.h"
61 #include "impeg2_format_conv.h"
62 #include "impeg2_mem_func.h"
63
64 #include "impeg2d.h"
65 #include "impeg2d_api.h"
66 #include "impeg2d_bitstream.h"
67 #include "impeg2d_debug.h"
68 #include "impeg2d_structs.h"
69 #include "impeg2d_mc.h"
70 #include "impeg2d_pic_proc.h"
71 #include "impeg2d_deinterlace.h"
72
73 #define NUM_FRAMES_LIMIT_ENABLED 0
74
75 #ifdef LOGO_EN
76 #include "impeg2_ittiam_logo.h"
77 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht) impeg2_insert_logo(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht);
78 #else
79 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht)
80 #endif
81
82 #if NUM_FRAMES_LIMIT_ENABLED
83 #define NUM_FRAMES_LIMIT 10000
84 #else
85 #define NUM_FRAMES_LIMIT 0x7FFFFFFF
86 #endif
87
88 #define CODEC_NAME "MPEG2VDEC"
89 #define CODEC_RELEASE_TYPE "eval"
90 #define CODEC_RELEASE_VER "01.00"
91 #define CODEC_VENDOR "ITTIAM"
92
93 #ifdef ANDROID
94 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
95 strcpy(version_string,"@(#)Id:"); \
96 strcat(version_string,codec_name); \
97 strcat(version_string,"_"); \
98 strcat(version_string,codec_release_type); \
99 strcat(version_string," Ver:"); \
100 strcat(version_string,codec_release_ver); \
101 strcat(version_string," Released by "); \
102 strcat(version_string,codec_vendor);
103 #else
104 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
105 strcpy(version_string,"@(#)Id:"); \
106 strcat(version_string,codec_name); \
107 strcat(version_string,"_"); \
108 strcat(version_string,codec_release_type); \
109 strcat(version_string," Ver:"); \
110 strcat(version_string,codec_release_ver); \
111 strcat(version_string," Released by "); \
112 strcat(version_string,codec_vendor); \
113 strcat(version_string," Build: "); \
114 strcat(version_string,__DATE__); \
115 strcat(version_string," @ "); \
116 strcat(version_string,__TIME__);
117 #endif
118
119
120 #define MIN_OUT_BUFS_420 3
121 #define MIN_OUT_BUFS_422ILE 1
122 #define MIN_OUT_BUFS_RGB565 1
123 #define MIN_OUT_BUFS_420SP 2
124
125
126 void impeg2d_init_arch(void *pv_codec);
127 void impeg2d_init_function_ptr(void *pv_codec);
128 UWORD32 impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht, WORD32 u1_chroma_format,UWORD32 *p_buf_size);
129
130 /*****************************************************************************/
131 /* */
132 /* Function Name : impeg2d_api_rel_display_frame */
133 /* */
134 /* Description : Release displ buffers that will be shared between decoder */
135 /* and application */
136 /* Inputs : Error message */
137 /* Globals : None */
138 /* Processing : Just prints error message to console */
139 /* Outputs : Error mesage to the console */
140 /* Returns : None */
141 /* */
142 /* Issues : <List any issues or problems with this function> */
143 /* */
144 /* Revision History: */
145 /* */
146 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
147 /* 27 05 2006 Sankar Creation */
148 /* */
149 /*****************************************************************************/
impeg2d_api_rel_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)150 IV_API_CALL_STATUS_T impeg2d_api_rel_display_frame(iv_obj_t *ps_dechdl,
151 void *pv_api_ip,
152 void *pv_api_op)
153 {
154
155 ivd_rel_display_frame_ip_t *dec_rel_disp_ip;
156 ivd_rel_display_frame_op_t *dec_rel_disp_op;
157
158 dec_state_t *ps_dec_state;
159 dec_state_multi_core_t *ps_dec_state_multi_core;
160
161
162 dec_rel_disp_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
163 dec_rel_disp_op = (ivd_rel_display_frame_op_t *)pv_api_op;
164
165 dec_rel_disp_op->u4_error_code = 0;
166 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
167 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
168
169
170 /* If not in shared disp buf mode, return */
171 if(0 == ps_dec_state->u4_share_disp_buf)
172 return IV_SUCCESS;
173
174 if(NULL == ps_dec_state->pv_pic_buf_mg)
175 return IV_SUCCESS;
176
177
178 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, dec_rel_disp_ip->u4_disp_buf_id, BUF_MGR_DISP);
179
180 return IV_SUCCESS;
181 }
182
183 /*****************************************************************************/
184 /* */
185 /* Function Name : impeg2d_api_set_display_frame */
186 /* */
187 /* Description : Sets display buffers that will be shared between decoder */
188 /* and application */
189 /* Inputs : Error message */
190 /* Globals : None */
191 /* Processing : Just prints error message to console */
192 /* Outputs : Error mesage to the console */
193 /* Returns : None */
194 /* */
195 /* Issues : <List any issues or problems with this function> */
196 /* */
197 /* Revision History: */
198 /* */
199 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
200 /* 27 05 2006 Sankar Creation */
201 /* */
202 /*****************************************************************************/
impeg2d_api_set_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)203 IV_API_CALL_STATUS_T impeg2d_api_set_display_frame(iv_obj_t *ps_dechdl,
204 void *pv_api_ip,
205 void *pv_api_op)
206 {
207
208 ivd_set_display_frame_ip_t *dec_disp_ip;
209 ivd_set_display_frame_op_t *dec_disp_op;
210
211 UWORD32 i;
212 dec_state_t *ps_dec_state;
213 dec_state_multi_core_t *ps_dec_state_multi_core;
214 UWORD32 u4_num_disp_bufs;
215 UWORD32 u4_disp_buf_size[3];
216 UWORD32 num_bufs;
217
218
219 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
220 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
221 dec_disp_op->u4_error_code = 0;
222
223 u4_num_disp_bufs = dec_disp_ip->num_disp_bufs;
224 if(u4_num_disp_bufs > BUF_MGR_MAX_CNT)
225 u4_num_disp_bufs = BUF_MGR_MAX_CNT;
226
227 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
228 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
229
230 num_bufs = dec_disp_ip->s_disp_buffer[0].u4_num_bufs;
231
232 if(ps_dec_state->u4_share_disp_buf)
233 {
234 pic_buf_t *ps_pic_buf;
235 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
236
237 /* Get the sizes of the first buffer structure. Compare this with the
238 * rest to make sure all the buffers are of the same size.
239 */
240 u4_disp_buf_size[0] =
241 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[0];
242 u4_disp_buf_size[1] =
243 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[1];
244 u4_disp_buf_size[2] =
245 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[2];
246 for(i = 0; i < u4_num_disp_bufs; i++)
247 {
248 /* Verify all buffer structures have the same sized buffers as the
249 * first buffer structure*/
250 if ((dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]
251 != u4_disp_buf_size[0])
252 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]
253 != u4_disp_buf_size[1])
254 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]
255 != u4_disp_buf_size[2]))
256 {
257 return IV_FAIL;
258 }
259 /* Verify all buffer structures have the same number of
260 * buffers (e.g. y, u, v) */
261 if (dec_disp_ip->s_disp_buffer[i].u4_num_bufs != num_bufs)
262 {
263 return IV_FAIL;
264 }
265
266 ps_pic_buf->pu1_y = dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
267 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
268 {
269 ps_pic_buf->pu1_u = dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
270 ps_pic_buf->pu1_v = dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
271 }
272 else
273 {
274 ps_pic_buf->pu1_u = ps_dec_state->pu1_chroma_ref_buf[i];
275 ps_pic_buf->pu1_v = ps_dec_state->pu1_chroma_ref_buf[i] +
276 ((ps_dec_state->u2_create_max_width * ps_dec_state->u2_create_max_height) >> 2);
277 }
278
279 ps_pic_buf->i4_buf_id = i;
280
281 ps_pic_buf->u1_used_as_ref = 0;
282
283 ps_pic_buf->u4_ts = 0;
284
285 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
286 impeg2_buf_mgr_set_status(ps_dec_state->pv_pic_buf_mg, i, BUF_MGR_DISP);
287 ps_pic_buf++;
288
289 }
290 }
291 memcpy(&(ps_dec_state->as_disp_buffers[0]),
292 &(dec_disp_ip->s_disp_buffer),
293 u4_num_disp_bufs * sizeof(ivd_out_bufdesc_t));
294
295 return IV_SUCCESS;
296
297 }
298
impeg2d_api_set_num_cores(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)299 IV_API_CALL_STATUS_T impeg2d_api_set_num_cores(iv_obj_t *ps_dechdl,
300 void *pv_api_ip,
301 void *pv_api_op)
302 {
303 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
304 impeg2d_ctl_set_num_cores_op_t *ps_op;
305 dec_state_t *ps_dec_state;
306 dec_state_multi_core_t *ps_dec_state_multi_core;
307
308 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
309 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
310
311 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
312 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
313
314 if(ps_ip->u4_num_cores > 0)
315 {
316
317
318 WORD32 i;
319 for(i = 0; i < MAX_THREADS; i++)
320 ps_dec_state_multi_core->ps_dec_state[i]->i4_num_cores = ps_ip->u4_num_cores;
321 }
322 else
323 {
324 ps_dec_state->i4_num_cores = 1;
325 }
326 ps_op->u4_error_code = IV_SUCCESS;
327
328 return IV_SUCCESS;
329 }
330
impeg2d_api_get_seq_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)331 IV_API_CALL_STATUS_T impeg2d_api_get_seq_info(iv_obj_t *ps_dechdl,
332 void *pv_api_ip,
333 void *pv_api_op)
334 {
335 impeg2d_ctl_get_seq_info_ip_t *ps_ip;
336 impeg2d_ctl_get_seq_info_op_t *ps_op;
337 dec_state_t *ps_codec;
338 dec_state_multi_core_t *ps_dec_state_multi_core;
339
340 ps_ip = (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip;
341 ps_op = (impeg2d_ctl_get_seq_info_op_t *)pv_api_op;
342
343 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
344 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
345 UNUSED(ps_ip);
346 if(ps_codec->u2_header_done == 1)
347 {
348 ps_op->u1_aspect_ratio_information = ps_codec->u2_aspect_ratio_info;
349 ps_op->u1_frame_rate_code = ps_codec->u2_frame_rate_code;
350 ps_op->u1_frame_rate_extension_n = ps_codec->u2_frame_rate_extension_n;
351 ps_op->u1_frame_rate_extension_d = ps_codec->u2_frame_rate_extension_d;
352 if(ps_codec->u1_seq_disp_extn_present == 1)
353 {
354 ps_op->u1_video_format = ps_codec->u1_video_format;
355 ps_op->u1_colour_primaries = ps_codec->u1_colour_primaries;
356 ps_op->u1_transfer_characteristics = ps_codec->u1_transfer_characteristics;
357 ps_op->u1_matrix_coefficients = ps_codec->u1_matrix_coefficients;
358 ps_op->u2_display_horizontal_size = ps_codec->u2_display_horizontal_size;
359 ps_op->u2_display_vertical_size = ps_codec->u2_display_vertical_size;
360 }
361 else
362 {
363 ps_op->u1_video_format = 5;
364 ps_op->u1_colour_primaries = 2;
365 ps_op->u1_transfer_characteristics = 2;
366 ps_op->u1_matrix_coefficients = 2;
367 ps_op->u2_display_horizontal_size = ps_codec->u2_horizontal_size;
368 ps_op->u2_display_vertical_size = ps_codec->u2_vertical_size;
369 }
370 ps_op->u4_error_code = IV_SUCCESS;
371 return IV_SUCCESS;
372 }
373 else
374 {
375 ps_op->u4_error_code = IV_FAIL;
376 return IV_FAIL;
377 }
378 }
379
380 /**
381 *******************************************************************************
382 *
383 * @brief
384 * Sets Processor type
385 *
386 * @par Description:
387 * Sets Processor type
388 *
389 * @param[in] ps_codec_obj
390 * Pointer to codec object at API level
391 *
392 * @param[in] pv_api_ip
393 * Pointer to input argument structure
394 *
395 * @param[out] pv_api_op
396 * Pointer to output argument structure
397 *
398 * @returns Status
399 *
400 * @remarks
401 *
402 *
403 *******************************************************************************
404 */
405
impeg2d_set_processor(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)406 IV_API_CALL_STATUS_T impeg2d_set_processor(iv_obj_t *ps_codec_obj,
407 void *pv_api_ip,
408 void *pv_api_op)
409 {
410 impeg2d_ctl_set_processor_ip_t *ps_ip;
411 impeg2d_ctl_set_processor_op_t *ps_op;
412 dec_state_t *ps_codec;
413 dec_state_multi_core_t *ps_dec_state_multi_core;
414
415 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
416 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
417
418 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
419 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
420
421 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
422 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
423
424 impeg2d_init_function_ptr(ps_codec);
425
426
427 ps_op->u4_error_code = 0;
428 return IV_SUCCESS;
429 }
430 /*****************************************************************************/
431 /* */
432 /* Function Name : impeg2d_fill_mem_rec */
433 /* */
434 /* Description : */
435 /* Inputs : */
436 /* Globals : */
437 /* Processing : */
438 /* Outputs : */
439 /* Returns : */
440 /* */
441 /* Issues : */
442 /* */
443 /* Revision History: */
444 /* */
445 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
446 /* 17 09 2007 Rajendra C Y Draft */
447 /* */
448 /*****************************************************************************/
impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t * ps_ip,impeg2d_fill_mem_rec_op_t * ps_op)449 void impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t *ps_ip,
450 impeg2d_fill_mem_rec_op_t *ps_op)
451 {
452 UWORD32 u4_i;
453
454 UWORD8 u1_no_rec = 0;
455 UWORD32 max_frm_width,max_frm_height,max_frm_size;
456 iv_mem_rec_t *ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
457 WORD32 i4_num_threads;
458 WORD32 i4_share_disp_buf, i4_chroma_format;
459 WORD32 i4_chroma_size;
460 UWORD32 u4_deinterlace;
461 UNUSED(u4_deinterlace);
462 max_frm_width = ALIGN16(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd);
463 /* In error clips with field prediction, the mv may incorrectly refer to
464 * the last MB row, causing an out of bounds read access. Allocating 8 extra
465 * rows to handle this. Adding another extra row to handle half_y prediction.
466 */
467 max_frm_height = ALIGN32(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht) + 9;
468
469 max_frm_size = (max_frm_width * max_frm_height * 3) >> 1;/* 420 P */
470
471 i4_chroma_size = max_frm_width * max_frm_height / 4;
472
473 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_share_disp_buf))
474 {
475 #ifndef LOGO_EN
476 i4_share_disp_buf = ps_ip->u4_share_disp_buf;
477 #else
478 i4_share_disp_buf = 0;
479 #endif
480 }
481 else
482 {
483 i4_share_disp_buf = 0;
484 }
485 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, e_output_format))
486 {
487 i4_chroma_format = ps_ip->e_output_format;
488 }
489 else
490 {
491 i4_chroma_format = -1;
492 }
493
494 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_deinterlace))
495 {
496 u4_deinterlace = ps_ip->u4_deinterlace;
497 }
498 else
499 {
500 u4_deinterlace = 0;
501 }
502
503
504 if( (i4_chroma_format != IV_YUV_420P) &&
505 (i4_chroma_format != IV_YUV_420SP_UV) &&
506 (i4_chroma_format != IV_YUV_420SP_VU))
507 {
508 i4_share_disp_buf = 0;
509 }
510
511 /* Disable deinterlacer in shared mode */
512 if(i4_share_disp_buf)
513 {
514 u4_deinterlace = 0;
515 }
516
517 /*************************************************************************/
518 /* Fill the memory requirement XDM Handle */
519 /*************************************************************************/
520 /* ! */
521 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
522 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
523 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
524
525 ps_mem_rec++;
526 u1_no_rec++;
527
528 {
529 /*************************************************************************/
530 /* Fill the memory requirement for threads context */
531 /*************************************************************************/
532 /* ! */
533 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
534 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
535 ps_mem_rec->u4_mem_size = sizeof(dec_state_multi_core_t);
536
537 ps_mem_rec++;
538 u1_no_rec++;
539 }
540
541 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
542 {
543 /*************************************************************************/
544 /* Fill the memory requirement for MPEG2 Decoder Context */
545 /*************************************************************************/
546 /* ! */
547 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
548 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
549 ps_mem_rec->u4_mem_size = sizeof(dec_state_t);
550
551 ps_mem_rec++;
552 u1_no_rec++;
553
554 /* To store thread handle */
555 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
556 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
557 ps_mem_rec->u4_mem_size = ithread_get_handle_size();
558
559 ps_mem_rec++;
560 u1_no_rec++;
561
562 #ifdef KEEP_THREADS_ACTIVE
563 /* To store start/done mutex */
564 ps_mem_rec->u4_mem_alignment = 8 /* 8 byte alignment*/;
565 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
566 /* Request memory to hold mutex (start/done) */
567 WORD32 size = 2 * ithread_get_mutex_lock_size();
568 ps_mem_rec->u4_mem_size = size;
569
570 ps_mem_rec++;
571 u1_no_rec++;
572
573 /* To store start/done condition variables */
574 ps_mem_rec->u4_mem_alignment = 8 /* 8 byte alignment*/;
575 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
576 /* Request memory to hold condition variables */
577 size = 2 * ithread_get_cond_struct_size();
578 ps_mem_rec->u4_mem_size = size;
579
580 ps_mem_rec++;
581 u1_no_rec++;
582 #endif
583
584 /*************************************************************************/
585 /* Fill the memory requirement for Motion Compensation Buffers */
586 /*************************************************************************/
587 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
588 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_SCRATCH_MEM;
589
590 /* for mc_fw_buf.pu1_y */
591 ps_mem_rec->u4_mem_size = MB_LUMA_MEM_SIZE;
592
593 /* for mc_fw_buf.pu1_u */
594 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
595
596 /* for mc_fw_buf.pu1_v */
597 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
598
599 /* for mc_bk_buf.pu1_y */
600 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
601
602 /* for mc_bk_buf.pu1_u */
603 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
604
605 /* for mc_bk_buf.pu1_v */
606 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
607
608 /* for mc_buf.pu1_y */
609 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
610
611 /* for mc_buf.pu1_u */
612 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
613
614 /* for mc_buf.pu1_v */
615 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
616
617 ps_mem_rec++;
618 u1_no_rec++;
619
620
621 /*************************************************************************/
622 /* Fill the memory requirement Stack Context */
623 /*************************************************************************/
624 /* ! */
625 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
626 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
627 ps_mem_rec->u4_mem_size = 392;
628
629 ps_mem_rec++;
630 u1_no_rec++;
631 }
632
633
634
635 {
636 /*************************************************************************/
637 /* Fill the memory requirement for Picture Buffer Manager */
638 /*************************************************************************/
639 /* ! */
640 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
641 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
642 ps_mem_rec->u4_mem_size = sizeof(buf_mgr_t) + sizeof(pic_buf_t) * BUF_MGR_MAX_CNT;
643
644 ps_mem_rec++;
645 u1_no_rec++;
646 }
647 /*************************************************************************/
648 /* Internal Frame Buffers */
649 /*************************************************************************/
650 /* ! */
651
652 {
653 for(u4_i = 0; u4_i < NUM_INT_FRAME_BUFFERS; u4_i++)
654 {
655 /* ! */
656 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
657 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
658 if(0 == i4_share_disp_buf)
659 ps_mem_rec->u4_mem_size = max_frm_size;
660 else if(IV_YUV_420P != i4_chroma_format)
661 {
662 /* If color format is not 420P and it is shared, then allocate for chroma */
663 ps_mem_rec->u4_mem_size = i4_chroma_size * 2;
664 }
665 else
666 ps_mem_rec->u4_mem_size = 64;
667 ps_mem_rec++;
668 u1_no_rec++;
669 }
670 }
671
672 ps_mem_rec->u4_mem_alignment = 128;
673 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
674 ps_mem_rec->u4_mem_size = MAX_BITSTREAM_BUFFER_SIZE + MIN_BUFFER_BYTES_AT_EOS;
675 ps_mem_rec++;
676 u1_no_rec++;
677
678 {
679 WORD32 i4_job_queue_size;
680 WORD32 i4_num_jobs;
681
682 /* One job per row of MBs */
683 i4_num_jobs = max_frm_height >> 4;
684
685 /* One format convert/frame copy job per row of MBs for non-shared mode*/
686 i4_num_jobs += max_frm_height >> 4;
687
688
689 i4_job_queue_size = impeg2_jobq_ctxt_size();
690 i4_job_queue_size += i4_num_jobs * sizeof(job_t);
691 ps_mem_rec->u4_mem_size = i4_job_queue_size;
692 ps_mem_rec->u4_mem_alignment = 128;
693 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
694
695 ps_mem_rec++;
696 u1_no_rec++;
697
698 }
699
700 ps_mem_rec->u4_mem_alignment = 128;
701 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
702 ps_mem_rec->u4_mem_size = impeg2d_deint_ctxt_size();
703 ps_mem_rec++;
704 u1_no_rec++;
705
706 ps_mem_rec->u4_mem_alignment = 128;
707 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
708
709 if(IV_YUV_420P != i4_chroma_format)
710 ps_mem_rec->u4_mem_size = max_frm_size;
711 else
712 ps_mem_rec->u4_mem_size = 64;
713
714 ps_mem_rec++;
715 u1_no_rec++;
716
717 ps_mem_rec->u4_mem_alignment = 128;
718 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
719 ps_mem_rec->u4_mem_size = sizeof(iv_mem_rec_t) * (NUM_MEM_RECORDS);
720 ps_mem_rec++;
721 u1_no_rec++;
722
723 ps_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = u1_no_rec;
724 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
725 }
726
727
728 /*****************************************************************************/
729 /* */
730 /* Function Name : impeg2d_api_get_version */
731 /* */
732 /* Description : */
733 /* */
734 /* Inputs : */
735 /* Globals : <Does it use any global variables?> */
736 /* Outputs : */
737 /* Returns : void */
738 /* */
739 /* Issues : none */
740 /* */
741 /* Revision History: */
742 /* */
743 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
744 /* 22 10 2008 100356 Draft */
745 /* */
746 /*****************************************************************************/
impeg2d_api_get_version(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)747 IV_API_CALL_STATUS_T impeg2d_api_get_version(iv_obj_t *ps_dechdl,
748 void *pv_api_ip,
749 void *pv_api_op)
750 {
751 char au1_version_string[512];
752
753 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
754 impeg2d_ctl_getversioninfo_op_t *ps_op;
755
756 UNUSED(ps_dechdl);
757
758 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
759 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
760
761 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
762
763 VERSION(au1_version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
764 CODEC_VENDOR);
765
766 if((WORD32)ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size <= 0)
767 {
768 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
769 return (IV_FAIL);
770 }
771
772 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size
773 >= (strlen(au1_version_string) + 1))
774 {
775 memcpy(ps_ip->s_ivd_ctl_getversioninfo_ip_t.pv_version_buffer,
776 au1_version_string, (strlen(au1_version_string) + 1));
777 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
778 }
779 else
780 {
781 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
782 }
783
784 return (IV_SUCCESS);
785 }
786
787 /*****************************************************************************/
788 /* */
789 /* Function Name : impeg2d_api_get_buf_info */
790 /* */
791 /* Description : */
792 /* */
793 /* Inputs : */
794 /* Globals : <Does it use any global variables?> */
795 /* Outputs : */
796 /* Returns : void */
797 /* */
798 /* Issues : none */
799 /* */
800 /* Revision History: */
801 /* */
802 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
803 /* 22 10 2008 100356 Draft */
804 /* */
805 /*****************************************************************************/
impeg2d_api_get_buf_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)806 IV_API_CALL_STATUS_T impeg2d_api_get_buf_info(iv_obj_t *ps_dechdl,
807 void *pv_api_ip,
808 void *pv_api_op)
809 {
810 dec_state_t *ps_dec_state;
811 dec_state_multi_core_t *ps_dec_state_multi_core;
812 impeg2d_ctl_getbufinfo_ip_t *ps_ctl_bufinfo_ip =
813 (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
814 impeg2d_ctl_getbufinfo_op_t *ps_ctl_bufinfo_op =
815 (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
816 UWORD32 u4_i, u4_stride, u4_height;
817 UNUSED(ps_ctl_bufinfo_ip);
818
819 ps_dec_state_multi_core =
820 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
821 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
822
823 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs = 1;
824 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 1;
825
826 for(u4_i = 0; u4_i < IVD_VIDDEC_MAX_IO_BUFFERS; u4_i++)
827 {
828 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
829 0;
830 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[u4_i] =
831 0;
832 }
833
834 for(u4_i = 0;
835 u4_i < ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs;
836 u4_i++)
837 {
838 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
839 MAX_BITSTREAM_BUFFER_SIZE;
840 }
841
842 if (0 == ps_dec_state->u4_frm_buf_stride)
843 {
844 if (1 == ps_dec_state->u2_header_done)
845 {
846 u4_stride = ps_dec_state->u2_horizontal_size;
847 }
848 else
849 {
850 u4_stride = ps_dec_state->u2_create_max_width;
851 }
852 }
853 else
854 {
855 u4_stride = ps_dec_state->u4_frm_buf_stride;
856 }
857 u4_stride = ALIGN16(u4_stride);
858 u4_height = ALIGN32(ps_dec_state->u2_frame_height) + 9;
859
860 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
861 impeg2d_get_outbuf_size(
862 u4_stride,
863 u4_height,
864 ps_dec_state->i4_chromaFormat,
865 &ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0]);
866
867 if (0 == ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs)
868 {
869 //Invalid chroma format; Error code may be updated, verify in testing if needed
870 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code =
871 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
872 return IV_FAIL;
873 }
874
875 /* Adding initialization for 2 uninitialized values */
876 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs = 1;
877 if(ps_dec_state->u4_share_disp_buf)
878 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs =
879 NUM_INT_FRAME_BUFFERS;
880 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_size = MAX_FRM_SIZE;
881
882 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = IV_SUCCESS;
883
884 return (IV_SUCCESS);
885 }
886
887 /*****************************************************************************/
888 /* */
889 /* Function Name : impeg2d_api_set_flush_mode */
890 /* */
891 /* Description : */
892 /* */
893 /* Inputs : */
894 /* Globals : <Does it use any global variables?> */
895 /* Outputs : */
896 /* Returns : void */
897 /* */
898 /* Issues : none */
899 /* */
900 /* Revision History: */
901 /* */
902 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
903 /* 08 06 2009 100356 RAVI */
904 /* */
905 /*****************************************************************************/
impeg2d_api_set_flush_mode(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)906 IV_API_CALL_STATUS_T impeg2d_api_set_flush_mode(iv_obj_t *ps_dechdl,
907 void *pv_api_ip,
908 void *pv_api_op)
909 {
910 dec_state_t *ps_dec_state;
911 dec_state_multi_core_t *ps_dec_state_multi_core;
912 impeg2d_ctl_flush_op_t *ps_ctl_dec_op =
913 (impeg2d_ctl_flush_op_t*)pv_api_op;
914
915 UNUSED(pv_api_ip);
916
917 ps_dec_state_multi_core =
918 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
919 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
920
921 ps_dec_state->u1_flushfrm = 1;
922
923 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_size =
924 sizeof(impeg2d_ctl_flush_op_t);
925 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_error_code = IV_SUCCESS;
926
927 return (IV_SUCCESS);
928 }
929
930 /*****************************************************************************/
931 /* */
932 /* Function Name : impeg2d_api_set_default */
933 /* */
934 /* Description : */
935 /* */
936 /* Inputs : */
937 /* Globals : <Does it use any global variables?> */
938 /* Outputs : */
939 /* Returns : void */
940 /* */
941 /* Issues : none */
942 /* */
943 /* Revision History: */
944 /* */
945 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
946 /* 08 06 2009 100356 RAVI */
947 /* */
948 /*****************************************************************************/
impeg2d_api_set_default(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)949 IV_API_CALL_STATUS_T impeg2d_api_set_default(iv_obj_t *ps_dechdl,
950 void *pv_api_ip,
951 void *pv_api_op)
952 {
953 dec_state_t *ps_dec_state;
954 dec_state_multi_core_t *ps_dec_state_multi_core;
955 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op =
956 (impeg2d_ctl_set_config_op_t *)pv_api_op;
957
958 UNUSED(pv_api_ip);
959
960 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
961 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_size =
962 sizeof(impeg2d_ctl_set_config_op_t);
963
964 ps_dec_state_multi_core =
965 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
966 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
967
968 ps_dec_state->u1_flushfrm = 0;
969 ps_dec_state->u2_decode_header = 1;
970
971 if (1 == ps_dec_state->u2_header_done)
972 {
973 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
974 }
975
976 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
977
978 return (IV_SUCCESS);
979
980 }
981
982 /*****************************************************************************/
983 /* */
984 /* Function Name : impeg2d_api_reset */
985 /* */
986 /* Description : */
987 /* */
988 /* Inputs : */
989 /* Globals : <Does it use any global variables?> */
990 /* Outputs : */
991 /* Returns : void */
992 /* */
993 /* Issues : none */
994 /* */
995 /* Revision History: */
996 /* */
997 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
998 /* 08 06 2009 100356 RAVI */
999 /* */
1000 /*****************************************************************************/
impeg2d_api_reset(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1001 IV_API_CALL_STATUS_T impeg2d_api_reset(iv_obj_t *ps_dechdl,
1002 void *pv_api_ip,
1003 void *pv_api_op)
1004 {
1005 dec_state_t *ps_dec_state;
1006 dec_state_multi_core_t *ps_dec_state_multi_core;
1007 UNUSED(pv_api_ip);
1008 impeg2d_ctl_reset_op_t *s_ctl_reset_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
1009
1010 WORD32 i4_num_threads;
1011
1012 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1013 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1014
1015 if(ps_dec_state_multi_core != NULL)
1016 {
1017 impeg2_buf_mgr_reset(ps_dec_state->pv_pic_buf_mg);
1018 /* Display buffer manager init behaves like a reset
1019 * as it doesn't need to preserve picture buffer addresses
1020 * like buffer manager */
1021 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr);
1022
1023 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1024 {
1025 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1026
1027
1028 /* --------------------------------------------------------------------- */
1029 /* Initializations */
1030
1031 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1032 ps_dec_state->u4_frm_buf_stride = 0;
1033 ps_dec_state->i4_pic_count = 0;
1034 ps_dec_state->u2_is_mpeg2 = 0;
1035 ps_dec_state->aps_ref_pics[0] = NULL;
1036 ps_dec_state->aps_ref_pics[1] = NULL;
1037 ps_dec_state->ps_deint_pic = NULL;
1038 }
1039 }
1040 else
1041 {
1042 s_ctl_reset_op->s_ivd_ctl_reset_op_t.u4_error_code =
1043 IMPEG2D_INIT_NOT_DONE;
1044 }
1045
1046 return(IV_SUCCESS);
1047 }
1048
1049 /*****************************************************************************/
1050 /* */
1051 /* Function Name : impeg2d_api_set_params */
1052 /* */
1053 /* Description : */
1054 /* */
1055 /* Inputs : */
1056 /* Globals : <Does it use any global variables?> */
1057 /* Outputs : */
1058 /* Returns : void */
1059 /* */
1060 /* Issues : none */
1061 /* */
1062 /* Revision History: */
1063 /* */
1064 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1065 /* 08 06 2009 100356 RAVI */
1066 /* */
1067 /*****************************************************************************/
impeg2d_api_set_params(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1068 IV_API_CALL_STATUS_T impeg2d_api_set_params(iv_obj_t *ps_dechdl,void *pv_api_ip,void *pv_api_op)
1069 {
1070 dec_state_t *ps_dec_state;
1071 dec_state_multi_core_t *ps_dec_state_multi_core;
1072 impeg2d_ctl_set_config_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
1073 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
1074
1075 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1076 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1077
1078 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_HEADER) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_FRAME))
1079 {
1080 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1081 return(IV_FAIL);
1082 }
1083
1084 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DISPLAY_FRAME_OUT) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DECODE_FRAME_OUT))
1085 {
1086 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1087 return(IV_FAIL);
1088 }
1089
1090 if( (WORD32) ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_skip_mode < IVD_SKIP_NONE)
1091 {
1092 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1093 return(IV_FAIL);
1094 }
1095
1096 if(ps_dec_state->u2_header_done == 1)
1097 {
1098 if(((WORD32)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < 0) ||
1099 ((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < ps_dec_state->u2_frame_width)))
1100 {
1101 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1102 return(IV_FAIL);
1103 }
1104
1105 }
1106
1107
1108 ps_dec_state->u2_decode_header = (UWORD8)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode;
1109
1110 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0)
1111 {
1112 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd;
1113 }
1114 else
1115 {
1116
1117 if(ps_dec_state->u2_header_done == 1)
1118 {
1119 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
1120 }
1121 else
1122 {
1123 ps_dec_state->u4_frm_buf_stride = 0;
1124 }
1125 }
1126
1127
1128 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode == IVD_DECODE_FRAME)
1129 {
1130 ps_dec_state->u1_flushfrm = 0;
1131 }
1132
1133
1134 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
1135 return(IV_SUCCESS);
1136
1137 }
1138
1139 /*****************************************************************************/
1140 /* */
1141 /* Function Name : impeg2d_api_get_status */
1142 /* */
1143 /* Description : */
1144 /* */
1145 /* Inputs : */
1146 /* Globals : <Does it use any global variables?> */
1147 /* Outputs : */
1148 /* Returns : void */
1149 /* */
1150 /* Issues : none */
1151 /* */
1152 /* Revision History: */
1153 /* */
1154 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1155 /* 08 06 2009 100356 RAVI */
1156 /* */
1157 /*****************************************************************************/
impeg2d_api_get_status(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1158 IV_API_CALL_STATUS_T impeg2d_api_get_status(iv_obj_t *ps_dechdl,
1159 void *pv_api_ip,
1160 void *pv_api_op)
1161 {
1162 dec_state_t *ps_dec_state;
1163 dec_state_multi_core_t *ps_dec_state_multi_core;
1164 UWORD32 u4_i,u4_stride,u4_height;
1165 impeg2d_ctl_getstatus_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
1166 impeg2d_ctl_getstatus_op_t *ps_ctl_dec_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
1167 UNUSED(ps_ctl_dec_ip);
1168
1169 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1170 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1171
1172 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_size = sizeof(impeg2d_ctl_getstatus_op_t);
1173 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_num_disp_bufs = 1;
1174 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_ht = ps_dec_state->u2_frame_height;
1175 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_wd = ps_dec_state->u2_frame_width;
1176 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_frame_rate = ps_dec_state->u2_framePeriod;
1177
1178
1179 if(ps_dec_state->u2_progressive_sequence == 1)
1180 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_PROGRESSIVE ;
1181 else
1182 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_INTERLACED;
1183
1184
1185 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_output_chroma_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
1186 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs = 1;
1187 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = 1;
1188
1189
1190 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1191 {
1192 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1193 }
1194 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1195 {
1196 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1197 }
1198 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565)
1199 {
1200 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1201 }
1202 else
1203 {
1204 //Invalid chroma format; Error code may be updated, verify in testing if needed
1205 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
1206 return IV_FAIL;
1207 }
1208
1209 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1210 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1211
1212 for(u4_i = 0; u4_i < ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs; u4_i++)
1213 {
1214 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[u4_i] = MAX_BITSTREAM_BUFFER_SIZE;
1215 }
1216
1217 u4_stride = ps_dec_state->u4_frm_buf_stride;
1218 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4;
1219
1220 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1221 {
1222 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1223 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>2 ;
1224 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = (u4_stride * u4_height)>>2;
1225 }
1226 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV) || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
1227 {
1228 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1229 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>1 ;
1230 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1231 }
1232 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1233 {
1234 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height)*2;
1235 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1236 }
1237
1238 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IV_SUCCESS;
1239
1240 return(IV_SUCCESS);
1241
1242 }
1243
1244 /**
1245 *******************************************************************************
1246 *
1247 * @brief
1248 * Gets frame dimensions/offsets
1249 *
1250 * @par Description:
1251 * Gets frame buffer chararacteristics such a x & y offsets display and
1252 * buffer dimensions
1253 *
1254 * @param[in] ps_codec_obj
1255 * Pointer to codec object at API level
1256 *
1257 * @param[in] pv_api_ip
1258 * Pointer to input argument structure
1259 *
1260 * @param[out] pv_api_op
1261 * Pointer to output argument structure
1262 *
1263 * @returns Status
1264 *
1265 * @remarks
1266 *
1267 *
1268 *******************************************************************************
1269 */
impeg2d_get_frame_dimensions(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)1270 IV_API_CALL_STATUS_T impeg2d_get_frame_dimensions(iv_obj_t *ps_codec_obj,
1271 void *pv_api_ip,
1272 void *pv_api_op)
1273 {
1274 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
1275 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
1276 WORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
1277 dec_state_t *ps_codec;
1278 dec_state_multi_core_t *ps_dec_state_multi_core;
1279
1280 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
1281 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
1282
1283
1284 ps_ip = (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
1285 ps_op = (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
1286 UNUSED(ps_ip);
1287 if(ps_codec->u2_header_done)
1288 {
1289 disp_wd = ps_codec->u2_horizontal_size;
1290 disp_ht = ps_codec->u2_vertical_size;
1291
1292 if(0 == ps_codec->u4_share_disp_buf)
1293 {
1294 buffer_wd = disp_wd;
1295 buffer_ht = disp_ht;
1296 }
1297 else
1298 {
1299 buffer_wd = ps_codec->u2_frame_width;
1300 buffer_ht = ps_codec->u2_frame_height;
1301 }
1302 }
1303 else
1304 {
1305
1306 disp_wd = ps_codec->u2_create_max_width;
1307 disp_ht = ps_codec->u2_create_max_height;
1308
1309 if(0 == ps_codec->u4_share_disp_buf)
1310 {
1311 buffer_wd = disp_wd;
1312 buffer_ht = disp_ht;
1313 }
1314 else
1315 {
1316 buffer_wd = ALIGN16(disp_wd);
1317 buffer_ht = ALIGN16(disp_ht);
1318
1319 }
1320 }
1321 if(ps_codec->u2_frame_width > buffer_wd)
1322 buffer_wd = ps_codec->u2_frame_width;
1323
1324 x_offset = 0;
1325 y_offset = 0;
1326
1327
1328 ps_op->u4_disp_wd[0] = disp_wd;
1329 ps_op->u4_disp_ht[0] = disp_ht;
1330 ps_op->u4_buffer_wd[0] = buffer_wd;
1331 ps_op->u4_buffer_ht[0] = buffer_ht;
1332 ps_op->u4_x_offset[0] = x_offset;
1333 ps_op->u4_y_offset[0] = y_offset;
1334
1335 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
1336 >> 1);
1337 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
1338 >> 1);
1339 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
1340 >> 1);
1341 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
1342 >> 1);
1343 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = (ps_op->u4_x_offset[0]
1344 >> 1);
1345 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = (ps_op->u4_y_offset[0]
1346 >> 1);
1347
1348 if((ps_codec->i4_chromaFormat == IV_YUV_420SP_UV)
1349 || (ps_codec->i4_chromaFormat == IV_YUV_420SP_VU))
1350 {
1351 ps_op->u4_disp_wd[2] = 0;
1352 ps_op->u4_disp_ht[2] = 0;
1353 ps_op->u4_buffer_wd[2] = 0;
1354 ps_op->u4_buffer_ht[2] = 0;
1355 ps_op->u4_x_offset[2] = 0;
1356 ps_op->u4_y_offset[2] = 0;
1357
1358 ps_op->u4_disp_wd[1] <<= 1;
1359 ps_op->u4_buffer_wd[1] <<= 1;
1360 ps_op->u4_x_offset[1] <<= 1;
1361 }
1362
1363 return IV_SUCCESS;
1364
1365 }
1366
impeg2d_api_function(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1367 IV_API_CALL_STATUS_T impeg2d_api_function (iv_obj_t *ps_dechdl, void *pv_api_ip,void *pv_api_op)
1368 {
1369 WORD32 i4_cmd;
1370 IV_API_CALL_STATUS_T u4_error_code;
1371 UWORD32 *pu4_api_ip;
1372
1373 u4_error_code = impeg2d_api_check_struct_sanity(ps_dechdl,pv_api_ip,pv_api_op);
1374 if(IV_SUCCESS != u4_error_code)
1375 {
1376 return u4_error_code;
1377 }
1378
1379
1380 pu4_api_ip = (UWORD32 *)pv_api_ip;
1381 i4_cmd = *(pu4_api_ip + 1);
1382
1383 switch(i4_cmd)
1384 {
1385
1386 case IV_CMD_GET_NUM_MEM_REC:
1387 u4_error_code = impeg2d_api_num_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1388 break;
1389
1390 case IV_CMD_FILL_NUM_MEM_REC:
1391 u4_error_code = impeg2d_api_fill_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1392 break;
1393
1394 case IV_CMD_INIT:
1395 u4_error_code = impeg2d_api_init(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1396 break;
1397
1398 case IVD_CMD_SET_DISPLAY_FRAME:
1399 u4_error_code = impeg2d_api_set_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1400 break;
1401
1402 case IVD_CMD_REL_DISPLAY_FRAME:
1403 u4_error_code = impeg2d_api_rel_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1404 break;
1405
1406 case IVD_CMD_VIDEO_DECODE:
1407 u4_error_code = impeg2d_api_entity(ps_dechdl, (void *)pv_api_ip,(void *)pv_api_op);
1408 break;
1409
1410 case IV_CMD_RETRIEVE_MEMREC:
1411 u4_error_code = impeg2d_api_retrieve_mem_rec(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1412 break;
1413
1414 case IVD_CMD_VIDEO_CTL:
1415 u4_error_code = impeg2d_api_ctl(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1416 break;
1417
1418 default:
1419 break;
1420 }
1421
1422 return(u4_error_code);
1423
1424 }
1425
1426 /*****************************************************************************/
1427 /* */
1428 /* Function Name : impeg2d_api_num_mem_rec */
1429 /* */
1430 /* Description : The function get the number mem records library needs */
1431 /* Inputs : Error message */
1432 /* Globals : None */
1433 /* Processing : Just prints error message to console */
1434 /* Outputs : Error mesage to the console */
1435 /* Returns : None */
1436 /* */
1437 /* Issues : <List any issues or problems with this function> */
1438 /* */
1439 /* Revision History: */
1440 /* */
1441 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1442 /* 23 09 2010 Hamsalekha Creation */
1443 /* */
1444 /*****************************************************************************/
1445
1446
impeg2d_api_num_mem_rec(void * pv_api_ip,void * pv_api_op)1447 IV_API_CALL_STATUS_T impeg2d_api_num_mem_rec(void *pv_api_ip,void *pv_api_op)
1448 {
1449 /* To Query No of Memory Records */
1450 impeg2d_num_mem_rec_ip_t *ps_query_mem_rec_ip;
1451 impeg2d_num_mem_rec_op_t *ps_query_mem_rec_op;
1452
1453 ps_query_mem_rec_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
1454 ps_query_mem_rec_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
1455
1456 UNUSED(ps_query_mem_rec_ip);
1457 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_size = sizeof(impeg2d_num_mem_rec_op_t);
1458
1459 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_num_mem_rec = (UWORD32)NUM_MEM_RECORDS;
1460
1461 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_error_code = IV_SUCCESS;
1462
1463
1464 return(IV_SUCCESS);
1465
1466 }
1467
1468
1469 /*****************************************************************************/
1470 /* */
1471 /* Function Name : impeg2d_api_fill_mem_rec */
1472 /* */
1473 /* Description : Thsi functions fills details of each mem record lib needs*/
1474 /* Inputs : Error message */
1475 /* Globals : None */
1476 /* Processing : Just prints error message to console */
1477 /* Outputs : Error mesage to the console */
1478 /* Returns : None */
1479 /* */
1480 /* Issues : <List any issues or problems with this function> */
1481 /* */
1482 /* Revision History: */
1483 /* */
1484 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1485 /* 23 09 2010 Hamsalekha Creation */
1486 /* */
1487 /*****************************************************************************/
1488
1489
impeg2d_api_fill_mem_rec(void * pv_api_ip,void * pv_api_op)1490 IV_API_CALL_STATUS_T impeg2d_api_fill_mem_rec(void *pv_api_ip,void *pv_api_op)
1491 {
1492
1493 impeg2d_fill_mem_rec_ip_t *ps_mem_q_ip;
1494 impeg2d_fill_mem_rec_op_t *ps_mem_q_op;
1495
1496
1497 ps_mem_q_ip = pv_api_ip;
1498 ps_mem_q_op = pv_api_op;
1499
1500
1501 impeg2d_fill_mem_rec((impeg2d_fill_mem_rec_ip_t *)ps_mem_q_ip,
1502 (impeg2d_fill_mem_rec_op_t *)ps_mem_q_op);
1503
1504
1505 return(IV_SUCCESS);
1506
1507 }
1508
impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht,WORD32 u1_chroma_format,UWORD32 * p_buf_size)1509 UWORD32 impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht, WORD32 u1_chroma_format,UWORD32 *p_buf_size)
1510 {
1511 UWORD32 u4_min_num_out_bufs = 0;
1512 if(u1_chroma_format == IV_YUV_420P)
1513 u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1514 else if(u1_chroma_format == IV_YUV_422ILE)
1515 u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1516 else if(u1_chroma_format == IV_RGB_565)
1517 u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1518 else if((u1_chroma_format == IV_YUV_420SP_UV)
1519 || (u1_chroma_format == IV_YUV_420SP_VU))
1520 u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
1521
1522 if(u1_chroma_format == IV_YUV_420P)
1523 {
1524 p_buf_size[0] = (pic_wd * pic_ht);
1525 p_buf_size[1] = ((pic_wd + 1) >> 1) * ((pic_ht + 1) >> 1);
1526 p_buf_size[2] = ((pic_wd + 1) >> 1) * ((pic_ht + 1) >> 1);
1527 }
1528 else if(u1_chroma_format == IV_YUV_422ILE)
1529 {
1530 p_buf_size[0] = (pic_wd * pic_ht)
1531 * 2;
1532 p_buf_size[1] =
1533 p_buf_size[2] = 0;
1534 }
1535 else if(u1_chroma_format == IV_RGB_565)
1536 {
1537 p_buf_size[0] = (pic_wd * pic_ht)
1538 * 2;
1539 p_buf_size[1] =
1540 p_buf_size[2] = 0;
1541 }
1542 else if((u1_chroma_format == IV_YUV_420SP_UV)
1543 || (u1_chroma_format == IV_YUV_420SP_VU))
1544 {
1545 p_buf_size[0] = (pic_wd * pic_ht);
1546 p_buf_size[1] = ((pic_wd + 1) >> 1) * ((pic_ht + 1) >> 1) * 2;
1547 p_buf_size[2] = 0;
1548 }
1549 return u4_min_num_out_bufs;
1550 }
1551
check_app_out_buf_size(dec_state_t * ps_dec)1552 WORD32 check_app_out_buf_size(dec_state_t *ps_dec)
1553 {
1554 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
1555 UWORD32 u4_min_num_out_bufs, i;
1556 UWORD32 pic_wd, pic_ht;
1557
1558 pic_wd = ps_dec->u2_horizontal_size;
1559 pic_ht = ps_dec->u2_vertical_size;
1560
1561 if(ps_dec->u4_frm_buf_stride > pic_wd)
1562 pic_wd = ps_dec->u4_frm_buf_stride;
1563
1564 u4_min_num_out_bufs = impeg2d_get_outbuf_size(pic_wd, pic_ht, ps_dec->i4_chromaFormat, &au4_min_out_buf_size[0]);
1565
1566 if (0 == ps_dec->u4_share_disp_buf)
1567 {
1568 if(ps_dec->ps_out_buf->u4_num_bufs < u4_min_num_out_bufs)
1569 {
1570 return IV_FAIL;
1571 }
1572
1573 for (i = 0 ; i < u4_min_num_out_bufs; i++)
1574 {
1575 if(ps_dec->ps_out_buf->u4_min_out_buf_size[i] < au4_min_out_buf_size[i])
1576 return (IV_FAIL);
1577 }
1578 }
1579 else
1580 {
1581 if(ps_dec->as_disp_buffers[0].u4_num_bufs < u4_min_num_out_bufs)
1582 return IV_FAIL;
1583
1584 for (i = 0 ; i < u4_min_num_out_bufs; i++)
1585 {
1586 /* We need to check only with the disp_buffer[0], because we have
1587 * already ensured that all the buffers are of the same size in
1588 * impeg2d_api_set_display_frame.
1589 */
1590 if(ps_dec->as_disp_buffers[0].u4_min_out_buf_size[i] <
1591 au4_min_out_buf_size[i])
1592 return (IV_FAIL);
1593 }
1594 }
1595
1596 return(IV_SUCCESS);
1597 }
1598
1599
1600
1601 /*****************************************************************************/
1602 /* */
1603 /* Function Name : impeg2d_api_init */
1604 /* */
1605 /* Description : */
1606 /* Inputs : */
1607 /* Globals : */
1608 /* Processing : */
1609 /* Outputs : */
1610 /* Returns : */
1611 /* */
1612 /* Issues : */
1613 /* */
1614 /* Revision History: */
1615 /* */
1616 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1617 /* 17 09 2007 Rajendra C Y Draft */
1618 /* */
1619 /*****************************************************************************/
impeg2d_api_init(iv_obj_t * ps_dechdl,void * ps_ip,void * ps_op)1620 IV_API_CALL_STATUS_T impeg2d_api_init(iv_obj_t *ps_dechdl,
1621 void *ps_ip,
1622 void *ps_op)
1623 {
1624 UWORD32 i;
1625
1626 void *pv;
1627 UWORD32 u4_size;
1628
1629 dec_state_t *ps_dec_state;
1630 dec_state_multi_core_t *ps_dec_state_multi_core;
1631 UWORD32 u4_num_mem_rec;
1632 iv_mem_rec_t *ps_mem_rec ;
1633 iv_mem_rec_t *ps_frm_buf;
1634 iv_obj_t *ps_dec_handle;
1635 WORD32 i4_max_wd, i4_max_ht;
1636
1637 impeg2d_init_ip_t *ps_dec_init_ip;
1638 impeg2d_init_op_t *ps_dec_init_op;
1639 WORD32 i4_num_threads;
1640 UWORD32 u4_share_disp_buf, u4_chroma_format;
1641 UWORD32 u4_deinterlace;
1642
1643 ps_dec_init_ip = (impeg2d_init_ip_t *)ps_ip;
1644 ps_dec_init_op = (impeg2d_init_op_t *)ps_op;
1645
1646 i4_max_wd = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1647 i4_max_ht = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1648
1649 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_share_disp_buf))
1650 {
1651 #ifndef LOGO_EN
1652 u4_share_disp_buf = ps_dec_init_ip->u4_share_disp_buf;
1653 #else
1654 u4_share_disp_buf = 0;
1655 #endif
1656 }
1657 else
1658 {
1659 u4_share_disp_buf = 0;
1660 }
1661
1662 u4_chroma_format = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1663
1664 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_deinterlace))
1665 {
1666 u4_deinterlace = ps_dec_init_ip->u4_deinterlace;
1667 }
1668 else
1669 {
1670 u4_deinterlace = 0;
1671 }
1672
1673 if( (u4_chroma_format != IV_YUV_420P) &&
1674 (u4_chroma_format != IV_YUV_420SP_UV) &&
1675 (u4_chroma_format != IV_YUV_420SP_VU))
1676 {
1677 u4_share_disp_buf = 0;
1678 }
1679
1680 /* Disable deinterlacer in shared mode */
1681 if(u4_share_disp_buf)
1682 {
1683 u4_deinterlace = 0;
1684 }
1685
1686 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1687 ps_mem_rec ++;
1688
1689
1690 ps_dec_init_op->s_ivd_init_op_t.u4_size = sizeof(impeg2d_init_op_t);
1691
1692
1693 /* Except memTab[0], all other memTabs are initialized to zero */
1694 for(i = 1; i < ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
1695 {
1696 memset(ps_mem_rec->pv_base,0,ps_mem_rec->u4_mem_size);
1697 ps_mem_rec++;
1698 }
1699
1700 /* Reinitializing memTab[0] memory base address */
1701 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1702
1703
1704 /* memTab[0] is for codec Handle,redundant currently not being used */
1705 ps_dec_handle = ps_mem_rec->pv_base;
1706 u4_num_mem_rec = 1;
1707 ps_mem_rec++;
1708
1709
1710
1711
1712
1713 /* decoder handle */
1714 ps_dec_state_multi_core = ps_mem_rec->pv_base;
1715 u4_num_mem_rec++;
1716 ps_mem_rec++;
1717
1718
1719 {
1720 ps_dec_handle->pv_codec_handle = (void *)ps_dec_state_multi_core; /* Initializing codec context */
1721
1722 ps_dechdl->pv_codec_handle = (void *)ps_dec_state_multi_core;
1723 ps_dechdl->pv_fxns = (void *)impeg2d_api_function;
1724 }
1725
1726
1727 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1728 {
1729 #ifdef KEEP_THREADS_ACTIVE
1730 WORD32 ret;
1731 UWORD8 *pv_buf;
1732 WORD32 mutex_size = ithread_get_mutex_lock_size();
1733 WORD32 cond_size = ithread_get_cond_struct_size();
1734 #endif
1735 /*************************************************************************/
1736 /* For MPEG2 Decoder Context */
1737 /*************************************************************************/
1738 ps_dec_state = ps_mem_rec->pv_base;
1739
1740 ps_dec_state_multi_core->ps_dec_state[i4_num_threads] = ps_dec_state;
1741
1742 ps_dec_state->ps_dec_state_multi_core = ps_dec_state_multi_core;
1743
1744 ps_dec_state->i4_num_cores = 1;
1745 /* @ */ /* Used for storing MemRecords */
1746 u4_num_mem_rec++;
1747 ps_mem_rec++;
1748
1749 /* Thread handle */
1750 ps_dec_state->pv_codec_thread_handle = ps_mem_rec->pv_base;
1751 u4_num_mem_rec++;
1752 ps_mem_rec++;
1753
1754 #ifdef KEEP_THREADS_ACTIVE
1755 pv_buf = ps_mem_rec->pv_base;
1756 if (ps_mem_rec->u4_mem_size < 2 * mutex_size)
1757 {
1758 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_DEC_PER_MEM_INSUFFICIENT;
1759 return(IV_FAIL);
1760 }
1761
1762 ps_dec_state->pv_proc_start_mutex = (UWORD8 *)pv_buf;
1763 ps_dec_state->pv_proc_done_mutex = (UWORD8 *)pv_buf + mutex_size;
1764
1765 ret = ithread_mutex_init(ps_dec_state->pv_proc_start_mutex);
1766 RETURN_IF((ret != (IMPEG2D_ERROR_CODES_T)IV_SUCCESS), ret);
1767
1768 ret = ithread_mutex_init(ps_dec_state->pv_proc_done_mutex);
1769 RETURN_IF((ret != (IMPEG2D_ERROR_CODES_T)IV_SUCCESS), ret);
1770
1771 u4_num_mem_rec++;
1772 ps_mem_rec++;
1773
1774 pv_buf = ps_mem_rec->pv_base;
1775 if (ps_mem_rec->u4_mem_size < 2 * cond_size)
1776 {
1777 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_DEC_PER_MEM_INSUFFICIENT;
1778 return(IV_FAIL);
1779 }
1780 ps_dec_state->pv_proc_start_condition = (UWORD8 *)pv_buf;
1781 ps_dec_state->pv_proc_done_condition = (UWORD8 *)pv_buf + cond_size;
1782
1783 ret = ithread_cond_init(ps_dec_state->pv_proc_start_condition);
1784 RETURN_IF((ret != (IMPEG2D_ERROR_CODES_T)IV_SUCCESS), ret);
1785
1786 ret = ithread_cond_init(ps_dec_state->pv_proc_done_condition);
1787 RETURN_IF((ret != (IMPEG2D_ERROR_CODES_T)IV_SUCCESS), ret);
1788
1789 u4_num_mem_rec++;
1790 ps_mem_rec++;
1791 #endif
1792
1793 /*************************************************************************/
1794 /* For Motion Compensation Buffers */
1795 /*************************************************************************/
1796 pv = ps_mem_rec->pv_base;
1797
1798 /* for mc_fw_buf.pu1_y */
1799
1800 ps_dec_state->s_mc_fw_buf.pu1_y = pv;
1801 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1802
1803 u4_size = sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1804 /* for mc_fw_buf.pu1_u */
1805
1806 ps_dec_state->s_mc_fw_buf.pu1_u = pv;
1807 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1808
1809 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1810
1811 /* for mc_fw_buf.pu1_v */
1812
1813 ps_dec_state->s_mc_fw_buf.pu1_v = pv;
1814 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1815
1816 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1817
1818 /* for mc_bk_buf.pu1_y */
1819
1820 ps_dec_state->s_mc_bk_buf.pu1_y = pv;
1821 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1822
1823 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1824
1825 /* for mc_bk_buf.pu1_u */
1826
1827 ps_dec_state->s_mc_bk_buf.pu1_u = pv;
1828 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1829
1830 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1831
1832 /* for mc_bk_buf.pu1_v */
1833
1834 ps_dec_state->s_mc_bk_buf.pu1_v = pv;
1835 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1836
1837 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1838
1839 /* for mc_buf.pu1_y */
1840
1841 ps_dec_state->s_mc_buf.pu1_y = pv;
1842 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1843
1844 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1845
1846 /* for mc_buf.pu1_u */
1847
1848 ps_dec_state->s_mc_buf.pu1_u = pv;
1849 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1850
1851 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1852
1853 /* for mc_buf.pu1_v */
1854
1855 ps_dec_state->s_mc_buf.pu1_v = pv;
1856
1857 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1858
1859 u4_num_mem_rec++;
1860 ps_mem_rec++;
1861
1862
1863
1864 ps_dec_state->pv_pic_buf_mg = 0;
1865
1866 /*************************************************************************/
1867 /* For saving stack context to support global error handling */
1868 /*************************************************************************/
1869 ps_dec_state->pv_stack_cntxt = ps_mem_rec->pv_base;
1870 u4_num_mem_rec++;
1871 ps_mem_rec++;
1872
1873 }
1874
1875
1876
1877
1878
1879 /*************************************************************************/
1880 /* For Picture Buffer Manager */
1881 /*************************************************************************/
1882 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1883
1884 ps_dec_state->pv_pic_buf_mg = ps_mem_rec->pv_base;
1885 ps_dec_state->pv_pic_buf_base = (UWORD8 *)ps_mem_rec->pv_base + sizeof(buf_mgr_t);
1886
1887 u4_num_mem_rec++;
1888 ps_mem_rec++;
1889
1890
1891
1892 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1893 {
1894
1895 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1896
1897
1898 /* --------------------------------------------------------------------- */
1899 /* Initializations */
1900
1901 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1902
1903
1904 {
1905 UWORD32 u4_max_frm_width,u4_max_frm_height;
1906
1907 u4_max_frm_width = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1908 u4_max_frm_height = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1909
1910 ps_dec_state->u2_create_max_width = u4_max_frm_width;
1911 ps_dec_state->u2_create_max_height = u4_max_frm_height;
1912
1913 ps_dec_state->i4_chromaFormat = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1914 ps_dec_state->u4_frm_buf_stride = 0 ;
1915 ps_dec_state->u2_frame_width = u4_max_frm_width;
1916 ps_dec_state->u2_picture_width = u4_max_frm_width;
1917 ps_dec_state->u2_horizontal_size = u4_max_frm_width;
1918
1919 ps_dec_state->u2_frame_height = u4_max_frm_height;
1920 ps_dec_state->u2_vertical_size = u4_max_frm_height;
1921 ps_dec_state->u4_share_disp_buf = u4_share_disp_buf;
1922 ps_dec_state->u4_deinterlace = u4_deinterlace;
1923 ps_dec_state->ps_deint_pic = NULL;
1924 }
1925 }
1926
1927 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1928
1929 if((ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1930 &&((ps_dec_state->u2_vertical_size & 0x1) != 0))
1931 {
1932 //printf("Error! Height should be multiple of 2 if Chroma format is 422ILE\n");
1933 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_CHROMA_FORMAT_HEIGHT_ERROR;
1934 return(IV_FAIL);
1935
1936
1937 }
1938
1939 /* --------------------------------------------------------------------- */
1940
1941
1942 /* ! */
1943 // picture buffer manager initialization will be done only for first thread
1944 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr);
1945 impeg2_buf_mgr_init((buf_mgr_t *)ps_dec_state->pv_pic_buf_mg);
1946
1947 /*************************************************************************/
1948 /* Internal Frame Buffers */
1949 /*************************************************************************/
1950
1951
1952 /* Set first frame to grey */
1953 {
1954 ps_frm_buf = ps_mem_rec;
1955 memset(ps_frm_buf->pv_base, 128, ps_frm_buf->u4_mem_size);
1956 ps_frm_buf++;
1957 }
1958
1959 if(0 == ps_dec_state->u4_share_disp_buf)
1960 {
1961 pic_buf_t *ps_pic_buf;
1962 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
1963 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1964 {
1965 UWORD8 *pu1_buf;
1966 pu1_buf = ps_mem_rec->pv_base;
1967
1968 ps_pic_buf->pu1_y = pu1_buf;
1969 pu1_buf += i4_max_ht * i4_max_wd;
1970
1971 ps_pic_buf->pu1_u = pu1_buf;
1972 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1973
1974 ps_pic_buf->pu1_v = pu1_buf;
1975 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1976
1977 ps_pic_buf->i4_buf_id = i;
1978
1979 ps_pic_buf->u1_used_as_ref = 0;
1980
1981 ps_pic_buf->u4_ts = 0;
1982
1983 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
1984 ps_mem_rec++;
1985 ps_pic_buf++;
1986 }
1987 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1988 }
1989 else if (ps_dec_state->i4_chromaFormat != IV_YUV_420P)
1990 {
1991 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1992 {
1993 ps_dec_state->pu1_chroma_ref_buf[i] = ps_mem_rec->pv_base;
1994 ps_mem_rec++;
1995 }
1996
1997 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1998 }
1999 else
2000 {
2001 ps_mem_rec+=NUM_INT_FRAME_BUFFERS;
2002 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
2003 }
2004
2005
2006 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
2007
2008 ps_dec_state->pu1_input_buffer = ps_mem_rec->pv_base;
2009 u4_num_mem_rec++;
2010 ps_mem_rec++;
2011
2012 ps_dec_state->pv_jobq_buf = ps_mem_rec->pv_base;
2013 ps_dec_state->i4_jobq_buf_size = ps_mem_rec->u4_mem_size;
2014 u4_num_mem_rec++;
2015 ps_mem_rec++;
2016
2017 ps_dec_state->u1_flushfrm = 0;
2018 ps_dec_state->u1_flushcnt = 0;
2019 ps_dec_state->pv_jobq = impeg2_jobq_init(ps_dec_state->pv_jobq_buf, ps_dec_state->i4_jobq_buf_size);
2020
2021
2022 ps_dec_state->pv_deinterlacer_ctxt = ps_mem_rec->pv_base;
2023 u4_num_mem_rec++;
2024 ps_mem_rec++;
2025
2026 ps_dec_state->pu1_deint_fmt_buf = ps_mem_rec->pv_base;
2027 u4_num_mem_rec++;
2028 ps_mem_rec++;
2029
2030
2031 /*************************************************************************/
2032 /* Last MemTab is used for storing TabRecords */
2033 /*************************************************************************/
2034 ps_dec_state->pv_memTab = (void *)ps_mem_rec->pv_base;
2035 memcpy(ps_mem_rec->pv_base,ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location, ps_mem_rec->u4_mem_size);
2036 /* Updating in Decoder Context with memRecords */
2037 u4_num_mem_rec++;
2038 ps_mem_rec++;
2039 ps_dec_state->u4_num_mem_records = u4_num_mem_rec;
2040
2041 if(u4_num_mem_rec != ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec)
2042 {
2043 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_NUM_MEM_REC_NOT_SUFFICIENT;
2044 return(IV_FAIL);
2045 }
2046
2047 ps_dec_state->u4_num_frames_decoded = 0;
2048 ps_dec_state->aps_ref_pics[0] = NULL;
2049 ps_dec_state->aps_ref_pics[1] = NULL;
2050
2051 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IV_SUCCESS;
2052
2053 impeg2d_init_arch(ps_dec_state);
2054
2055 impeg2d_init_function_ptr(ps_dec_state);
2056
2057 return(IV_SUCCESS);
2058 }
2059
2060 /*****************************************************************************/
2061 /* */
2062 /* Function Name : impeg2d_api_retrieve_mem_rec */
2063 /* */
2064 /* Description : */
2065 /* */
2066 /* Inputs : */
2067 /* Globals : <Does it use any global variables?> */
2068 /* Outputs : */
2069 /* Returns : void */
2070 /* */
2071 /* Issues : none */
2072 /* */
2073 /* Revision History: */
2074 /* */
2075 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2076 /* 22 10 2008 100356 Draft */
2077 /* */
2078 /*****************************************************************************/
impeg2d_api_retrieve_mem_rec(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)2079 IV_API_CALL_STATUS_T impeg2d_api_retrieve_mem_rec(iv_obj_t *ps_dechdl,
2080 void *pv_api_ip,
2081 void *pv_api_op)
2082 {
2083 UWORD32 u4_i;
2084 dec_state_t *ps_dec_state;
2085 dec_state_multi_core_t *ps_dec_state_multi_core;
2086 iv_mem_rec_t *ps_mem_rec;
2087 iv_mem_rec_t *ps_temp_rec;
2088 #ifdef KEEP_THREADS_ACTIVE
2089 IMPEG2D_ERROR_CODES_T ret;
2090 dec_state_t *ps_dec_thd;
2091 #endif
2092
2093
2094
2095 impeg2d_retrieve_mem_rec_ip_t *ps_retr_mem_rec_ip;
2096 impeg2d_retrieve_mem_rec_op_t *ps_retr_mem_rec_op;
2097
2098 ps_retr_mem_rec_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
2099 ps_retr_mem_rec_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
2100
2101 ps_mem_rec = ps_retr_mem_rec_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
2102 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
2103 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
2104 ps_temp_rec = ps_dec_state->pv_memTab;
2105
2106 for(u4_i = 0; u4_i < (ps_dec_state->u4_num_mem_records);u4_i++)
2107 {
2108 ps_mem_rec[u4_i].u4_mem_size = ps_temp_rec[u4_i].u4_mem_size;
2109 ps_mem_rec[u4_i].u4_mem_alignment = ps_temp_rec[u4_i].u4_mem_alignment;
2110 ps_mem_rec[u4_i].e_mem_type = ps_temp_rec[u4_i].e_mem_type;
2111 ps_mem_rec[u4_i].pv_base = ps_temp_rec[u4_i].pv_base;
2112 }
2113
2114 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = IV_SUCCESS;
2115 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_num_mem_rec_filled = ps_dec_state->u4_num_mem_records;
2116
2117 #ifdef KEEP_THREADS_ACTIVE
2118 for(u4_i = 0; u4_i < MAX_THREADS; u4_i++)
2119 {
2120 ps_dec_thd = ps_dec_state_multi_core->ps_dec_state[u4_i];
2121 if(ps_dec_state_multi_core->au4_thread_launched[u4_i])
2122 {
2123 ret = ithread_mutex_lock(ps_dec_thd->pv_proc_start_mutex);
2124 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret) return(IV_FAIL);
2125
2126 // set process start for the threads waiting on the start condition
2127 // in the decode routine so as to break them
2128 ps_dec_thd->ai4_process_start = 1;
2129 ps_dec_state_multi_core->i4_break_threads = 1;
2130
2131 ret = ithread_cond_signal(ps_dec_thd->pv_proc_start_condition);
2132 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret) return(IV_FAIL);
2133
2134 ret = ithread_mutex_unlock(ps_dec_thd->pv_proc_start_mutex);
2135 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret) return(IV_FAIL);
2136
2137 ithread_join(ps_dec_thd->pv_codec_thread_handle, NULL);
2138 ps_dec_state_multi_core->au4_thread_launched[u4_i] = 0;
2139 }
2140
2141 ret = ithread_cond_destroy(ps_dec_thd->pv_proc_start_condition);
2142 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret)
2143 return(IV_FAIL);
2144
2145 ret = ithread_cond_destroy(ps_dec_thd->pv_proc_done_condition);
2146 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret)
2147 return(IV_FAIL);
2148
2149 ret = ithread_mutex_destroy(ps_dec_thd->pv_proc_start_mutex);
2150 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret)
2151 return(IV_FAIL);
2152
2153 ret = ithread_mutex_destroy(ps_dec_thd->pv_proc_done_mutex);
2154 if((IMPEG2D_ERROR_CODES_T)IV_SUCCESS != ret)
2155 return(IV_FAIL);
2156 }
2157 #endif
2158
2159 impeg2_jobq_deinit(ps_dec_state->pv_jobq);
2160 IMPEG2D_PRINT_STATISTICS();
2161
2162
2163 return(IV_SUCCESS);
2164
2165 }
2166
2167 /*****************************************************************************/
2168 /* */
2169 /* Function Name : impeg2d_api_ctl */
2170 /* */
2171 /* Description : */
2172 /* */
2173 /* Inputs : */
2174 /* Globals : <Does it use any global variables?> */
2175 /* Outputs : */
2176 /* Returns : void */
2177 /* */
2178 /* Issues : none */
2179 /* */
2180 /* Revision History: */
2181 /* */
2182 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2183 /* 22 10 2008 100356 Draft */
2184 /* */
2185 /*****************************************************************************/
impeg2d_api_ctl(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)2186 IV_API_CALL_STATUS_T impeg2d_api_ctl(iv_obj_t *ps_dechdl,
2187 void *pv_api_ip,
2188 void *pv_api_op)
2189 {
2190 WORD32 i4_sub_cmd;
2191 UWORD32 *pu4_api_ip;
2192 IV_API_CALL_STATUS_T u4_error_code;
2193
2194 pu4_api_ip = (UWORD32 *)pv_api_ip;
2195 i4_sub_cmd = *(pu4_api_ip + 2);
2196
2197 switch(i4_sub_cmd)
2198 {
2199 case IVD_CMD_CTL_GETPARAMS:
2200 u4_error_code = impeg2d_api_get_status(ps_dechdl, (void *)pv_api_ip,
2201 (void *)pv_api_op);
2202 break;
2203
2204 case IVD_CMD_CTL_SETPARAMS:
2205 u4_error_code = impeg2d_api_set_params(ps_dechdl, (void *)pv_api_ip,
2206 (void *)pv_api_op);
2207 break;
2208
2209 case IVD_CMD_CTL_RESET:
2210 u4_error_code = impeg2d_api_reset(ps_dechdl, (void *)pv_api_ip,
2211 (void *)pv_api_op);
2212 break;
2213
2214 case IVD_CMD_CTL_SETDEFAULT:
2215 u4_error_code = impeg2d_api_set_default(ps_dechdl,
2216 (void *)pv_api_ip,
2217 (void *)pv_api_op);
2218 break;
2219
2220 case IVD_CMD_CTL_FLUSH:
2221 u4_error_code = impeg2d_api_set_flush_mode(ps_dechdl,
2222 (void *)pv_api_ip,
2223 (void *)pv_api_op);
2224 break;
2225
2226 case IVD_CMD_CTL_GETBUFINFO:
2227 u4_error_code = impeg2d_api_get_buf_info(ps_dechdl,
2228 (void *)pv_api_ip,
2229 (void *)pv_api_op);
2230 break;
2231
2232 case IVD_CMD_CTL_GETVERSION:
2233 u4_error_code = impeg2d_api_get_version(ps_dechdl, (void *)pv_api_ip,
2234 (void *)pv_api_op);
2235 break;
2236
2237 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
2238 u4_error_code = impeg2d_api_set_num_cores(ps_dechdl,
2239 (void *)pv_api_ip,
2240 (void *)pv_api_op);
2241 break;
2242
2243 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
2244 u4_error_code = impeg2d_get_frame_dimensions(ps_dechdl,
2245 (void *)pv_api_ip,
2246 (void *)pv_api_op);
2247 break;
2248
2249 case IMPEG2D_CMD_CTL_GET_SEQ_INFO:
2250 u4_error_code = impeg2d_api_get_seq_info(ps_dechdl,
2251 (void *)pv_api_ip,
2252 (void *)pv_api_op);
2253 break;
2254
2255 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
2256 u4_error_code = impeg2d_set_processor(ps_dechdl, (void *)pv_api_ip,
2257 (void *)pv_api_op);
2258 break;
2259
2260 default:
2261 u4_error_code = IV_FAIL;
2262 break;
2263 }
2264
2265 return (u4_error_code);
2266
2267 }
2268
2269 /*****************************************************************************/
2270 /* */
2271 /* Function Name : impeg2d_api_check_struct_sanity */
2272 /* */
2273 /* Description : */
2274 /* */
2275 /* Inputs : */
2276 /* Globals : <Does it use any global variables?> */
2277 /* Outputs : */
2278 /* Returns : void */
2279 /* */
2280 /* Issues : none */
2281 /* */
2282 /* Revision History: */
2283 /* */
2284 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2285 /* 22 10 2008 100356 Draft */
2286 /* */
2287 /*****************************************************************************/
impeg2d_api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)2288 IV_API_CALL_STATUS_T impeg2d_api_check_struct_sanity(iv_obj_t *ps_handle,
2289 void *pv_api_ip,
2290 void *pv_api_op)
2291 {
2292 WORD32 i4_cmd;
2293 UWORD32 *pu4_api_ip;
2294 UWORD32 *pu4_api_op;
2295 WORD32 i,j;
2296
2297 if(NULL == pv_api_op)
2298 return(IV_FAIL);
2299
2300 if(NULL == pv_api_ip)
2301 return(IV_FAIL);
2302
2303 pu4_api_ip = (UWORD32 *)pv_api_ip;
2304 pu4_api_op = (UWORD32 *)pv_api_op;
2305 i4_cmd = (IVD_API_COMMAND_TYPE_T)*(pu4_api_ip + 1);
2306
2307 /* error checks on handle */
2308 switch(i4_cmd)
2309 {
2310 case IV_CMD_GET_NUM_MEM_REC:
2311 case IV_CMD_FILL_NUM_MEM_REC:
2312 break;
2313 case IV_CMD_INIT:
2314 if(ps_handle == NULL)
2315 {
2316 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2317 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2318 return IV_FAIL;
2319 }
2320
2321 if(ps_handle->u4_size != sizeof(iv_obj_t))
2322 {
2323 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2324 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2325 return IV_FAIL;
2326 }
2327 break;
2328 case IVD_CMD_GET_DISPLAY_FRAME:
2329 case IVD_CMD_VIDEO_DECODE:
2330 case IV_CMD_RETRIEVE_MEMREC:
2331 case IVD_CMD_SET_DISPLAY_FRAME:
2332 case IVD_CMD_REL_DISPLAY_FRAME:
2333 case IVD_CMD_VIDEO_CTL:
2334 {
2335 if(ps_handle == NULL)
2336 {
2337 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2338 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2339 return IV_FAIL;
2340 }
2341
2342 if(ps_handle->u4_size != sizeof(iv_obj_t))
2343 {
2344 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2345 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2346 return IV_FAIL;
2347 }
2348 if(ps_handle->pv_fxns != impeg2d_api_function)
2349 {
2350 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2351 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2352 return IV_FAIL;
2353 }
2354
2355 if(ps_handle->pv_codec_handle == NULL)
2356 {
2357 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2358 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2359 return IV_FAIL;
2360 }
2361 }
2362 break;
2363 default:
2364 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2365 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
2366 return IV_FAIL;
2367 }
2368
2369 switch(i4_cmd)
2370 {
2371 case IV_CMD_GET_NUM_MEM_REC:
2372 {
2373 impeg2d_num_mem_rec_ip_t *ps_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
2374 impeg2d_num_mem_rec_op_t *ps_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
2375 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0;
2376
2377 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size != sizeof(impeg2d_num_mem_rec_ip_t))
2378 {
2379 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2380 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2381 return(IV_FAIL);
2382 }
2383
2384 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size != sizeof(impeg2d_num_mem_rec_op_t))
2385 {
2386 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2387 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2388 return(IV_FAIL);
2389 }
2390 }
2391 break;
2392 case IV_CMD_FILL_NUM_MEM_REC:
2393 {
2394 impeg2d_fill_mem_rec_ip_t *ps_ip = (impeg2d_fill_mem_rec_ip_t *)pv_api_ip;
2395 impeg2d_fill_mem_rec_op_t *ps_op = (impeg2d_fill_mem_rec_op_t *)pv_api_op;
2396 iv_mem_rec_t *ps_mem_rec;
2397
2398 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
2399
2400 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size != sizeof(impeg2d_fill_mem_rec_ip_t))
2401 {
2402 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2403 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2404 return(IV_FAIL);
2405 }
2406
2407 if(ps_op->s_ivd_fill_mem_rec_op_t.u4_size != sizeof(impeg2d_fill_mem_rec_op_t))
2408 {
2409 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2410 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2411 return(IV_FAIL);
2412 }
2413
2414 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd < MIN_WIDTH)
2415 {
2416 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2417 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2418 return(IV_FAIL);
2419 }
2420
2421 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd > MAX_WIDTH)
2422 {
2423 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2424 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2425 return(IV_FAIL);
2426 }
2427
2428 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht < MIN_HEIGHT)
2429 {
2430 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2431 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2432 return(IV_FAIL);
2433 }
2434
2435 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht > MAX_HEIGHT)
2436 {
2437 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2438 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2439 return(IV_FAIL);
2440 }
2441
2442 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location)
2443 {
2444 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2445 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2446 return(IV_FAIL);
2447 }
2448
2449 /* check memrecords sizes are correct */
2450 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
2451 for(i=0;i<NUM_MEM_RECORDS;i++)
2452 {
2453 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2454 {
2455 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2456 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2457 return IV_FAIL;
2458 }
2459 }
2460 }
2461 break;
2462
2463 case IV_CMD_INIT:
2464 {
2465 impeg2d_init_ip_t *ps_ip = (impeg2d_init_ip_t *)pv_api_ip;
2466 impeg2d_init_op_t *ps_op = (impeg2d_init_op_t *)pv_api_op;
2467 iv_mem_rec_t *ps_mem_rec;
2468 UWORD32 u4_tot_num_mem_recs;
2469
2470 ps_op->s_ivd_init_op_t.u4_error_code = 0;
2471
2472 if(ps_ip->s_ivd_init_ip_t.u4_size != sizeof(impeg2d_init_ip_t))
2473 {
2474 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2475 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2476 return(IV_FAIL);
2477 }
2478
2479 if(ps_op->s_ivd_init_op_t.u4_size != sizeof(impeg2d_init_op_t))
2480 {
2481 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2482 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2483 return(IV_FAIL);
2484 }
2485
2486 u4_tot_num_mem_recs = NUM_MEM_RECORDS;
2487
2488
2489
2490
2491 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec > u4_tot_num_mem_recs)
2492 {
2493 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2494 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_NOT_SUFFICIENT;
2495 return(IV_FAIL);
2496 }
2497
2498 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd < MIN_WIDTH)
2499 {
2500 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2501 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2502 return(IV_FAIL);
2503 }
2504
2505 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd > MAX_WIDTH)
2506 {
2507 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2508 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2509 return(IV_FAIL);
2510 }
2511
2512 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht < MIN_HEIGHT)
2513 {
2514 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2515 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2516 return(IV_FAIL);
2517 }
2518
2519 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht > MAX_HEIGHT)
2520 {
2521 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2522 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2523 return(IV_FAIL);
2524 }
2525
2526 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location)
2527 {
2528 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2529 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2530 return(IV_FAIL);
2531 }
2532
2533 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) &&
2534 (ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_422ILE)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_UV)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_VU))
2535 {
2536 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2537 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
2538 return(IV_FAIL);
2539 }
2540
2541 /* verify number of mem records */
2542 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < NUM_MEM_RECORDS)
2543 {
2544 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2545 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT;
2546 return IV_FAIL;
2547 }
2548
2549 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location;
2550 /* verify wether first memrecord is handle or not */
2551 /*
2552 if(ps_mem_rec->pv_base != ps_handle)
2553 {
2554 // indicate the incorrect handle error
2555 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2556 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INVALID_HANDLE;
2557 return IV_FAIL;
2558 }
2559 */
2560 /* check memrecords sizes are correct */
2561 for(i=0;i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec ; i++)
2562 {
2563 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2564 {
2565 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2566 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2567 return IV_FAIL;
2568 }
2569 }
2570
2571 /* verify memtabs for overlapping regions */
2572 {
2573 UWORD8 *pau1_start[NUM_MEM_RECORDS];
2574 UWORD8 *pau1_end[NUM_MEM_RECORDS];
2575
2576
2577 pau1_start[0] = (UWORD8 *)(ps_mem_rec[0].pv_base);
2578 pau1_end[0] = (UWORD8 *)(ps_mem_rec[0].pv_base) + ps_mem_rec[0].u4_mem_size - 1;
2579 for(i = 1; i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
2580 {
2581 /* This array is populated to check memtab overlapp */
2582 pau1_start[i] = (UWORD8 *)(ps_mem_rec[i].pv_base);
2583 pau1_end[i] = (UWORD8 *)(ps_mem_rec[i].pv_base) + ps_mem_rec[i].u4_mem_size - 1;
2584
2585 for(j = 0; j < i; j++)
2586 {
2587 if((pau1_start[i] >= pau1_start[j]) && (pau1_start[i] <= pau1_end[j]))
2588 {
2589 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2590 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2591 return IV_FAIL;
2592 }
2593
2594 if((pau1_end[i] >= pau1_start[j]) && (pau1_end[i] <= pau1_end[j]))
2595 {
2596 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2597 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2598 return IV_FAIL;
2599 }
2600
2601 if((pau1_start[i] < pau1_start[j]) && (pau1_end[i] > pau1_end[j]))
2602 {
2603 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2604 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2605 return IV_FAIL;
2606 }
2607 }
2608 }
2609 }
2610
2611
2612
2613
2614 {
2615 iv_mem_rec_t as_mem_rec_ittiam_api[NUM_MEM_RECORDS];
2616
2617 impeg2d_fill_mem_rec_ip_t s_fill_mem_rec_ip;
2618 impeg2d_fill_mem_rec_op_t s_fill_mem_rec_op;
2619 IV_API_CALL_STATUS_T e_status;
2620 WORD32 i4_num_memrec;
2621 {
2622
2623 iv_num_mem_rec_ip_t s_no_of_mem_rec_query_ip;
2624 iv_num_mem_rec_op_t s_no_of_mem_rec_query_op;
2625
2626
2627 s_no_of_mem_rec_query_ip.u4_size = sizeof(iv_num_mem_rec_ip_t);
2628 s_no_of_mem_rec_query_op.u4_size = sizeof(iv_num_mem_rec_op_t);
2629
2630 s_no_of_mem_rec_query_ip.e_cmd = IV_CMD_GET_NUM_MEM_REC;
2631 impeg2d_api_function(NULL,
2632 (void *)&s_no_of_mem_rec_query_ip,
2633 (void *)&s_no_of_mem_rec_query_op);
2634
2635 i4_num_memrec = s_no_of_mem_rec_query_op.u4_num_mem_rec;
2636
2637
2638
2639 }
2640
2641
2642 /* initialize mem records array with sizes */
2643 for(i = 0; i < i4_num_memrec; i++)
2644 {
2645 as_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
2646 }
2647
2648 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size = sizeof(impeg2d_fill_mem_rec_ip_t);
2649 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
2650 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd;
2651 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht;
2652 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = as_mem_rec_ittiam_api;
2653 s_fill_mem_rec_ip.u4_share_disp_buf = ps_ip->u4_share_disp_buf;
2654 s_fill_mem_rec_ip.e_output_format = ps_ip->s_ivd_init_ip_t.e_output_format;
2655 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size = sizeof(impeg2d_fill_mem_rec_op_t);
2656
2657
2658 e_status = impeg2d_api_function(NULL,
2659 (void *)&s_fill_mem_rec_ip,
2660 (void *)&s_fill_mem_rec_op);
2661 if(IV_FAIL == e_status)
2662 {
2663 ps_op->s_ivd_init_op_t.u4_error_code = s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code;
2664 return(IV_FAIL);
2665 }
2666
2667
2668
2669 for(i = 0; i < i4_num_memrec; i ++)
2670 {
2671 if(ps_mem_rec[i].pv_base == NULL)
2672 {
2673 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2674 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_BASE_NULL;
2675 return IV_FAIL;
2676 }
2677 #ifdef CHECK_ALIGN
2678
2679 if((UWORD32)(ps_mem_rec[i].pv_base) & (ps_mem_rec[i].u4_mem_alignment - 1))
2680 {
2681 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2682 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2683 return IV_FAIL;
2684 }
2685 #endif //CHECK_ALIGN
2686 if(ps_mem_rec[i].u4_mem_alignment != as_mem_rec_ittiam_api[i].u4_mem_alignment)
2687 {
2688 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2689 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2690 return IV_FAIL;
2691 }
2692
2693 if(ps_mem_rec[i].u4_mem_size < as_mem_rec_ittiam_api[i].u4_mem_size)
2694 {
2695 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2696 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE;
2697 return IV_FAIL;
2698 }
2699
2700 if(ps_mem_rec[i].e_mem_type != as_mem_rec_ittiam_api[i].e_mem_type)
2701 {
2702 if (IV_EXTERNAL_CACHEABLE_SCRATCH_MEM == as_mem_rec_ittiam_api[i].e_mem_type)
2703 {
2704 if (IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM == ps_mem_rec[i].e_mem_type)
2705 {
2706 continue;
2707 }
2708 }
2709 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2710 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE;
2711 return IV_FAIL;
2712 }
2713 }
2714 }
2715
2716
2717 }
2718 break;
2719
2720 case IVD_CMD_GET_DISPLAY_FRAME:
2721 {
2722 impeg2d_get_display_frame_ip_t *ps_ip = (impeg2d_get_display_frame_ip_t *)pv_api_ip;
2723 impeg2d_get_display_frame_op_t *ps_op = (impeg2d_get_display_frame_op_t *)pv_api_op;
2724
2725 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
2726
2727 if(ps_ip->s_ivd_get_display_frame_ip_t.u4_size != sizeof(impeg2d_get_display_frame_ip_t))
2728 {
2729 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2730 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2731 return(IV_FAIL);
2732 }
2733
2734 if(ps_op->s_ivd_get_display_frame_op_t.u4_size != sizeof(impeg2d_get_display_frame_op_t))
2735 {
2736 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2737 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2738 return(IV_FAIL);
2739 }
2740
2741 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs == 0)
2742 {
2743 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2744 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2745 return IV_FAIL;
2746 }
2747
2748 for(i = 0; i< (WORD32)ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs;i++)
2749 {
2750 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.pu1_bufs[i] == NULL)
2751 {
2752 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2753 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2754 return IV_FAIL;
2755 }
2756
2757 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2758 {
2759 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2760 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2761 return IV_FAIL;
2762 }
2763 /*
2764 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2765 {
2766 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2767 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2768 return IV_FAIL;
2769 }
2770 */
2771 }
2772 }
2773 break;
2774 case IVD_CMD_REL_DISPLAY_FRAME:
2775 {
2776 impeg2d_rel_display_frame_ip_t *ps_ip = (impeg2d_rel_display_frame_ip_t *)pv_api_ip;
2777 impeg2d_rel_display_frame_op_t *ps_op = (impeg2d_rel_display_frame_op_t *)pv_api_op;
2778
2779 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
2780
2781 if ((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(impeg2d_rel_display_frame_ip_t))
2782 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(ivd_rel_display_frame_ip_t)))
2783 {
2784 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2785 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2786 return(IV_FAIL);
2787 }
2788
2789 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(impeg2d_rel_display_frame_op_t)) &&
2790 (ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(ivd_rel_display_frame_op_t)))
2791 {
2792 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2793 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2794 return(IV_FAIL);
2795 }
2796
2797 }
2798 break;
2799
2800
2801 case IVD_CMD_SET_DISPLAY_FRAME:
2802 {
2803 impeg2d_set_display_frame_ip_t *ps_ip = (impeg2d_set_display_frame_ip_t *)pv_api_ip;
2804 impeg2d_set_display_frame_op_t *ps_op = (impeg2d_set_display_frame_op_t *)pv_api_op;
2805 UWORD32 j, i;
2806
2807 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
2808
2809 if ((ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(impeg2d_set_display_frame_ip_t))
2810 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(ivd_set_display_frame_ip_t)))
2811 {
2812 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2813 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2814 return(IV_FAIL);
2815 }
2816
2817 if((ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(impeg2d_set_display_frame_op_t)) &&
2818 (ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(ivd_set_display_frame_op_t)))
2819 {
2820 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2821 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2822 return(IV_FAIL);
2823 }
2824
2825 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
2826 {
2827 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2828 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2829 return IV_FAIL;
2830 }
2831
2832 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; j++)
2833 {
2834 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs == 0)
2835 {
2836 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2837 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2838 return IV_FAIL;
2839 }
2840
2841 for(i=0;i< ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;i++)
2842 {
2843 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] == NULL)
2844 {
2845 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2846 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2847 return IV_FAIL;
2848 }
2849
2850 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] == 0)
2851 {
2852 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2853 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2854 return IV_FAIL;
2855 }
2856 }
2857 }
2858 }
2859 break;
2860
2861 case IVD_CMD_VIDEO_DECODE:
2862 {
2863 impeg2d_video_decode_ip_t *ps_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
2864 impeg2d_video_decode_op_t *ps_op = (impeg2d_video_decode_op_t *)pv_api_op;
2865
2866 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
2867
2868 if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(impeg2d_video_decode_ip_t))
2869 {
2870 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2871 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2872 return(IV_FAIL);
2873 }
2874
2875 if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(impeg2d_video_decode_op_t))
2876 {
2877 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2878 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2879 return(IV_FAIL);
2880 }
2881
2882 }
2883 break;
2884
2885 case IV_CMD_RETRIEVE_MEMREC:
2886 {
2887 impeg2d_retrieve_mem_rec_ip_t *ps_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
2888 impeg2d_retrieve_mem_rec_op_t *ps_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
2889 iv_mem_rec_t *ps_mem_rec;
2890
2891 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0;
2892
2893 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_ip_t))
2894 {
2895 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2896 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2897 return(IV_FAIL);
2898 }
2899
2900 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_op_t))
2901 {
2902 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2903 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2904 return(IV_FAIL);
2905 }
2906
2907 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
2908 /* check memrecords sizes are correct */
2909 for(i=0;i < NUM_MEM_RECORDS ; i++)
2910 {
2911 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2912 {
2913 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2914 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2915 return IV_FAIL;
2916 }
2917 }
2918 }
2919 break;
2920
2921 case IVD_CMD_VIDEO_CTL:
2922 {
2923 UWORD32 *pu4_ptr_cmd;
2924 UWORD32 u4_sub_command;
2925
2926 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
2927 pu4_ptr_cmd += 2;
2928 u4_sub_command = *pu4_ptr_cmd;
2929
2930 switch(u4_sub_command)
2931 {
2932 case IVD_CMD_CTL_SETPARAMS:
2933 {
2934 impeg2d_ctl_set_config_ip_t *ps_ip;
2935 impeg2d_ctl_set_config_op_t *ps_op;
2936 ps_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
2937 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2938
2939 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2940
2941 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size != sizeof(impeg2d_ctl_set_config_ip_t))
2942 {
2943 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2944 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2945 return IV_FAIL;
2946 }
2947 }
2948 case IVD_CMD_CTL_SETDEFAULT:
2949 {
2950 impeg2d_ctl_set_config_op_t *ps_op;
2951 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2952 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2953
2954 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size != sizeof(impeg2d_ctl_set_config_op_t))
2955 {
2956 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2957 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2958 return IV_FAIL;
2959 }
2960 }
2961 break;
2962
2963 case IVD_CMD_CTL_GETPARAMS:
2964 {
2965 impeg2d_ctl_getstatus_ip_t *ps_ip;
2966 impeg2d_ctl_getstatus_op_t *ps_op;
2967
2968 ps_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
2969 ps_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
2970
2971 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code = 0;
2972
2973 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size != sizeof(impeg2d_ctl_getstatus_ip_t))
2974 {
2975 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2976 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2977 return IV_FAIL;
2978 }
2979 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size != sizeof(impeg2d_ctl_getstatus_op_t))
2980 {
2981 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2982 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2983 return IV_FAIL;
2984 }
2985 }
2986 break;
2987
2988 case IVD_CMD_CTL_GETBUFINFO:
2989 {
2990 impeg2d_ctl_getbufinfo_ip_t *ps_ip;
2991 impeg2d_ctl_getbufinfo_op_t *ps_op;
2992 ps_ip = (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
2993 ps_op = (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
2994
2995 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = 0;
2996
2997 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_ip_t))
2998 {
2999 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3000 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
3001 return IV_FAIL;
3002 }
3003 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_op_t))
3004 {
3005 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3006 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
3007 return IV_FAIL;
3008 }
3009 }
3010 break;
3011
3012 case IVD_CMD_CTL_GETVERSION:
3013 {
3014 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
3015 impeg2d_ctl_getversioninfo_op_t *ps_op;
3016 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
3017 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
3018
3019 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = 0;
3020
3021 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_ip_t))
3022 {
3023 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3024 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
3025 return IV_FAIL;
3026 }
3027 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_op_t))
3028 {
3029 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3030 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
3031 return IV_FAIL;
3032 }
3033 }
3034 break;
3035
3036 case IVD_CMD_CTL_FLUSH:
3037 {
3038 impeg2d_ctl_flush_ip_t *ps_ip;
3039 impeg2d_ctl_flush_op_t *ps_op;
3040 ps_ip = (impeg2d_ctl_flush_ip_t *)pv_api_ip;
3041 ps_op = (impeg2d_ctl_flush_op_t *)pv_api_op;
3042
3043 ps_op->s_ivd_ctl_flush_op_t.u4_error_code = 0;
3044
3045 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size != sizeof(impeg2d_ctl_flush_ip_t))
3046 {
3047 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3048 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
3049 return IV_FAIL;
3050 }
3051 if(ps_op->s_ivd_ctl_flush_op_t.u4_size != sizeof(impeg2d_ctl_flush_op_t))
3052 {
3053 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3054 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
3055 return IV_FAIL;
3056 }
3057 }
3058 break;
3059
3060 case IVD_CMD_CTL_RESET:
3061 {
3062 impeg2d_ctl_reset_ip_t *ps_ip;
3063 impeg2d_ctl_reset_op_t *ps_op;
3064 ps_ip = (impeg2d_ctl_reset_ip_t *)pv_api_ip;
3065 ps_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
3066
3067 ps_op->s_ivd_ctl_reset_op_t.u4_error_code = 0;
3068
3069 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size != sizeof(impeg2d_ctl_reset_ip_t))
3070 {
3071 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3072 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
3073 return IV_FAIL;
3074 }
3075 if(ps_op->s_ivd_ctl_reset_op_t.u4_size != sizeof(impeg2d_ctl_reset_op_t))
3076 {
3077 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3078 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
3079 return IV_FAIL;
3080 }
3081 }
3082 break;
3083
3084 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
3085 {
3086 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
3087 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
3088
3089 ps_ip =
3090 (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
3091 ps_op =
3092 (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
3093
3094 if(ps_ip->u4_size
3095 != sizeof(impeg2d_ctl_get_frame_dimensions_ip_t))
3096 {
3097 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3098 ps_op->u4_error_code |=
3099 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3100 return IV_FAIL;
3101 }
3102
3103 if(ps_op->u4_size
3104 != sizeof(impeg2d_ctl_get_frame_dimensions_op_t))
3105 {
3106 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3107 ps_op->u4_error_code |=
3108 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3109 return IV_FAIL;
3110 }
3111
3112 break;
3113 }
3114 case IMPEG2D_CMD_CTL_GET_SEQ_INFO:
3115 {
3116 impeg2d_ctl_get_seq_info_ip_t *ps_ip;
3117 impeg2d_ctl_get_seq_info_op_t *ps_op;
3118
3119 ps_ip =
3120 (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip;
3121 ps_op =
3122 (impeg2d_ctl_get_seq_info_op_t *)pv_api_op;
3123
3124 if(ps_ip->u4_size
3125 != sizeof(impeg2d_ctl_get_seq_info_ip_t))
3126 {
3127 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3128 ps_op->u4_error_code |=
3129 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3130 return IV_FAIL;
3131 }
3132
3133 if(ps_op->u4_size
3134 != sizeof(impeg2d_ctl_get_seq_info_op_t))
3135 {
3136 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3137 ps_op->u4_error_code |=
3138 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3139 return IV_FAIL;
3140 }
3141
3142 break;
3143 }
3144 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
3145 {
3146 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
3147 impeg2d_ctl_set_num_cores_op_t *ps_op;
3148
3149 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
3150 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
3151
3152 if(ps_ip->u4_size
3153 != sizeof(impeg2d_ctl_set_num_cores_ip_t))
3154 {
3155 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3156 ps_op->u4_error_code |=
3157 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3158 return IV_FAIL;
3159 }
3160
3161 if(ps_op->u4_size
3162 != sizeof(impeg2d_ctl_set_num_cores_op_t))
3163 {
3164 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3165 ps_op->u4_error_code |=
3166 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3167 return IV_FAIL;
3168 }
3169
3170 #ifdef MULTICORE
3171 if((ps_ip->u4_num_cores < 1) || (ps_ip->u4_num_cores > MAX_THREADS))
3172 #else
3173 if(ps_ip->u4_num_cores != 1)
3174 #endif
3175 {
3176 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3177 return IV_FAIL;
3178 }
3179 break;
3180 }
3181 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
3182 {
3183 impeg2d_ctl_set_processor_ip_t *ps_ip;
3184 impeg2d_ctl_set_processor_op_t *ps_op;
3185
3186 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
3187 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
3188
3189 if(ps_ip->u4_size
3190 != sizeof(impeg2d_ctl_set_processor_ip_t))
3191 {
3192 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3193 ps_op->u4_error_code |=
3194 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3195 return IV_FAIL;
3196 }
3197
3198 if(ps_op->u4_size
3199 != sizeof(impeg2d_ctl_set_processor_op_t))
3200 {
3201 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3202 ps_op->u4_error_code |=
3203 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3204 return IV_FAIL;
3205 }
3206
3207 break;
3208 }
3209 default:
3210 break;
3211
3212 }
3213 }
3214 break;
3215
3216 default:
3217 { *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
3218 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
3219 return IV_FAIL;
3220 }
3221
3222
3223 }
3224
3225 return IV_SUCCESS;
3226 }
3227
3228 /*****************************************************************************/
3229 /* */
3230 /* Function Name : impeg2d_api_entity */
3231 /* */
3232 /* Description : */
3233 /* */
3234 /* Inputs : */
3235 /* Globals : <Does it use any global variables?> */
3236 /* Outputs : */
3237 /* Returns : void */
3238 /* */
3239 /* Issues : none */
3240 /* */
3241 /* Revision History: */
3242 /* */
3243 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3244 /* 22 10 2008 100356 Draft */
3245 /* */
3246 /*****************************************************************************/
3247
3248
impeg2d_api_entity(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)3249 IV_API_CALL_STATUS_T impeg2d_api_entity(iv_obj_t *ps_dechdl,
3250 void *pv_api_ip,
3251 void *pv_api_op)
3252 {
3253 iv_obj_t *ps_dec_handle;
3254 dec_state_t *ps_dec_state;
3255 dec_state_multi_core_t *ps_dec_state_multi_core;
3256
3257 impeg2d_video_decode_ip_t *ps_dec_ip;
3258
3259 impeg2d_video_decode_op_t *ps_dec_op;
3260 WORD32 bytes_remaining;
3261 pic_buf_t *ps_disp_pic;
3262
3263
3264
3265 ps_dec_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
3266 ps_dec_op = (impeg2d_video_decode_op_t *)pv_api_op;
3267
3268 memset(ps_dec_op,0,sizeof(impeg2d_video_decode_op_t));
3269
3270 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3271 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3272 bytes_remaining = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3273
3274 ps_dec_handle = (iv_obj_t *)ps_dechdl;
3275
3276 if(ps_dechdl == NULL)
3277 {
3278 return(IV_FAIL);
3279 }
3280
3281
3282
3283 ps_dec_state_multi_core = ps_dec_handle->pv_codec_handle;
3284 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
3285
3286 ps_dec_state->ps_disp_frm_buf = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3287 if(0 == ps_dec_state->u4_share_disp_buf)
3288 {
3289 ps_dec_state->ps_disp_frm_buf->pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3290 ps_dec_state->ps_disp_frm_buf->pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3291 ps_dec_state->ps_disp_frm_buf->pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3292 }
3293
3294 ps_dec_state->ps_disp_pic = NULL;
3295 ps_dec_state->i4_frame_decoded = 0;
3296 /*rest bytes consumed */
3297 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = 0;
3298
3299 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IV_SUCCESS;
3300
3301 if((ps_dec_ip->s_ivd_video_decode_ip_t.pv_stream_buffer == NULL)&&(ps_dec_state->u1_flushfrm==0))
3302 {
3303 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3304 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
3305 return IV_FAIL;
3306 }
3307
3308
3309 if (ps_dec_state->u4_num_frames_decoded > NUM_FRAMES_LIMIT)
3310 {
3311 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IMPEG2D_SAMPLE_VERSION_LIMIT_ERR;
3312 return(IV_FAIL);
3313 }
3314
3315 if(((0 == ps_dec_state->u2_header_done) || (ps_dec_state->u2_decode_header == 1)) && (ps_dec_state->u1_flushfrm == 0))
3316 {
3317 impeg2d_dec_hdr(ps_dec_state,ps_dec_ip ,ps_dec_op);
3318 bytes_remaining -= ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed;
3319 }
3320
3321 if((1 != ps_dec_state->u2_decode_header) &&
3322 (((bytes_remaining > 0) && (1 == ps_dec_state->u2_header_done)) || ps_dec_state->u1_flushfrm))
3323 {
3324 if(ps_dec_state->u1_flushfrm)
3325 {
3326 if(ps_dec_state->aps_ref_pics[1] != NULL)
3327 {
3328 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[1], ps_dec_state->aps_ref_pics[1]->i4_buf_id);
3329 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF);
3330 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3331
3332 ps_dec_state->aps_ref_pics[1] = NULL;
3333 ps_dec_state->aps_ref_pics[0] = NULL;
3334
3335 }
3336 else if(ps_dec_state->aps_ref_pics[0] != NULL)
3337 {
3338 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[0], ps_dec_state->aps_ref_pics[0]->i4_buf_id);
3339 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3340
3341 ps_dec_state->aps_ref_pics[0] = NULL;
3342 }
3343 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3344 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3345
3346 ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id);
3347
3348 ps_dec_state->ps_disp_pic = ps_disp_pic;
3349 if(ps_disp_pic == NULL)
3350 {
3351 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3352 }
3353 else
3354 {
3355 WORD32 fmt_conv;
3356 if(0 == ps_dec_state->u4_share_disp_buf)
3357 {
3358 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3359 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3360 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3361 fmt_conv = 1;
3362 }
3363 else
3364 {
3365 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_disp_pic->pu1_y;
3366 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
3367 {
3368 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_disp_pic->pu1_u;
3369 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_disp_pic->pu1_v;
3370 fmt_conv = 0;
3371 }
3372 else
3373 {
3374 UWORD8 *pu1_buf;
3375
3376 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[1];
3377 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = pu1_buf;
3378
3379 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[2];
3380 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = pu1_buf;
3381 fmt_conv = 1;
3382 }
3383 }
3384
3385 if(fmt_conv == 1)
3386 {
3387 iv_yuv_buf_t *ps_dst;
3388
3389
3390 ps_dst = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3391 if(ps_dec_state->u4_deinterlace && (0 == ps_dec_state->u2_progressive_frame))
3392 {
3393 impeg2d_deinterlace(ps_dec_state,
3394 ps_disp_pic,
3395 ps_dst,
3396 0,
3397 ps_dec_state->u2_vertical_size);
3398
3399 }
3400 else
3401 {
3402 impeg2d_format_convert(ps_dec_state,
3403 ps_disp_pic,
3404 ps_dst,
3405 0,
3406 ps_dec_state->u2_vertical_size);
3407 }
3408 }
3409
3410 if(ps_dec_state->u4_deinterlace)
3411 {
3412 if(ps_dec_state->ps_deint_pic)
3413 {
3414 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3415 ps_dec_state->ps_deint_pic->i4_buf_id,
3416 MPEG2_BUF_MGR_DEINT);
3417 }
3418 ps_dec_state->ps_deint_pic = ps_disp_pic;
3419 }
3420 if(0 == ps_dec_state->u4_share_disp_buf)
3421 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3422
3423 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_ht = ps_dec_state->u2_vertical_size;
3424 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_wd = ps_dec_state->u2_horizontal_size;
3425 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3426
3427 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_disp_pic->i4_buf_id;
3428 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_disp_pic->u4_ts;
3429
3430 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3431
3432 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3433
3434 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3435
3436 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3437 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3438 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3439
3440 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = (ps_dec_state->u2_horizontal_size + 1) >> 1;
3441 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = (ps_dec_state->u4_frm_buf_stride + 1) >> 1;
3442 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = (ps_dec_state->u2_vertical_size + 1) >> 1;
3443
3444 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = (ps_dec_state->u2_horizontal_size + 1) >> 1;
3445 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = (ps_dec_state->u4_frm_buf_stride + 1) >> 1;
3446 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = (ps_dec_state->u2_vertical_size + 1) >> 1;
3447 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3448
3449 switch(ps_dec_state->i4_chromaFormat)
3450 {
3451 case IV_YUV_420SP_UV:
3452 case IV_YUV_420SP_VU:
3453 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = (((ps_dec_state->u2_horizontal_size + 1) >> 1) << 1);
3454 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3455 break;
3456 case IV_YUV_422ILE:
3457 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3458 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3459 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3460 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3461 break;
3462 default:
3463 break;
3464 }
3465
3466
3467 }
3468 if(ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3469 {
3470 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3471 {
3472 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3473 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3474 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3475 ps_dec_state->u4_frm_buf_stride,
3476 ps_dec_state->u2_horizontal_size,
3477 ps_dec_state->u2_vertical_size,
3478 ps_dec_state->i4_chromaFormat,
3479 ps_dec_state->u2_horizontal_size,
3480 ps_dec_state->u2_vertical_size);
3481 }
3482 return(IV_SUCCESS);
3483 }
3484 else
3485 {
3486 ps_dec_state->u1_flushfrm = 0;
3487
3488 return(IV_FAIL);
3489 }
3490
3491 }
3492 else if(ps_dec_state->u1_flushfrm==0)
3493 {
3494 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3495 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3496 if(ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes < 4)
3497 {
3498 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3499 return(IV_FAIL);
3500 }
3501
3502 if(1 == ps_dec_state->u4_share_disp_buf)
3503 {
3504 if(0 == impeg2_buf_mgr_check_free(ps_dec_state->pv_pic_buf_mg))
3505 {
3506 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code =
3507 (IMPEG2D_ERROR_CODES_T)IVD_DEC_REF_BUF_NULL;
3508 return IV_FAIL;
3509 }
3510 }
3511
3512
3513 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3514
3515 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3516
3517 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3518
3519 if (0 == ps_dec_state->u4_frm_buf_stride)
3520 {
3521 ps_dec_state->u4_frm_buf_stride = (ps_dec_state->u2_horizontal_size);
3522 }
3523
3524 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3525 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3526 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3527
3528 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = (ps_dec_state->u2_horizontal_size + 1) >> 1;
3529 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = (ps_dec_state->u4_frm_buf_stride + 1) >> 1;
3530 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = (ps_dec_state->u2_vertical_size + 1) >> 1;
3531
3532 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = (ps_dec_state->u2_horizontal_size + 1) >> 1;
3533 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = (ps_dec_state->u4_frm_buf_stride + 1) >> 1;
3534 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = (ps_dec_state->u2_vertical_size + 1) >> 1;
3535 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3536
3537 switch(ps_dec_state->i4_chromaFormat)
3538 {
3539 case IV_YUV_420SP_UV:
3540 case IV_YUV_420SP_VU:
3541 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = (((ps_dec_state->u2_horizontal_size + 1) >> 1) << 1);
3542 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3543 break;
3544 case IV_YUV_422ILE:
3545 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3546 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3547 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3548 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3549 break;
3550 default:
3551 break;
3552 }
3553
3554 if( ps_dec_state->u1_flushfrm == 0)
3555 {
3556 ps_dec_state->u1_flushcnt = 0;
3557
3558 ps_dec_state->ps_out_buf = &ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer;
3559 if (IV_SUCCESS != check_app_out_buf_size(ps_dec_state))
3560 {
3561 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
3562 return IV_FAIL;
3563 }
3564
3565 /*************************************************************************/
3566 /* Frame Decode */
3567 /*************************************************************************/
3568 ps_dec_state->u4_inp_ts = ps_dec_ip->s_ivd_video_decode_ip_t.u4_ts;
3569
3570 impeg2d_dec_frm(ps_dec_state,ps_dec_ip,ps_dec_op);
3571
3572 if (IVD_ERROR_NONE ==
3573 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3574 {
3575 if(ps_dec_state->u1_first_frame_done == 0)
3576 {
3577 ps_dec_state->u1_first_frame_done = 1;
3578 }
3579
3580 if(ps_dec_state->ps_disp_pic)
3581 {
3582 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3583 switch(ps_dec_state->ps_disp_pic->e_pic_type)
3584 {
3585 case I_PIC :
3586 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3587 break;
3588
3589 case P_PIC:
3590 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_P_FRAME;
3591 break;
3592
3593 case B_PIC:
3594 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_B_FRAME;
3595 break;
3596
3597 case D_PIC:
3598 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3599 break;
3600
3601 default :
3602 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_FRAMETYPE_DEFAULT;
3603 break;
3604 }
3605 }
3606 else
3607 {
3608 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3609 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_NA_FRAME;
3610 }
3611
3612 ps_dec_state->u4_num_frames_decoded++;
3613 }
3614 }
3615 else
3616 {
3617 ps_dec_state->u1_flushcnt++;
3618 }
3619 }
3620 if(ps_dec_state->ps_disp_pic)
3621 {
3622 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_dec_state->ps_disp_pic->i4_buf_id;
3623 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_dec_state->ps_disp_pic->u4_ts;
3624
3625 if(0 == ps_dec_state->u4_share_disp_buf)
3626 {
3627 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3628 }
3629 }
3630
3631 if(ps_dec_state->u4_deinterlace)
3632 {
3633 if(ps_dec_state->ps_deint_pic)
3634 {
3635 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3636 ps_dec_state->ps_deint_pic->i4_buf_id,
3637 MPEG2_BUF_MGR_DEINT);
3638 }
3639 ps_dec_state->ps_deint_pic = ps_dec_state->ps_disp_pic;
3640 }
3641
3642 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3643 {
3644 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3645 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3646 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3647 ps_dec_state->u4_frm_buf_stride,
3648 ps_dec_state->u2_horizontal_size,
3649 ps_dec_state->u2_vertical_size,
3650 ps_dec_state->i4_chromaFormat,
3651 ps_dec_state->u2_horizontal_size,
3652 ps_dec_state->u2_vertical_size);
3653 }
3654
3655 }
3656
3657 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = 1;
3658 ps_dec_op->s_ivd_video_decode_op_t.e4_fld_type = ps_dec_state->s_disp_op.e4_fld_type;
3659
3660
3661 if(ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3662 return IV_FAIL;
3663 else
3664 return IV_SUCCESS;
3665 }
3666