1 /*
2 * Copyright 2016 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6 #ifdef DRV_AMDGPU
7 #include <amdgpu.h>
8 #include <amdgpu_drm.h>
9 #include <assert.h>
10 #include <drm_fourcc.h>
11 #include <errno.h>
12 #include <fcntl.h>
13 #include <inttypes.h>
14 #include <stdio.h>
15 #include <stdlib.h>
16 #include <string.h>
17 #include <sys/mman.h>
18 #include <unistd.h>
19 #include <xf86drm.h>
20 #include <xf86drmMode.h>
21
22 #include "dri.h"
23 #include "drv_helpers.h"
24 #include "drv_priv.h"
25 #include "util.h"
26
27 // clang-format off
28 #define DRI_PATH STRINGIZE(DRI_DRIVER_DIR/radeonsi_dri.so)
29 // clang-format on
30
31 #define TILE_TYPE_LINEAR 0
32 /* We decide a modifier and then use DRI to manage allocation */
33 #define TILE_TYPE_DRI_MODIFIER 1
34 /* DRI backend decides tiling in this case. */
35 #define TILE_TYPE_DRI 2
36
37 /* Height alignement for Encoder/Decoder buffers */
38 #define CHROME_HEIGHT_ALIGN 16
39
40 struct amdgpu_priv {
41 struct dri_driver dri;
42 int drm_version;
43
44 /* sdma */
45 struct drm_amdgpu_info_device dev_info;
46 uint32_t sdma_ctx;
47 uint32_t sdma_cmdbuf_bo;
48 uint64_t sdma_cmdbuf_addr;
49 uint64_t sdma_cmdbuf_size;
50 uint32_t *sdma_cmdbuf_map;
51 };
52
53 struct amdgpu_linear_vma_priv {
54 uint32_t handle;
55 uint32_t map_flags;
56 };
57
58 const static uint32_t render_target_formats[] = {
59 DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
60 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888, DRM_FORMAT_ABGR2101010,
61 DRM_FORMAT_ARGB2101010, DRM_FORMAT_XBGR2101010, DRM_FORMAT_XRGB2101010,
62 DRM_FORMAT_ABGR16161616F,
63 };
64
65 const static uint32_t texture_source_formats[] = {
66 DRM_FORMAT_GR88, DRM_FORMAT_R8, DRM_FORMAT_NV21, DRM_FORMAT_NV12,
67 DRM_FORMAT_YVU420_ANDROID, DRM_FORMAT_YVU420, DRM_FORMAT_P010
68 };
69
query_dev_info(int fd,struct drm_amdgpu_info_device * dev_info)70 static int query_dev_info(int fd, struct drm_amdgpu_info_device *dev_info)
71 {
72 struct drm_amdgpu_info info_args = { 0 };
73
74 info_args.return_pointer = (uintptr_t)dev_info;
75 info_args.return_size = sizeof(*dev_info);
76 info_args.query = AMDGPU_INFO_DEV_INFO;
77
78 return drmCommandWrite(fd, DRM_AMDGPU_INFO, &info_args, sizeof(info_args));
79 }
80
sdma_init(struct amdgpu_priv * priv,int fd)81 static int sdma_init(struct amdgpu_priv *priv, int fd)
82 {
83 union drm_amdgpu_ctx ctx_args = { { 0 } };
84 union drm_amdgpu_gem_create gem_create = { { 0 } };
85 struct drm_amdgpu_gem_va va_args = { 0 };
86 union drm_amdgpu_gem_mmap gem_map = { { 0 } };
87 struct drm_gem_close gem_close = { 0 };
88 int ret;
89
90 /* Ensure we can make a submission without BO lists. */
91 if (priv->drm_version < 27)
92 return 0;
93
94 /* Anything outside this range needs adjustments to the SDMA copy commands */
95 if (priv->dev_info.family < AMDGPU_FAMILY_CI || priv->dev_info.family > AMDGPU_FAMILY_NV)
96 return 0;
97
98 ctx_args.in.op = AMDGPU_CTX_OP_ALLOC_CTX;
99
100 ret = drmCommandWriteRead(fd, DRM_AMDGPU_CTX, &ctx_args, sizeof(ctx_args));
101 if (ret < 0)
102 return ret;
103
104 priv->sdma_ctx = ctx_args.out.alloc.ctx_id;
105
106 priv->sdma_cmdbuf_size = ALIGN(4096, priv->dev_info.virtual_address_alignment);
107 gem_create.in.bo_size = priv->sdma_cmdbuf_size;
108 gem_create.in.alignment = 4096;
109 gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
110
111 ret = drmCommandWriteRead(fd, DRM_AMDGPU_GEM_CREATE, &gem_create, sizeof(gem_create));
112 if (ret < 0)
113 goto fail_ctx;
114
115 priv->sdma_cmdbuf_bo = gem_create.out.handle;
116
117 priv->sdma_cmdbuf_addr =
118 ALIGN(priv->dev_info.virtual_address_offset, priv->dev_info.virtual_address_alignment);
119
120 /* Map the buffer into the GPU address space so we can use it from the GPU */
121 va_args.handle = priv->sdma_cmdbuf_bo;
122 va_args.operation = AMDGPU_VA_OP_MAP;
123 va_args.flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_EXECUTABLE;
124 va_args.va_address = priv->sdma_cmdbuf_addr;
125 va_args.offset_in_bo = 0;
126 va_args.map_size = priv->sdma_cmdbuf_size;
127
128 ret = drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
129 if (ret)
130 goto fail_bo;
131
132 gem_map.in.handle = priv->sdma_cmdbuf_bo;
133 ret = drmIoctl(fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
134 if (ret)
135 goto fail_va;
136
137 priv->sdma_cmdbuf_map = mmap(0, priv->sdma_cmdbuf_size, PROT_READ | PROT_WRITE, MAP_SHARED,
138 fd, gem_map.out.addr_ptr);
139 if (priv->sdma_cmdbuf_map == MAP_FAILED) {
140 priv->sdma_cmdbuf_map = NULL;
141 ret = -ENOMEM;
142 goto fail_va;
143 }
144
145 return 0;
146 fail_va:
147 va_args.operation = AMDGPU_VA_OP_UNMAP;
148 va_args.flags = 0;
149 drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
150 fail_bo:
151 gem_close.handle = priv->sdma_cmdbuf_bo;
152 drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
153 fail_ctx:
154 memset(&ctx_args, 0, sizeof(ctx_args));
155 ctx_args.in.op = AMDGPU_CTX_OP_FREE_CTX;
156 ctx_args.in.ctx_id = priv->sdma_ctx;
157 drmCommandWriteRead(fd, DRM_AMDGPU_CTX, &ctx_args, sizeof(ctx_args));
158 return ret;
159 }
160
sdma_finish(struct amdgpu_priv * priv,int fd)161 static void sdma_finish(struct amdgpu_priv *priv, int fd)
162 {
163 union drm_amdgpu_ctx ctx_args = { { 0 } };
164 struct drm_amdgpu_gem_va va_args = { 0 };
165 struct drm_gem_close gem_close = { 0 };
166
167 if (!priv->sdma_cmdbuf_map)
168 return;
169
170 va_args.handle = priv->sdma_cmdbuf_bo;
171 va_args.operation = AMDGPU_VA_OP_UNMAP;
172 va_args.flags = 0;
173 va_args.va_address = priv->sdma_cmdbuf_addr;
174 va_args.offset_in_bo = 0;
175 va_args.map_size = priv->sdma_cmdbuf_size;
176 drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
177
178 gem_close.handle = priv->sdma_cmdbuf_bo;
179 drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
180
181 ctx_args.in.op = AMDGPU_CTX_OP_FREE_CTX;
182 ctx_args.in.ctx_id = priv->sdma_ctx;
183 drmCommandWriteRead(fd, DRM_AMDGPU_CTX, &ctx_args, sizeof(ctx_args));
184 }
185
sdma_copy(struct amdgpu_priv * priv,int fd,uint32_t src_handle,uint32_t dst_handle,uint64_t size)186 static int sdma_copy(struct amdgpu_priv *priv, int fd, uint32_t src_handle, uint32_t dst_handle,
187 uint64_t size)
188 {
189 const uint64_t max_size_per_cmd = 0x3fff00;
190 const uint32_t cmd_size = 7 * sizeof(uint32_t); /* 7 dwords, see loop below. */
191 const uint64_t max_commands = priv->sdma_cmdbuf_size / cmd_size;
192 uint64_t src_addr = priv->sdma_cmdbuf_addr + priv->sdma_cmdbuf_size;
193 uint64_t dst_addr = src_addr + size;
194 struct drm_amdgpu_gem_va va_args = { 0 };
195 unsigned cmd = 0;
196 uint64_t remaining_size = size;
197 uint64_t cur_src_addr = src_addr;
198 uint64_t cur_dst_addr = dst_addr;
199 struct drm_amdgpu_cs_chunk_ib ib = { 0 };
200 struct drm_amdgpu_cs_chunk chunks[2] = { { 0 } };
201 uint64_t chunk_ptrs[2];
202 union drm_amdgpu_cs cs = { { 0 } };
203 struct drm_amdgpu_bo_list_in bo_list = { 0 };
204 struct drm_amdgpu_bo_list_entry bo_list_entries[3] = { { 0 } };
205 union drm_amdgpu_wait_cs wait_cs = { { 0 } };
206 int ret = 0;
207
208 if (size > UINT64_MAX - max_size_per_cmd ||
209 DIV_ROUND_UP(size, max_size_per_cmd) > max_commands)
210 return -ENOMEM;
211
212 /* Map both buffers into the GPU address space so we can access them from the GPU. */
213 va_args.handle = src_handle;
214 va_args.operation = AMDGPU_VA_OP_MAP;
215 va_args.flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_DELAY_UPDATE;
216 va_args.va_address = src_addr;
217 va_args.map_size = size;
218
219 ret = drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
220 if (ret)
221 return ret;
222
223 va_args.handle = dst_handle;
224 va_args.flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_DELAY_UPDATE;
225 va_args.va_address = dst_addr;
226
227 ret = drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
228 if (ret)
229 goto unmap_src;
230
231 while (remaining_size) {
232 uint64_t cur_size = remaining_size;
233 if (cur_size > max_size_per_cmd)
234 cur_size = max_size_per_cmd;
235
236 priv->sdma_cmdbuf_map[cmd++] = 0x01; /* linear copy */
237 priv->sdma_cmdbuf_map[cmd++] =
238 priv->dev_info.family >= AMDGPU_FAMILY_AI ? (cur_size - 1) : cur_size;
239 priv->sdma_cmdbuf_map[cmd++] = 0;
240 priv->sdma_cmdbuf_map[cmd++] = cur_src_addr;
241 priv->sdma_cmdbuf_map[cmd++] = cur_src_addr >> 32;
242 priv->sdma_cmdbuf_map[cmd++] = cur_dst_addr;
243 priv->sdma_cmdbuf_map[cmd++] = cur_dst_addr >> 32;
244
245 remaining_size -= cur_size;
246 cur_src_addr += cur_size;
247 cur_dst_addr += cur_size;
248 }
249
250 ib.va_start = priv->sdma_cmdbuf_addr;
251 ib.ib_bytes = cmd * 4;
252 ib.ip_type = AMDGPU_HW_IP_DMA;
253
254 chunks[1].chunk_id = AMDGPU_CHUNK_ID_IB;
255 chunks[1].length_dw = sizeof(ib) / 4;
256 chunks[1].chunk_data = (uintptr_t)&ib;
257
258 bo_list_entries[0].bo_handle = priv->sdma_cmdbuf_bo;
259 bo_list_entries[0].bo_priority = 8; /* Middle of range, like RADV. */
260 bo_list_entries[1].bo_handle = src_handle;
261 bo_list_entries[1].bo_priority = 8;
262 bo_list_entries[2].bo_handle = dst_handle;
263 bo_list_entries[2].bo_priority = 8;
264
265 bo_list.bo_number = 3;
266 bo_list.bo_info_size = sizeof(bo_list_entries[0]);
267 bo_list.bo_info_ptr = (uintptr_t)bo_list_entries;
268
269 chunks[0].chunk_id = AMDGPU_CHUNK_ID_BO_HANDLES;
270 chunks[0].length_dw = sizeof(bo_list) / 4;
271 chunks[0].chunk_data = (uintptr_t)&bo_list;
272
273 chunk_ptrs[0] = (uintptr_t)&chunks[0];
274 chunk_ptrs[1] = (uintptr_t)&chunks[1];
275
276 cs.in.ctx_id = priv->sdma_ctx;
277 cs.in.num_chunks = 2;
278 cs.in.chunks = (uintptr_t)chunk_ptrs;
279
280 ret = drmCommandWriteRead(fd, DRM_AMDGPU_CS, &cs, sizeof(cs));
281 if (ret) {
282 drv_loge("SDMA copy command buffer submission failed %d\n", ret);
283 goto unmap_dst;
284 }
285
286 wait_cs.in.handle = cs.out.handle;
287 wait_cs.in.ip_type = AMDGPU_HW_IP_DMA;
288 wait_cs.in.ctx_id = priv->sdma_ctx;
289 wait_cs.in.timeout = INT64_MAX;
290
291 ret = drmCommandWriteRead(fd, DRM_AMDGPU_WAIT_CS, &wait_cs, sizeof(wait_cs));
292 if (ret) {
293 drv_loge("Could not wait for CS to finish\n");
294 } else if (wait_cs.out.status) {
295 drv_loge("Infinite wait timed out, likely GPU hang.\n");
296 ret = -ENODEV;
297 }
298
299 unmap_dst:
300 va_args.handle = dst_handle;
301 va_args.operation = AMDGPU_VA_OP_UNMAP;
302 va_args.flags = AMDGPU_VM_DELAY_UPDATE;
303 va_args.va_address = dst_addr;
304 drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
305
306 unmap_src:
307 va_args.handle = src_handle;
308 va_args.operation = AMDGPU_VA_OP_UNMAP;
309 va_args.flags = AMDGPU_VM_DELAY_UPDATE;
310 va_args.va_address = src_addr;
311 drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
312
313 return ret;
314 }
315
is_modifier_scanout_capable(struct amdgpu_priv * priv,uint32_t format,uint64_t modifier)316 static bool is_modifier_scanout_capable(struct amdgpu_priv *priv, uint32_t format,
317 uint64_t modifier)
318 {
319 unsigned bytes_per_pixel = drv_stride_from_format(format, 1, 0);
320
321 if (modifier == DRM_FORMAT_MOD_LINEAR)
322 return true;
323
324 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_AMD)
325 return false;
326
327 unsigned swizzle = AMD_FMT_MOD_GET(TILE, modifier);
328 if (priv->dev_info.family >= AMDGPU_FAMILY_RV) { /* DCN based GPUs */
329 /* D swizzle only supported for 64 bpp */
330 if ((swizzle & 3) == 2 && bytes_per_pixel != 8)
331 return false;
332
333 /* S swizzle not supported for 64 bpp */
334 if ((swizzle & 3) == 1 && bytes_per_pixel == 8)
335 return false;
336 } else { /* DCE based GPUs with GFX9 based modifier swizzling. */
337 assert(priv->dev_info.family == AMDGPU_FAMILY_AI);
338 /* Only D swizzles are allowed for display */
339 if ((swizzle & 3) != 2)
340 return false;
341 }
342
343 if (AMD_FMT_MOD_GET(DCC, modifier) &&
344 (AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier) || !AMD_FMT_MOD_GET(DCC_RETILE, modifier)))
345 return false;
346 return true;
347 }
348
amdgpu_preload(bool load)349 static void amdgpu_preload(bool load)
350 {
351 static void *handle;
352
353 if (load && !handle)
354 handle = dri_dlopen(DRI_PATH);
355 else if (!load && handle) {
356 dri_dlclose(handle);
357 handle = NULL;
358 }
359 }
360
amdgpu_init(struct driver * drv)361 static int amdgpu_init(struct driver *drv)
362 {
363 struct amdgpu_priv *priv;
364 drmVersionPtr drm_version;
365 struct format_metadata metadata;
366 uint64_t use_flags = BO_USE_RENDER_MASK;
367
368 priv = calloc(1, sizeof(struct amdgpu_priv));
369 if (!priv)
370 return -ENOMEM;
371
372 drm_version = drmGetVersion(drv_get_fd(drv));
373 if (!drm_version) {
374 free(priv);
375 return -ENODEV;
376 }
377
378 priv->drm_version = drm_version->version_minor;
379 drmFreeVersion(drm_version);
380
381 drv->priv = priv;
382
383 if (query_dev_info(drv_get_fd(drv), &priv->dev_info)) {
384 free(priv);
385 drv->priv = NULL;
386 return -ENODEV;
387 }
388 if (dri_init(drv, DRI_PATH, "radeonsi")) {
389 free(priv);
390 drv->priv = NULL;
391 return -ENODEV;
392 }
393
394 /* Continue on failure, as we can still succesfully map things without SDMA. */
395 if (sdma_init(priv, drv_get_fd(drv)))
396 drv_loge("SDMA init failed\n");
397
398 metadata.tiling = TILE_TYPE_LINEAR;
399 metadata.priority = 1;
400 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
401
402 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
403 &metadata, use_flags);
404
405 drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
406 &metadata, BO_USE_TEXTURE_MASK);
407
408 /* NV12 format for camera, display, decoding and encoding. */
409 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
410 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
411 BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER |
412 BO_USE_PROTECTED);
413
414 drv_modify_combination(drv, DRM_FORMAT_P010, &metadata,
415 BO_USE_SCANOUT | BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER |
416 BO_USE_PROTECTED);
417
418 /* Android CTS tests require this. */
419 drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
420
421 /* Linear formats supported by display. */
422 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
423 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
424 drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
425 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
426 drv_modify_combination(drv, DRM_FORMAT_RGB565, &metadata, BO_USE_SCANOUT);
427
428 drv_modify_combination(drv, DRM_FORMAT_ABGR2101010, &metadata, BO_USE_SCANOUT);
429 drv_modify_combination(drv, DRM_FORMAT_ARGB2101010, &metadata, BO_USE_SCANOUT);
430 drv_modify_combination(drv, DRM_FORMAT_XBGR2101010, &metadata, BO_USE_SCANOUT);
431 drv_modify_combination(drv, DRM_FORMAT_XRGB2101010, &metadata, BO_USE_SCANOUT);
432
433 drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT);
434
435 /*
436 * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
437 * from camera and input/output from hardware decoder/encoder.
438 */
439 drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
440 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
441 BO_USE_HW_VIDEO_ENCODER | BO_USE_GPU_DATA_BUFFER |
442 BO_USE_SENSOR_DIRECT_DATA);
443
444 /*
445 * The following formats will be allocated by the DRI backend and may be potentially tiled.
446 * Since format modifier support hasn't been implemented fully yet, it's not
447 * possible to enumerate the different types of buffers (like i915 can).
448 */
449 use_flags &= ~BO_USE_RENDERSCRIPT;
450 use_flags &= ~BO_USE_SW_WRITE_OFTEN;
451 use_flags &= ~BO_USE_SW_READ_OFTEN;
452 #if __ANDROID__
453 use_flags &= ~BO_USE_SW_WRITE_RARELY;
454 use_flags &= ~BO_USE_SW_READ_RARELY;
455 #endif
456 use_flags &= ~BO_USE_LINEAR;
457
458 metadata.priority = 2;
459
460 for (unsigned f = 0; f < ARRAY_SIZE(render_target_formats); ++f) {
461 uint32_t format = render_target_formats[f];
462 int mod_cnt;
463 if (dri_query_modifiers(drv, format, 0, NULL, &mod_cnt) && mod_cnt) {
464 uint64_t *modifiers = calloc(mod_cnt, sizeof(uint64_t));
465 dri_query_modifiers(drv, format, mod_cnt, modifiers, &mod_cnt);
466 metadata.tiling = TILE_TYPE_DRI_MODIFIER;
467 for (int i = 0; i < mod_cnt; ++i) {
468 bool scanout =
469 is_modifier_scanout_capable(drv->priv, format, modifiers[i]);
470
471 /* LINEAR will be handled using the LINEAR metadata. */
472 if (modifiers[i] == DRM_FORMAT_MOD_LINEAR)
473 continue;
474
475 /* The virtgpu minigbm can't handle auxiliary planes in the host. */
476 if (dri_num_planes_from_modifier(drv, format, modifiers[i]) !=
477 drv_num_planes_from_format(format))
478 continue;
479
480 metadata.modifier = modifiers[i];
481 drv_add_combination(drv, format, &metadata,
482 use_flags | (scanout ? BO_USE_SCANOUT : 0));
483 }
484 free(modifiers);
485 } else {
486 bool scanout = false;
487 switch (format) {
488 case DRM_FORMAT_ARGB8888:
489 case DRM_FORMAT_XRGB8888:
490 case DRM_FORMAT_ABGR8888:
491 case DRM_FORMAT_XBGR8888:
492 case DRM_FORMAT_ABGR2101010:
493 case DRM_FORMAT_ARGB2101010:
494 case DRM_FORMAT_XBGR2101010:
495 case DRM_FORMAT_XRGB2101010:
496 scanout = true;
497 break;
498 default:
499 break;
500 }
501 metadata.tiling = TILE_TYPE_DRI;
502 drv_add_combination(drv, format, &metadata,
503 use_flags | (scanout ? BO_USE_SCANOUT : 0));
504 }
505 }
506 return 0;
507 }
508
amdgpu_close(struct driver * drv)509 static void amdgpu_close(struct driver *drv)
510 {
511 sdma_finish(drv->priv, drv_get_fd(drv));
512 dri_close(drv);
513 free(drv->priv);
514 drv->priv = NULL;
515 }
516
amdgpu_create_bo_linear(struct bo * bo,uint32_t width,uint32_t height,uint32_t format,uint64_t use_flags)517 static int amdgpu_create_bo_linear(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
518 uint64_t use_flags)
519 {
520 int ret;
521 uint32_t stride_align = 1;
522 uint32_t plane, stride;
523 union drm_amdgpu_gem_create gem_create = { { 0 } };
524 struct amdgpu_priv *priv = bo->drv->priv;
525
526 stride = drv_stride_from_format(format, width, 0);
527
528 if (use_flags & BO_USE_HW_MASK) {
529 /* GFX9+ requires the stride to be aligned to 256 bytes */
530 stride_align = 256;
531 stride = ALIGN(stride, stride_align);
532
533 /* Android YV12 requires the UV stride to be half of the Y
534 * stride. Before GFX10, we can double the alignment for the
535 * Y stride, which makes sure the UV stride is still aligned
536 * to 256 bytes after halving.
537 *
538 * GFX10+ additionally requires the stride to be as small as
539 * possible. It is impossible to support the format in some
540 * cases. Instead, we force DRM_FORMAT_YVU420 and knowingly
541 * vioate Android YV12 stride requirement. This is done
542 * because
543 *
544 * - we would like to know what breaks, and
545 * - when used as a classic resource by virglrenderer, the
546 * requirement hopefully does not matter
547 */
548 bool double_align = format == DRM_FORMAT_YVU420_ANDROID;
549 if (double_align && priv->dev_info.family >= AMDGPU_FAMILY_NV &&
550 (use_flags & BO_USE_GPU_HW) && ((stride / stride_align) & 1)) {
551 drv_loge("allocating %dx%d YV12 bo (usage 0x%" PRIx64 ") with bad strides",
552 width, height, use_flags);
553 format = DRM_FORMAT_YVU420;
554 double_align = false;
555 }
556 if (double_align)
557 stride = ALIGN(stride, stride_align * 2);
558 }
559
560 /*
561 * Currently, allocator used by chrome aligns the height for Encoder/
562 * Decoder buffers while allocator used by android(gralloc/minigbm)
563 * doesn't provide any aligment.
564 *
565 * See b/153130069
566 */
567 if (use_flags & (BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER))
568 height = ALIGN(height, CHROME_HEIGHT_ALIGN);
569
570 drv_bo_from_format(bo, stride, stride_align, height, format);
571
572 gem_create.in.bo_size =
573 ALIGN(bo->meta.total_size, priv->dev_info.virtual_address_alignment);
574 gem_create.in.alignment = 256;
575 gem_create.in.domain_flags = 0;
576
577 if (use_flags & (BO_USE_LINEAR | BO_USE_SW_MASK))
578 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
579
580 gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
581
582 /* Scanout in GTT requires USWC, otherwise try to use cachable memory
583 * for buffers that are read often, because uncacheable reads can be
584 * very slow. USWC should be faster on the GPU though. */
585 if ((use_flags & BO_USE_SCANOUT) || !(use_flags & BO_USE_SW_READ_OFTEN))
586 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
587
588 /* For protected data Buffer needs to be allocated from TMZ */
589 if (use_flags & BO_USE_PROTECTED)
590 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_ENCRYPTED;
591
592 /* Allocate the buffer with the preferred heap. */
593 ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
594 sizeof(gem_create));
595 if (ret < 0)
596 return ret;
597
598 for (plane = 0; plane < bo->meta.num_planes; plane++)
599 bo->handles[plane].u32 = gem_create.out.handle;
600
601 bo->meta.format_modifier = DRM_FORMAT_MOD_LINEAR;
602
603 return 0;
604 }
605
amdgpu_create_bo(struct bo * bo,uint32_t width,uint32_t height,uint32_t format,uint64_t use_flags)606 static int amdgpu_create_bo(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
607 uint64_t use_flags)
608 {
609 struct combination *combo;
610 struct amdgpu_priv *priv = bo->drv->priv;
611
612 combo = drv_get_combination(bo->drv, format, use_flags);
613 if (!combo)
614 return -EINVAL;
615
616 if (combo->metadata.tiling == TILE_TYPE_DRI) {
617 // See b/122049612
618 if (use_flags & (BO_USE_SCANOUT) && priv->dev_info.family == AMDGPU_FAMILY_CZ) {
619 uint32_t bytes_per_pixel = drv_bytes_per_pixel_from_format(format, 0);
620 width = ALIGN(width, 256 / bytes_per_pixel);
621 }
622
623 return dri_bo_create(bo, width, height, format, use_flags);
624 } else if (combo->metadata.tiling == TILE_TYPE_DRI_MODIFIER) {
625 return dri_bo_create_with_modifiers(bo, width, height, format,
626 &combo->metadata.modifier, 1);
627 }
628
629 return amdgpu_create_bo_linear(bo, width, height, format, use_flags);
630 }
631
amdgpu_create_bo_with_modifiers(struct bo * bo,uint32_t width,uint32_t height,uint32_t format,const uint64_t * modifiers,uint32_t count)632 static int amdgpu_create_bo_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
633 uint32_t format, const uint64_t *modifiers,
634 uint32_t count)
635 {
636 bool only_use_linear = true;
637
638 for (uint32_t i = 0; i < count; ++i)
639 if (modifiers[i] != DRM_FORMAT_MOD_LINEAR)
640 only_use_linear = false;
641
642 if (only_use_linear)
643 return amdgpu_create_bo_linear(bo, width, height, format, BO_USE_SCANOUT);
644
645 return dri_bo_create_with_modifiers(bo, width, height, format, modifiers, count);
646 }
647
amdgpu_import_bo(struct bo * bo,struct drv_import_fd_data * data)648 static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data)
649 {
650 bool dri_tiling = data->format_modifier != DRM_FORMAT_MOD_LINEAR;
651 if (data->format_modifier == DRM_FORMAT_MOD_INVALID) {
652 struct combination *combo;
653 combo = drv_get_combination(bo->drv, data->format, data->use_flags);
654 if (!combo)
655 return -EINVAL;
656
657 dri_tiling = combo->metadata.tiling != TILE_TYPE_LINEAR;
658 }
659
660 bo->meta.num_planes =
661 dri_num_planes_from_modifier(bo->drv, data->format, data->format_modifier);
662
663 if (dri_tiling)
664 return dri_bo_import(bo, data);
665 else
666 return drv_prime_bo_import(bo, data);
667 }
668
amdgpu_release_bo(struct bo * bo)669 static int amdgpu_release_bo(struct bo *bo)
670 {
671 if (bo->priv)
672 return dri_bo_release(bo);
673
674 return 0;
675 }
676
amdgpu_destroy_bo(struct bo * bo)677 static int amdgpu_destroy_bo(struct bo *bo)
678 {
679 if (bo->priv)
680 return dri_bo_destroy(bo);
681 else
682 return drv_gem_bo_destroy(bo);
683 }
684
amdgpu_map_bo(struct bo * bo,struct vma * vma,uint32_t map_flags)685 static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, uint32_t map_flags)
686 {
687 void *addr = MAP_FAILED;
688 int ret;
689 union drm_amdgpu_gem_mmap gem_map = { { 0 } };
690 struct drm_amdgpu_gem_create_in bo_info = { 0 };
691 struct drm_amdgpu_gem_op gem_op = { 0 };
692 uint32_t handle = bo->handles[0].u32;
693 struct amdgpu_linear_vma_priv *priv = NULL;
694 struct amdgpu_priv *drv_priv;
695
696 if (bo->priv)
697 return dri_bo_map(bo, vma, 0, map_flags);
698
699 drv_priv = bo->drv->priv;
700 gem_op.handle = handle;
701 gem_op.op = AMDGPU_GEM_OP_GET_GEM_CREATE_INFO;
702 gem_op.value = (uintptr_t)&bo_info;
703
704 ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_OP, &gem_op, sizeof(gem_op));
705 if (ret)
706 return MAP_FAILED;
707
708 vma->length = bo_info.bo_size;
709
710 if (((bo_info.domains & AMDGPU_GEM_DOMAIN_VRAM) ||
711 (bo_info.domain_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)) &&
712 drv_priv->sdma_cmdbuf_map) {
713 union drm_amdgpu_gem_create gem_create = { { 0 } };
714
715 priv = calloc(1, sizeof(struct amdgpu_linear_vma_priv));
716 if (!priv)
717 return MAP_FAILED;
718
719 gem_create.in.bo_size = bo_info.bo_size;
720 gem_create.in.alignment = 4096;
721 gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
722
723 ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_CREATE, &gem_create,
724 sizeof(gem_create));
725 if (ret < 0) {
726 drv_loge("GEM create failed\n");
727 free(priv);
728 return MAP_FAILED;
729 }
730
731 priv->map_flags = map_flags;
732 handle = priv->handle = gem_create.out.handle;
733
734 ret = sdma_copy(bo->drv->priv, bo->drv->fd, bo->handles[0].u32, priv->handle,
735 bo_info.bo_size);
736 if (ret) {
737 drv_loge("SDMA copy for read failed\n");
738 goto fail;
739 }
740 }
741
742 gem_map.in.handle = handle;
743 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
744 if (ret) {
745 drv_loge("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
746 goto fail;
747 }
748
749 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
750 gem_map.out.addr_ptr);
751 if (addr == MAP_FAILED)
752 goto fail;
753
754 vma->priv = priv;
755 return addr;
756
757 fail:
758 if (priv) {
759 struct drm_gem_close gem_close = { 0 };
760 gem_close.handle = priv->handle;
761 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
762 free(priv);
763 }
764 return MAP_FAILED;
765 }
766
amdgpu_unmap_bo(struct bo * bo,struct vma * vma)767 static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma)
768 {
769 if (bo->priv) {
770 return dri_bo_unmap(bo, vma);
771 } else {
772 int r = munmap(vma->addr, vma->length);
773 if (r)
774 return r;
775
776 if (vma->priv) {
777 struct amdgpu_linear_vma_priv *priv = vma->priv;
778 struct drm_gem_close gem_close = { 0 };
779
780 if (BO_MAP_WRITE & priv->map_flags) {
781 r = sdma_copy(bo->drv->priv, bo->drv->fd, priv->handle,
782 bo->handles[0].u32, vma->length);
783 if (r)
784 return r;
785 }
786
787 gem_close.handle = priv->handle;
788 r = drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
789 }
790
791 return 0;
792 }
793 }
794
amdgpu_bo_invalidate(struct bo * bo,struct mapping * mapping)795 static int amdgpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
796 {
797 int ret;
798 union drm_amdgpu_gem_wait_idle wait_idle = { { 0 } };
799
800 if (bo->priv)
801 return 0;
802
803 wait_idle.in.handle = bo->handles[0].u32;
804 wait_idle.in.timeout = AMDGPU_TIMEOUT_INFINITE;
805
806 ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_WAIT_IDLE, &wait_idle,
807 sizeof(wait_idle));
808
809 if (ret < 0) {
810 drv_loge("DRM_AMDGPU_GEM_WAIT_IDLE failed with %d\n", ret);
811 return ret;
812 }
813
814 if (ret == 0 && wait_idle.out.status)
815 drv_loge("DRM_AMDGPU_GEM_WAIT_IDLE BO is busy\n");
816
817 return 0;
818 }
819
820 const struct backend backend_amdgpu = {
821 .name = "amdgpu",
822 .preload = amdgpu_preload,
823 .init = amdgpu_init,
824 .close = amdgpu_close,
825 .bo_create = amdgpu_create_bo,
826 .bo_create_with_modifiers = amdgpu_create_bo_with_modifiers,
827 .bo_release = amdgpu_release_bo,
828 .bo_destroy = amdgpu_destroy_bo,
829 .bo_import = amdgpu_import_bo,
830 .bo_map = amdgpu_map_bo,
831 .bo_unmap = amdgpu_unmap_bo,
832 .bo_invalidate = amdgpu_bo_invalidate,
833 .resolve_format_and_use_flags = drv_resolve_format_and_use_flags_helper,
834 .num_planes_from_modifier = dri_num_planes_from_modifier,
835 };
836
837 #endif
838