Lines Matching refs:rs2
797 Reg rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FpBinOp() argument
800 (assembler->*opS)(rd, rs1, rs2); in FpBinOp()
803 (assembler->*opD)(rd, rs1, rs2); in FpBinOp()
808 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FAdd() argument
809 FpBinOp<FRegister, &Riscv64Assembler::FAddS, &Riscv64Assembler::FAddD>(rd, rs1, rs2, type); in FAdd()
813 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FSub() argument
814 FpBinOp<FRegister, &Riscv64Assembler::FSubS, &Riscv64Assembler::FSubD>(rd, rs1, rs2, type); in FSub()
818 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FDiv() argument
819 FpBinOp<FRegister, &Riscv64Assembler::FDivS, &Riscv64Assembler::FDivD>(rd, rs1, rs2, type); in FDiv()
823 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FMul() argument
824 FpBinOp<FRegister, &Riscv64Assembler::FMulS, &Riscv64Assembler::FMulD>(rd, rs1, rs2, type); in FMul()
828 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FMin() argument
829 FpBinOp<FRegister, &Riscv64Assembler::FMinS, &Riscv64Assembler::FMinD>(rd, rs1, rs2, type); in FMin()
833 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FMax() argument
834 FpBinOp<FRegister, &Riscv64Assembler::FMaxS, &Riscv64Assembler::FMaxD>(rd, rs1, rs2, type); in FMax()
838 XRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FEq() argument
839 FpBinOp<XRegister, &Riscv64Assembler::FEqS, &Riscv64Assembler::FEqD>(rd, rs1, rs2, type); in FEq()
843 XRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FLt() argument
844 FpBinOp<XRegister, &Riscv64Assembler::FLtS, &Riscv64Assembler::FLtD>(rd, rs1, rs2, type); in FLt()
848 XRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FLe() argument
849 FpBinOp<XRegister, &Riscv64Assembler::FLeS, &Riscv64Assembler::FLeD>(rd, rs1, rs2, type); in FLe()
1022 XRegister rd, XRegister rs1, XRegister rs2, DataType::Type type) { in ShNAdd() argument
1028 __ Add(rd, rs1, rs2); in ShNAdd()
1033 __ Sh1Add(rd, rs1, rs2); in ShNAdd()
1039 __ Sh2Add(rd, rs1, rs2); in ShNAdd()
1044 __ Sh3Add(rd, rs1, rs2); in ShNAdd()
1588 XRegister rs2 = use_imm ? kNoXRegister : rs2_location.AsRegister<XRegister>(); in GenerateIntLongCondition() local
1594 __ Sub(rd, rs1, rs2); // SUB is OK here even for 32-bit comparison. in GenerateIntLongCondition()
1612 __ Slt(rd, rs1, rs2); in GenerateIntLongCondition()
1625 __ Slt(rd, rs2, rs1); in GenerateIntLongCondition()
1641 __ Sltu(rd, rs1, rs2); in GenerateIntLongCondition()
1657 __ Sltu(rd, rs2, rs1); in GenerateIntLongCondition()
1801 FRegister rs2 = locations->InAt(1).AsFpuRegister<FRegister>(); in GenerateFpCondition() local
1806 FEq(rd, rs1, rs2, type); in GenerateFpCondition()
1809 FEq(rd, rs1, rs2, type); in GenerateFpCondition()
1814 FLt(rd, rs1, rs2, type); in GenerateFpCondition()
1816 FLe(rd, rs2, rs1, type); in GenerateFpCondition()
1822 FLe(rd, rs1, rs2, type); in GenerateFpCondition()
1824 FLt(rd, rs2, rs1, type); in GenerateFpCondition()
1830 FLe(rd, rs1, rs2, type); in GenerateFpCondition()
1833 FLt(rd, rs2, rs1, type); in GenerateFpCondition()
1838 FLt(rd, rs1, rs2, type); in GenerateFpCondition()
1841 FLe(rd, rs2, rs1, type); in GenerateFpCondition()
2161 XRegister rs2 = use_imm ? kNoXRegister : rs2_location.AsRegister<XRegister>(); in HandleBinaryOp() local
2168 __ And(rd, rs1, rs2); in HandleBinaryOp()
2174 __ Or(rd, rs1, rs2); in HandleBinaryOp()
2180 __ Xor(rd, rs1, rs2); in HandleBinaryOp()
2187 __ Addw(rd, rs1, rs2); in HandleBinaryOp()
2190 __ Subw(rd, rs1, rs2); in HandleBinaryOp()
2196 __ Add(rd, rs1, rs2); in HandleBinaryOp()
2199 __ Sub(rd, rs1, rs2); in HandleBinaryOp()
2204 __ Min(rd, rs1, use_imm ? Zero : rs2); in HandleBinaryOp()
2208 __ Max(rd, rs1, use_imm ? Zero : rs2); in HandleBinaryOp()
2216 FRegister rs2 = locations->InAt(1).AsFpuRegister<FRegister>(); in HandleBinaryOp() local
2218 FAdd(rd, rs1, rs2, type); in HandleBinaryOp()
2220 FSub(rd, rs1, rs2, type); in HandleBinaryOp()
2226 DCHECK_NE(rd, rs2); // Requested `Location::kOutputOverlap`. in HandleBinaryOp()
2237 FClass(tmp, rs2, type); in HandleBinaryOp()
2238 FMv(rd, rs2, type); in HandleBinaryOp()
2242 FMin(rd, rs1, rs2, type); in HandleBinaryOp()
2244 FMax(rd, rs1, rs2, type); in HandleBinaryOp()
2400 XRegister rs2 = rs2_location.AsRegister<XRegister>(); in HandleShift() local
2403 __ Sllw(rd, rs1, rs2); in HandleShift()
2405 __ Sraw(rd, rs1, rs2); in HandleShift()
2407 __ Srlw(rd, rs1, rs2); in HandleShift()
2410 __ Rorw(rd, rs1, rs2); in HandleShift()
2414 __ Sll(rd, rs1, rs2); in HandleShift()
2416 __ Sra(rd, rs1, rs2); in HandleShift()
2418 __ Srl(rd, rs1, rs2); in HandleShift()
2421 __ Ror(rd, rs1, rs2); in HandleShift()