Lines Matching refs:rs2
116 void Riscv64Assembler::Beq(XRegister rs1, XRegister rs2, int32_t offset) { in Beq() argument
118 if (rs2 == Zero && IsShortReg(rs1) && IsInt<9>(offset)) { in Beq()
121 } else if (rs1 == Zero && IsShortReg(rs2) && IsInt<9>(offset)) { in Beq()
122 CBeqz(rs2, offset); in Beq()
127 EmitB(offset, rs2, rs1, 0x0, 0x63); in Beq()
130 void Riscv64Assembler::Bne(XRegister rs1, XRegister rs2, int32_t offset) { in Bne() argument
132 if (rs2 == Zero && IsShortReg(rs1) && IsInt<9>(offset)) { in Bne()
135 } else if (rs1 == Zero && IsShortReg(rs2) && IsInt<9>(offset)) { in Bne()
136 CBnez(rs2, offset); in Bne()
141 EmitB(offset, rs2, rs1, 0x1, 0x63); in Bne()
144 void Riscv64Assembler::Blt(XRegister rs1, XRegister rs2, int32_t offset) { in Blt() argument
145 EmitB(offset, rs2, rs1, 0x4, 0x63); in Blt()
148 void Riscv64Assembler::Bge(XRegister rs1, XRegister rs2, int32_t offset) { in Bge() argument
149 EmitB(offset, rs2, rs1, 0x5, 0x63); in Bge()
152 void Riscv64Assembler::Bltu(XRegister rs1, XRegister rs2, int32_t offset) { in Bltu() argument
153 EmitB(offset, rs2, rs1, 0x6, 0x63); in Bltu()
156 void Riscv64Assembler::Bgeu(XRegister rs1, XRegister rs2, int32_t offset) { in Bgeu() argument
157 EmitB(offset, rs2, rs1, 0x7, 0x63); in Bgeu()
245 void Riscv64Assembler::Sb(XRegister rs2, XRegister rs1, int32_t offset) { in Sb() argument
249 if (IsShortReg(rs2) && IsShortReg(rs1) && IsUint<2>(offset)) { in Sb()
250 CSb(rs2, rs1, offset); in Sb()
255 EmitS(offset, rs2, rs1, 0x0, 0x23); in Sb()
258 void Riscv64Assembler::Sh(XRegister rs2, XRegister rs1, int32_t offset) { in Sh() argument
262 if (IsShortReg(rs2) && IsShortReg(rs1) && IsUint<2>(offset) && IsAligned<2>(offset)) { in Sh()
263 CSh(rs2, rs1, offset); in Sh()
268 EmitS(offset, rs2, rs1, 0x1, 0x23); in Sh()
271 void Riscv64Assembler::Sw(XRegister rs2, XRegister rs1, int32_t offset) { in Sw() argument
276 CSwsp(rs2, offset); in Sw()
278 } else if (IsShortReg(rs2) && IsShortReg(rs1) && IsUint<7>(offset) && IsAligned<4>(offset)) { in Sw()
279 CSw(rs2, rs1, offset); in Sw()
284 EmitS(offset, rs2, rs1, 0x2, 0x23); in Sw()
287 void Riscv64Assembler::Sd(XRegister rs2, XRegister rs1, int32_t offset) { in Sd() argument
292 CSdsp(rs2, offset); in Sd()
294 } else if (IsShortReg(rs2) && IsShortReg(rs1) && IsUint<8>(offset) && IsAligned<8>(offset)) { in Sd()
295 CSd(rs2, rs1, offset); in Sd()
300 EmitS(offset, rs2, rs1, 0x3, 0x23); in Sd()
417 void Riscv64Assembler::Add(XRegister rd, XRegister rs1, XRegister rs2) { in Add() argument
420 if (rs1 != Zero || rs2 != Zero) { in Add()
422 DCHECK_NE(rs2, Zero); in Add()
423 CMv(rd, rs2); in Add()
425 } else if (rs2 == Zero) { in Add()
430 DCHECK_NE(rs2, Zero); in Add()
431 CAdd(rd, rs2); in Add()
433 } else if (rd == rs2) { in Add()
449 EmitR(0x0, rs2, rs1, 0x0, rd, 0x33); in Add()
452 void Riscv64Assembler::Sub(XRegister rd, XRegister rs1, XRegister rs2) { in Sub() argument
454 if (rd == rs1 && IsShortReg(rd) && IsShortReg(rs2)) { in Sub()
455 CSub(rd, rs2); in Sub()
460 EmitR(0x20, rs2, rs1, 0x0, rd, 0x33); in Sub()
463 void Riscv64Assembler::Slt(XRegister rd, XRegister rs1, XRegister rs2) { in Slt() argument
464 EmitR(0x0, rs2, rs1, 0x02, rd, 0x33); in Slt()
467 void Riscv64Assembler::Sltu(XRegister rd, XRegister rs1, XRegister rs2) { in Sltu() argument
468 EmitR(0x0, rs2, rs1, 0x03, rd, 0x33); in Sltu()
471 void Riscv64Assembler::Xor(XRegister rd, XRegister rs1, XRegister rs2) { in Xor() argument
474 if (rd == rs1 && IsShortReg(rs2)) { in Xor()
475 CXor(rd, rs2); in Xor()
477 } else if (rd == rs2 && IsShortReg(rs1)) { in Xor()
484 EmitR(0x0, rs2, rs1, 0x04, rd, 0x33); in Xor()
487 void Riscv64Assembler::Or(XRegister rd, XRegister rs1, XRegister rs2) { in Or() argument
490 if (rd == rs1 && IsShortReg(rs2)) { in Or()
491 COr(rd, rs2); in Or()
493 } else if (rd == rs2 && IsShortReg(rs1)) { in Or()
500 EmitR(0x0, rs2, rs1, 0x06, rd, 0x33); in Or()
503 void Riscv64Assembler::And(XRegister rd, XRegister rs1, XRegister rs2) { in And() argument
506 if (rd == rs1 && IsShortReg(rs2)) { in And()
507 CAnd(rd, rs2); in And()
509 } else if (rd == rs2 && IsShortReg(rs1)) { in And()
516 EmitR(0x0, rs2, rs1, 0x07, rd, 0x33); in And()
519 void Riscv64Assembler::Sll(XRegister rd, XRegister rs1, XRegister rs2) { in Sll() argument
520 EmitR(0x0, rs2, rs1, 0x01, rd, 0x33); in Sll()
523 void Riscv64Assembler::Srl(XRegister rd, XRegister rs1, XRegister rs2) { in Srl() argument
524 EmitR(0x0, rs2, rs1, 0x05, rd, 0x33); in Srl()
527 void Riscv64Assembler::Sra(XRegister rd, XRegister rs1, XRegister rs2) { in Sra() argument
528 EmitR(0x20, rs2, rs1, 0x05, rd, 0x33); in Sra()
566 void Riscv64Assembler::Addw(XRegister rd, XRegister rs1, XRegister rs2) { in Addw() argument
569 if (rd == rs1 && IsShortReg(rs2)) { in Addw()
570 CAddw(rd, rs2); in Addw()
572 } else if (rd == rs2 && IsShortReg(rs1)) { in Addw()
579 EmitR(0x0, rs2, rs1, 0x0, rd, 0x3b); in Addw()
582 void Riscv64Assembler::Subw(XRegister rd, XRegister rs1, XRegister rs2) { in Subw() argument
584 if (rd == rs1 && IsShortReg(rd) && IsShortReg(rs2)) { in Subw()
585 CSubw(rd, rs2); in Subw()
590 EmitR(0x20, rs2, rs1, 0x0, rd, 0x3b); in Subw()
593 void Riscv64Assembler::Sllw(XRegister rd, XRegister rs1, XRegister rs2) { in Sllw() argument
594 EmitR(0x0, rs2, rs1, 0x1, rd, 0x3b); in Sllw()
597 void Riscv64Assembler::Srlw(XRegister rd, XRegister rs1, XRegister rs2) { in Srlw() argument
598 EmitR(0x0, rs2, rs1, 0x5, rd, 0x3b); in Srlw()
601 void Riscv64Assembler::Sraw(XRegister rd, XRegister rs1, XRegister rs2) { in Sraw() argument
602 EmitR(0x20, rs2, rs1, 0x5, rd, 0x3b); in Sraw()
648 void Riscv64Assembler::Mul(XRegister rd, XRegister rs1, XRegister rs2) { in Mul() argument
653 if (rd == rs1 && IsShortReg(rs2)) { in Mul()
654 CMul(rd, rs2); in Mul()
656 } else if (rd == rs2 && IsShortReg(rs1)) { in Mul()
663 EmitR(0x1, rs2, rs1, 0x0, rd, 0x33); in Mul()
666 void Riscv64Assembler::Mulh(XRegister rd, XRegister rs1, XRegister rs2) { in Mulh() argument
668 EmitR(0x1, rs2, rs1, 0x1, rd, 0x33); in Mulh()
671 void Riscv64Assembler::Mulhsu(XRegister rd, XRegister rs1, XRegister rs2) { in Mulhsu() argument
673 EmitR(0x1, rs2, rs1, 0x2, rd, 0x33); in Mulhsu()
676 void Riscv64Assembler::Mulhu(XRegister rd, XRegister rs1, XRegister rs2) { in Mulhu() argument
678 EmitR(0x1, rs2, rs1, 0x3, rd, 0x33); in Mulhu()
681 void Riscv64Assembler::Div(XRegister rd, XRegister rs1, XRegister rs2) { in Div() argument
683 EmitR(0x1, rs2, rs1, 0x4, rd, 0x33); in Div()
686 void Riscv64Assembler::Divu(XRegister rd, XRegister rs1, XRegister rs2) { in Divu() argument
688 EmitR(0x1, rs2, rs1, 0x5, rd, 0x33); in Divu()
691 void Riscv64Assembler::Rem(XRegister rd, XRegister rs1, XRegister rs2) { in Rem() argument
693 EmitR(0x1, rs2, rs1, 0x6, rd, 0x33); in Rem()
696 void Riscv64Assembler::Remu(XRegister rd, XRegister rs1, XRegister rs2) { in Remu() argument
698 EmitR(0x1, rs2, rs1, 0x7, rd, 0x33); in Remu()
703 void Riscv64Assembler::Mulw(XRegister rd, XRegister rs1, XRegister rs2) { in Mulw() argument
705 EmitR(0x1, rs2, rs1, 0x0, rd, 0x3b); in Mulw()
708 void Riscv64Assembler::Divw(XRegister rd, XRegister rs1, XRegister rs2) { in Divw() argument
710 EmitR(0x1, rs2, rs1, 0x4, rd, 0x3b); in Divw()
713 void Riscv64Assembler::Divuw(XRegister rd, XRegister rs1, XRegister rs2) { in Divuw() argument
715 EmitR(0x1, rs2, rs1, 0x5, rd, 0x3b); in Divuw()
718 void Riscv64Assembler::Remw(XRegister rd, XRegister rs1, XRegister rs2) { in Remw() argument
720 EmitR(0x1, rs2, rs1, 0x6, rd, 0x3b); in Remw()
723 void Riscv64Assembler::Remuw(XRegister rd, XRegister rs1, XRegister rs2) { in Remuw() argument
725 EmitR(0x1, rs2, rs1, 0x7, rd, 0x3b); in Remuw()
744 void Riscv64Assembler::ScW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in ScW() argument
747 EmitR4(0x3, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f); in ScW()
750 void Riscv64Assembler::ScD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in ScD() argument
753 EmitR4(0x3, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f); in ScD()
756 void Riscv64Assembler::AmoSwapW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoSwapW() argument
758 EmitR4(0x1, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f); in AmoSwapW()
761 void Riscv64Assembler::AmoSwapD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoSwapD() argument
763 EmitR4(0x1, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f); in AmoSwapD()
766 void Riscv64Assembler::AmoAddW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoAddW() argument
768 EmitR4(0x0, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f); in AmoAddW()
771 void Riscv64Assembler::AmoAddD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoAddD() argument
773 EmitR4(0x0, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f); in AmoAddD()
776 void Riscv64Assembler::AmoXorW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoXorW() argument
778 EmitR4(0x4, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f); in AmoXorW()
781 void Riscv64Assembler::AmoXorD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoXorD() argument
783 EmitR4(0x4, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f); in AmoXorD()
786 void Riscv64Assembler::AmoAndW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoAndW() argument
788 EmitR4(0xc, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f); in AmoAndW()
791 void Riscv64Assembler::AmoAndD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoAndD() argument
793 EmitR4(0xc, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f); in AmoAndD()
796 void Riscv64Assembler::AmoOrW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoOrW() argument
798 EmitR4(0x8, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f); in AmoOrW()
801 void Riscv64Assembler::AmoOrD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoOrD() argument
803 EmitR4(0x8, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f); in AmoOrD()
806 void Riscv64Assembler::AmoMinW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoMinW() argument
808 EmitR4(0x10, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f); in AmoMinW()
811 void Riscv64Assembler::AmoMinD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoMinD() argument
813 EmitR4(0x10, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f); in AmoMinD()
816 void Riscv64Assembler::AmoMaxW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoMaxW() argument
818 EmitR4(0x14, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f); in AmoMaxW()
821 void Riscv64Assembler::AmoMaxD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoMaxD() argument
823 EmitR4(0x14, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f); in AmoMaxD()
826 void Riscv64Assembler::AmoMinuW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoMinuW() argument
828 EmitR4(0x18, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f); in AmoMinuW()
831 void Riscv64Assembler::AmoMinuD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoMinuD() argument
833 EmitR4(0x18, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f); in AmoMinuD()
836 void Riscv64Assembler::AmoMaxuW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoMaxuW() argument
838 EmitR4(0x1c, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f); in AmoMaxuW()
841 void Riscv64Assembler::AmoMaxuD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) { in AmoMaxuD() argument
843 EmitR4(0x1c, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f); in AmoMaxuD()
909 void Riscv64Assembler::FSw(FRegister rs2, XRegister rs1, int32_t offset) { in FSw() argument
911 EmitS(offset, rs2, rs1, 0x2, 0x27); in FSw()
914 void Riscv64Assembler::FSd(FRegister rs2, XRegister rs1, int32_t offset) { in FSd() argument
919 CFSdsp(rs2, offset); in FSd()
921 } else if (IsShortReg(rs2) && IsShortReg(rs1) && IsUint<8>(offset) && IsAligned<8>(offset)) { in FSd()
922 CFSd(rs2, rs1, offset); in FSd()
927 EmitS(offset, rs2, rs1, 0x3, 0x27); in FSd()
933 FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) { in FMAddS() argument
935 EmitR4(rs3, 0x0, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x43); in FMAddS()
939 FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) { in FMAddD() argument
941 EmitR4(rs3, 0x1, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x43); in FMAddD()
945 FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) { in FMSubS() argument
947 EmitR4(rs3, 0x0, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x47); in FMSubS()
951 FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) { in FMSubD() argument
953 EmitR4(rs3, 0x1, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x47); in FMSubD()
957 FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) { in FNMSubS() argument
959 EmitR4(rs3, 0x0, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x4b); in FNMSubS()
963 FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) { in FNMSubD() argument
965 EmitR4(rs3, 0x1, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x4b); in FNMSubD()
969 FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) { in FNMAddS() argument
971 EmitR4(rs3, 0x0, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x4f); in FNMAddS()
975 FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3, FPRoundingMode frm) { in FNMAddD() argument
977 EmitR4(rs3, 0x1, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x4f); in FNMAddD()
982 void Riscv64Assembler::FAddS(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) { in FAddS() argument
984 EmitR(0x0, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53); in FAddS()
987 void Riscv64Assembler::FAddD(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) { in FAddD() argument
989 EmitR(0x1, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53); in FAddD()
992 void Riscv64Assembler::FSubS(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) { in FSubS() argument
994 EmitR(0x4, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53); in FSubS()
997 void Riscv64Assembler::FSubD(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) { in FSubD() argument
999 EmitR(0x5, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53); in FSubD()
1002 void Riscv64Assembler::FMulS(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) { in FMulS() argument
1004 EmitR(0x8, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53); in FMulS()
1007 void Riscv64Assembler::FMulD(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) { in FMulD() argument
1009 EmitR(0x9, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53); in FMulD()
1012 void Riscv64Assembler::FDivS(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) { in FDivS() argument
1014 EmitR(0xc, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53); in FDivS()
1017 void Riscv64Assembler::FDivD(FRegister rd, FRegister rs1, FRegister rs2, FPRoundingMode frm) { in FDivD() argument
1019 EmitR(0xd, rs2, rs1, enum_cast<uint32_t>(frm), rd, 0x53); in FDivD()
1032 void Riscv64Assembler::FSgnjS(FRegister rd, FRegister rs1, FRegister rs2) { in FSgnjS() argument
1034 EmitR(0x10, rs2, rs1, 0x0, rd, 0x53); in FSgnjS()
1037 void Riscv64Assembler::FSgnjD(FRegister rd, FRegister rs1, FRegister rs2) { in FSgnjD() argument
1039 EmitR(0x11, rs2, rs1, 0x0, rd, 0x53); in FSgnjD()
1042 void Riscv64Assembler::FSgnjnS(FRegister rd, FRegister rs1, FRegister rs2) { in FSgnjnS() argument
1044 EmitR(0x10, rs2, rs1, 0x1, rd, 0x53); in FSgnjnS()
1047 void Riscv64Assembler::FSgnjnD(FRegister rd, FRegister rs1, FRegister rs2) { in FSgnjnD() argument
1049 EmitR(0x11, rs2, rs1, 0x1, rd, 0x53); in FSgnjnD()
1052 void Riscv64Assembler::FSgnjxS(FRegister rd, FRegister rs1, FRegister rs2) { in FSgnjxS() argument
1054 EmitR(0x10, rs2, rs1, 0x2, rd, 0x53); in FSgnjxS()
1057 void Riscv64Assembler::FSgnjxD(FRegister rd, FRegister rs1, FRegister rs2) { in FSgnjxD() argument
1059 EmitR(0x11, rs2, rs1, 0x2, rd, 0x53); in FSgnjxD()
1062 void Riscv64Assembler::FMinS(FRegister rd, FRegister rs1, FRegister rs2) { in FMinS() argument
1064 EmitR(0x14, rs2, rs1, 0x0, rd, 0x53); in FMinS()
1067 void Riscv64Assembler::FMinD(FRegister rd, FRegister rs1, FRegister rs2) { in FMinD() argument
1069 EmitR(0x15, rs2, rs1, 0x0, rd, 0x53); in FMinD()
1072 void Riscv64Assembler::FMaxS(FRegister rd, FRegister rs1, FRegister rs2) { in FMaxS() argument
1074 EmitR(0x14, rs2, rs1, 0x1, rd, 0x53); in FMaxS()
1077 void Riscv64Assembler::FMaxD(FRegister rd, FRegister rs1, FRegister rs2) { in FMaxD() argument
1078 EmitR(0x15, rs2, rs1, 0x1, rd, 0x53); in FMaxD()
1095 void Riscv64Assembler::FEqS(XRegister rd, FRegister rs1, FRegister rs2) { in FEqS() argument
1097 EmitR(0x50, rs2, rs1, 0x2, rd, 0x53); in FEqS()
1100 void Riscv64Assembler::FEqD(XRegister rd, FRegister rs1, FRegister rs2) { in FEqD() argument
1102 EmitR(0x51, rs2, rs1, 0x2, rd, 0x53); in FEqD()
1105 void Riscv64Assembler::FLtS(XRegister rd, FRegister rs1, FRegister rs2) { in FLtS() argument
1107 EmitR(0x50, rs2, rs1, 0x1, rd, 0x53); in FLtS()
1110 void Riscv64Assembler::FLtD(XRegister rd, FRegister rs1, FRegister rs2) { in FLtD() argument
1112 EmitR(0x51, rs2, rs1, 0x1, rd, 0x53); in FLtD()
1115 void Riscv64Assembler::FLeS(XRegister rd, FRegister rs1, FRegister rs2) { in FLeS() argument
1117 EmitR(0x50, rs2, rs1, 0x0, rd, 0x53); in FLeS()
1120 void Riscv64Assembler::FLeD(XRegister rd, FRegister rs1, FRegister rs2) { in FLeD() argument
1122 EmitR(0x51, rs2, rs1, 0x0, rd, 0x53); in FLeD()
1265 void Riscv64Assembler::CSwsp(XRegister rs2, int32_t offset) { in CSwsp() argument
1267 EmitCSS(0b110u, ExtractOffset52_76(offset), rs2, 0b10u); in CSwsp()
1270 void Riscv64Assembler::CSdsp(XRegister rs2, int32_t offset) { in CSdsp() argument
1272 EmitCSS(0b111u, ExtractOffset53_86(offset), rs2, 0b10u); in CSdsp()
1275 void Riscv64Assembler::CFSdsp(FRegister rs2, int32_t offset) { in CFSdsp() argument
1278 EmitCSS(0b101u, ExtractOffset53_86(offset), rs2, 0b10u); in CFSdsp()
1402 void Riscv64Assembler::CMv(XRegister rd, XRegister rs2) { in CMv() argument
1405 DCHECK_NE(rs2, Zero); in CMv()
1406 EmitCR(0b1000u, rd, rs2, 0b10u); in CMv()
1409 void Riscv64Assembler::CAdd(XRegister rd, XRegister rs2) { in CAdd() argument
1412 DCHECK_NE(rs2, Zero); in CAdd()
1413 EmitCR(0b1001u, rd, rs2, 0b10u); in CAdd()
1560 void Riscv64Assembler::AddUw(XRegister rd, XRegister rs1, XRegister rs2) { in AddUw() argument
1562 EmitR(0x4, rs2, rs1, 0x0, rd, 0x3b); in AddUw()
1565 void Riscv64Assembler::Sh1Add(XRegister rd, XRegister rs1, XRegister rs2) { in Sh1Add() argument
1567 EmitR(0x10, rs2, rs1, 0x2, rd, 0x33); in Sh1Add()
1570 void Riscv64Assembler::Sh1AddUw(XRegister rd, XRegister rs1, XRegister rs2) { in Sh1AddUw() argument
1572 EmitR(0x10, rs2, rs1, 0x2, rd, 0x3b); in Sh1AddUw()
1575 void Riscv64Assembler::Sh2Add(XRegister rd, XRegister rs1, XRegister rs2) { in Sh2Add() argument
1577 EmitR(0x10, rs2, rs1, 0x4, rd, 0x33); in Sh2Add()
1580 void Riscv64Assembler::Sh2AddUw(XRegister rd, XRegister rs1, XRegister rs2) { in Sh2AddUw() argument
1582 EmitR(0x10, rs2, rs1, 0x4, rd, 0x3b); in Sh2AddUw()
1585 void Riscv64Assembler::Sh3Add(XRegister rd, XRegister rs1, XRegister rs2) { in Sh3Add() argument
1587 EmitR(0x10, rs2, rs1, 0x6, rd, 0x33); in Sh3Add()
1590 void Riscv64Assembler::Sh3AddUw(XRegister rd, XRegister rs1, XRegister rs2) { in Sh3AddUw() argument
1592 EmitR(0x10, rs2, rs1, 0x6, rd, 0x3b); in Sh3AddUw()
1604 void Riscv64Assembler::Andn(XRegister rd, XRegister rs1, XRegister rs2) { in Andn() argument
1606 EmitR(0x20, rs2, rs1, 0x7, rd, 0x33); in Andn()
1609 void Riscv64Assembler::Orn(XRegister rd, XRegister rs1, XRegister rs2) { in Orn() argument
1611 EmitR(0x20, rs2, rs1, 0x6, rd, 0x33); in Orn()
1614 void Riscv64Assembler::Xnor(XRegister rd, XRegister rs1, XRegister rs2) { in Xnor() argument
1616 EmitR(0x20, rs2, rs1, 0x4, rd, 0x33); in Xnor()
1649 void Riscv64Assembler::Min(XRegister rd, XRegister rs1, XRegister rs2) { in Min() argument
1651 EmitR(0x5, rs2, rs1, 0x4, rd, 0x33); in Min()
1654 void Riscv64Assembler::Minu(XRegister rd, XRegister rs1, XRegister rs2) { in Minu() argument
1656 EmitR(0x5, rs2, rs1, 0x5, rd, 0x33); in Minu()
1659 void Riscv64Assembler::Max(XRegister rd, XRegister rs1, XRegister rs2) { in Max() argument
1661 EmitR(0x5, rs2, rs1, 0x6, rd, 0x33); in Max()
1664 void Riscv64Assembler::Maxu(XRegister rd, XRegister rs1, XRegister rs2) { in Maxu() argument
1666 EmitR(0x5, rs2, rs1, 0x7, rd, 0x33); in Maxu()
1669 void Riscv64Assembler::Rol(XRegister rd, XRegister rs1, XRegister rs2) { in Rol() argument
1671 EmitR(0x30, rs2, rs1, 0x1, rd, 0x33); in Rol()
1674 void Riscv64Assembler::Rolw(XRegister rd, XRegister rs1, XRegister rs2) { in Rolw() argument
1676 EmitR(0x30, rs2, rs1, 0x1, rd, 0x3b); in Rolw()
1679 void Riscv64Assembler::Ror(XRegister rd, XRegister rs1, XRegister rs2) { in Ror() argument
1681 EmitR(0x30, rs2, rs1, 0x5, rd, 0x33); in Ror()
1684 void Riscv64Assembler::Rorw(XRegister rd, XRegister rs1, XRegister rs2) { in Rorw() argument
1686 EmitR(0x30, rs2, rs1, 0x5, rd, 0x3b); in Rorw()
1743 void Riscv64Assembler::VSetvl(XRegister rd, XRegister rs1, XRegister rs2) { in VSetvl() argument
1745 EmitR(0x40, rs2, rs1, enum_cast<uint32_t>(VAIEncoding::kOPCFG), rd, 0x57); in VSetvl()
1840 void Riscv64Assembler::VLse8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLse8() argument
1844 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7); in VLse8()
1847 void Riscv64Assembler::VLse16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLse16() argument
1851 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7); in VLse16()
1854 void Riscv64Assembler::VLse32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLse32() argument
1858 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7); in VLse32()
1861 void Riscv64Assembler::VLse64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLse64() argument
1865 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7); in VLse64()
1868 void Riscv64Assembler::VSse8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSse8() argument
1871 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27); in VSse8()
1874 void Riscv64Assembler::VSse16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSse16() argument
1877 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27); in VSse16()
1880 void Riscv64Assembler::VSse32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSse32() argument
1883 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27); in VSse32()
1886 void Riscv64Assembler::VSse64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSse64() argument
1889 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27); in VSse64()
2556 void Riscv64Assembler::VLsseg2e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg2e8() argument
2560 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7); in VLsseg2e8()
2563 void Riscv64Assembler::VLsseg2e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg2e16() argument
2567 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7); in VLsseg2e16()
2570 void Riscv64Assembler::VLsseg2e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg2e32() argument
2574 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7); in VLsseg2e32()
2577 void Riscv64Assembler::VLsseg2e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg2e64() argument
2581 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7); in VLsseg2e64()
2584 void Riscv64Assembler::VLsseg3e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg3e8() argument
2588 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7); in VLsseg3e8()
2591 void Riscv64Assembler::VLsseg3e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg3e16() argument
2595 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7); in VLsseg3e16()
2598 void Riscv64Assembler::VLsseg3e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg3e32() argument
2602 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7); in VLsseg3e32()
2605 void Riscv64Assembler::VLsseg3e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg3e64() argument
2609 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7); in VLsseg3e64()
2612 void Riscv64Assembler::VLsseg4e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg4e8() argument
2616 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7); in VLsseg4e8()
2619 void Riscv64Assembler::VLsseg4e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg4e16() argument
2623 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7); in VLsseg4e16()
2626 void Riscv64Assembler::VLsseg4e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg4e32() argument
2630 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7); in VLsseg4e32()
2633 void Riscv64Assembler::VLsseg4e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg4e64() argument
2637 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7); in VLsseg4e64()
2640 void Riscv64Assembler::VLsseg5e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg5e8() argument
2644 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7); in VLsseg5e8()
2647 void Riscv64Assembler::VLsseg5e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg5e16() argument
2651 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7); in VLsseg5e16()
2654 void Riscv64Assembler::VLsseg5e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg5e32() argument
2658 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7); in VLsseg5e32()
2661 void Riscv64Assembler::VLsseg5e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg5e64() argument
2665 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7); in VLsseg5e64()
2668 void Riscv64Assembler::VLsseg6e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg6e8() argument
2672 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7); in VLsseg6e8()
2675 void Riscv64Assembler::VLsseg6e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg6e16() argument
2679 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7); in VLsseg6e16()
2682 void Riscv64Assembler::VLsseg6e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg6e32() argument
2686 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7); in VLsseg6e32()
2689 void Riscv64Assembler::VLsseg6e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg6e64() argument
2693 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7); in VLsseg6e64()
2696 void Riscv64Assembler::VLsseg7e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg7e8() argument
2700 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7); in VLsseg7e8()
2703 void Riscv64Assembler::VLsseg7e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg7e16() argument
2707 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7); in VLsseg7e16()
2710 void Riscv64Assembler::VLsseg7e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg7e32() argument
2714 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7); in VLsseg7e32()
2717 void Riscv64Assembler::VLsseg7e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg7e64() argument
2721 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7); in VLsseg7e64()
2724 void Riscv64Assembler::VLsseg8e8(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg8e8() argument
2728 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vd, 0x7); in VLsseg8e8()
2731 void Riscv64Assembler::VLsseg8e16(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg8e16() argument
2735 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vd, 0x7); in VLsseg8e16()
2738 void Riscv64Assembler::VLsseg8e32(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg8e32() argument
2742 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vd, 0x7); in VLsseg8e32()
2745 void Riscv64Assembler::VLsseg8e64(VRegister vd, XRegister rs1, XRegister rs2, VM vm) { in VLsseg8e64() argument
2749 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vd, 0x7); in VLsseg8e64()
2752 void Riscv64Assembler::VSsseg2e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg2e8() argument
2755 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27); in VSsseg2e8()
2758 void Riscv64Assembler::VSsseg2e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg2e16() argument
2761 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27); in VSsseg2e16()
2764 void Riscv64Assembler::VSsseg2e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg2e32() argument
2767 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27); in VSsseg2e32()
2770 void Riscv64Assembler::VSsseg2e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg2e64() argument
2773 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27); in VSsseg2e64()
2776 void Riscv64Assembler::VSsseg3e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg3e8() argument
2779 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27); in VSsseg3e8()
2782 void Riscv64Assembler::VSsseg3e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg3e16() argument
2785 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27); in VSsseg3e16()
2788 void Riscv64Assembler::VSsseg3e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg3e32() argument
2791 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27); in VSsseg3e32()
2794 void Riscv64Assembler::VSsseg3e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg3e64() argument
2797 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27); in VSsseg3e64()
2800 void Riscv64Assembler::VSsseg4e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg4e8() argument
2803 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27); in VSsseg4e8()
2806 void Riscv64Assembler::VSsseg4e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg4e16() argument
2809 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27); in VSsseg4e16()
2812 void Riscv64Assembler::VSsseg4e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg4e32() argument
2815 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27); in VSsseg4e32()
2818 void Riscv64Assembler::VSsseg4e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg4e64() argument
2821 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27); in VSsseg4e64()
2824 void Riscv64Assembler::VSsseg5e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg5e8() argument
2827 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27); in VSsseg5e8()
2830 void Riscv64Assembler::VSsseg5e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg5e16() argument
2833 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27); in VSsseg5e16()
2836 void Riscv64Assembler::VSsseg5e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg5e32() argument
2839 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27); in VSsseg5e32()
2842 void Riscv64Assembler::VSsseg5e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg5e64() argument
2845 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27); in VSsseg5e64()
2848 void Riscv64Assembler::VSsseg6e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg6e8() argument
2851 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27); in VSsseg6e8()
2854 void Riscv64Assembler::VSsseg6e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg6e16() argument
2857 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27); in VSsseg6e16()
2860 void Riscv64Assembler::VSsseg6e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg6e32() argument
2863 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27); in VSsseg6e32()
2866 void Riscv64Assembler::VSsseg6e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg6e64() argument
2869 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27); in VSsseg6e64()
2872 void Riscv64Assembler::VSsseg7e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg7e8() argument
2875 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27); in VSsseg7e8()
2878 void Riscv64Assembler::VSsseg7e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg7e16() argument
2881 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27); in VSsseg7e16()
2884 void Riscv64Assembler::VSsseg7e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg7e32() argument
2887 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27); in VSsseg7e32()
2890 void Riscv64Assembler::VSsseg7e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg7e64() argument
2893 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27); in VSsseg7e64()
2896 void Riscv64Assembler::VSsseg8e8(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg8e8() argument
2899 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k8), vs3, 0x27); in VSsseg8e8()
2902 void Riscv64Assembler::VSsseg8e16(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg8e16() argument
2905 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k16), vs3, 0x27); in VSsseg8e16()
2908 void Riscv64Assembler::VSsseg8e32(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg8e32() argument
2911 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k32), vs3, 0x27); in VSsseg8e32()
2914 void Riscv64Assembler::VSsseg8e64(VRegister vs3, XRegister rs1, XRegister rs2, VM vm) { in VSsseg8e64() argument
2917 EmitR(funct7, rs2, rs1, enum_cast<uint32_t>(VectorWidth::k64), vs3, 0x27); in VSsseg8e64()
6339 void Riscv64Assembler::Storeb(XRegister rs2, XRegister rs1, int32_t offset) { in Storeb() argument
6340 StoreToOffset<&Riscv64Assembler::Sb>(rs2, rs1, offset); in Storeb()
6343 void Riscv64Assembler::Storeh(XRegister rs2, XRegister rs1, int32_t offset) { in Storeh() argument
6344 StoreToOffset<&Riscv64Assembler::Sh>(rs2, rs1, offset); in Storeh()
6347 void Riscv64Assembler::Storew(XRegister rs2, XRegister rs1, int32_t offset) { in Storew() argument
6348 StoreToOffset<&Riscv64Assembler::Sw>(rs2, rs1, offset); in Storew()
6351 void Riscv64Assembler::Stored(XRegister rs2, XRegister rs1, int32_t offset) { in Stored() argument
6352 StoreToOffset<&Riscv64Assembler::Sd>(rs2, rs1, offset); in Stored()
6363 void Riscv64Assembler::FStorew(FRegister rs2, XRegister rs1, int32_t offset) { in FStorew() argument
6364 FStoreToOffset<&Riscv64Assembler::FSw>(rs2, rs1, offset); in FStorew()
6367 void Riscv64Assembler::FStored(FRegister rs2, XRegister rs1, int32_t offset) { in FStored() argument
6368 FStoreToOffset<&Riscv64Assembler::FSd>(rs2, rs1, offset); in FStored()
7610 void Riscv64Assembler::StoreToOffset(XRegister rs2, XRegister rs1, int32_t offset) { in StoreToOffset() argument
7612 CHECK_EQ((1u << rs2) & available_scratch_core_registers_, 0u); in StoreToOffset()
7615 (this->*insn)(rs2, rs1, offset); in StoreToOffset()
7627 void Riscv64Assembler::FStoreToOffset(FRegister rs2, XRegister rs1, int32_t offset) { in FStoreToOffset() argument
7631 (this->*insn)(rs2, rs1, offset); in FStoreToOffset()