Lines Matching +full:- +full:- +full:unified

6 		 * Cortex-A5 Technical Reference Manual:
11 		 *   Misses from the instruction and data micro TLBs are handled by a unified main TLB.
12 		 *   The main TLB is 128-entry two-way set-associative.
17 		 * Cortex-A7 MPCore Technical Reference Manual:
22 		 *   Misses from the micro TLBs are handled by a unified main TLB. This is a 256-entry 2-way
23 		 *   set-associative structure. The main TLB supports all the VMSAv7 page sizes of
29 		 * Cortex-A8 Technical Reference Manual:
32 		 *     - separate, fully-associative, 32-entry data and instruction TLBs
33 		 *     - TLB entries that support 4KB, 64KB, 1MB, and 16MB pages
44 		 *     - A fully-associative, lockable array of four elements.
45 		 *     - A 2-way associative structure of 2x32, 2x64, 2x128 or 2x256 entries.
50 		 * ARM Cortex-A15 MPCore Processor Technical Reference Manual:
52 …*    The L1 instruction TLB is a 32-entry fully-associative structure. This TLB caches entries at …
57 …*    There are two separate 32-entry fully-associative TLBs that are used for data loads and store…
59 …*    VA to PA mappings only. At implementation time, the Cortex-A15 MPCore processor can be config…
60 …*    the -l1tlb_1m option, to have the L1 data TLB cache entries at both the 4KB and 1MB granulari…
65 …es from the L1 instruction and data TLBs are handled by a unified L2 TLB. This is a 512-entry 4-way
66 …*    set-associative structure. The L2 TLB supports all the VMSAv7 page sizes of 4K, 64K, 1MB and …
72 		 * ARM Cortex-A17 MPCore Processor Technical Reference Manual:
74 …*    The instruction micro TLB is implemented as a 32, 48 or 64 entry, fully-associative structure…
79 …*    The data micro TLB is a 32 entry fully-associative TLB that is used for data loads and stores…
81 		 * 5.2.3. Unified main TLB
82 …*    Misses from the instruction and data micro TLBs are handled by a unified main TLB. This is a …
83 …*    4-way set-associative structure. The main TLB supports all the VMSAv7 page sizes of 4K, 64K, …
95 …*     A unified main TLB handles misses from the micro TLBs. It has a 512-entry, 2-way, set-associ…
102 		 * ARM Cortex-A53 MPCore Processor Technical Reference Manual:
107 …*    A unified main TLB handles misses from the micro TLBs. This is a 512-entry, 4-way, set-associ…
114 		 * ARM® Cortex-A57 MPCore Processor Technical Reference Manual:
116 …*    The L1 instruction TLB is a 48-entry fully-associative structure. This TLB caches entries of …
121 …*    The L1 data TLB is a 32-entry fully-associative TLB that is used for data loads and stores. T…
124 …s from the L1 instruction and data TLBs are handled by a unified L2 TLB. This is a 1024-entry 4-way
125 …*    set-associative structure. The L2 TLB supports the page sizes of 4K, 64K, 1MB and 16MB. It al…