Lines Matching full:micro
7 * 6.3.1. Micro TLB
8 * The first level of caching for the page table information is a micro TLB of
11 * Misses from the instruction and data micro TLBs are handled by a unified main TLB.
18 * 5.3.1. Micro TLB
19 * The first level of caching for the page table information is a micro TLB of
22 * Misses from the micro TLBs are handled by a unified main TLB. This is a 256-entry 2-way
39 * 6.2.1 Micro TLB
40 …* The first level of caching for the page table information is a micro TLB of 32 entries on the…
73 * 5.2.1. Instruction micro TLB
74 …* The instruction micro TLB is implemented as a 32, 48 or 64 entry, fully-associative structure…
78 * 5.2.2. Data micro TLB
79 …* The data micro TLB is a 32 entry fully-associative TLB that is used for data loads and stores…
82 …* Misses from the instruction and data micro TLBs are handled by a unified main TLB. This is a …
91 * Micro TLB
92 …* The first level of caching for the translation table information is a micro TLB of ten entri…
95 …* A unified main TLB handles misses from the micro TLBs. It has a 512-entry, 2-way, set-associ…
103 * 5.2.1. Micro TLB
104 …* The first level of caching for the translation table information is a micro TLB of ten entrie…
107 …* A unified main TLB handles misses from the micro TLBs. This is a 512-entry, 4-way, set-associ…