Lines Matching +full:implicit +full:- +full:fall +full:- +full:through
1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
8 //===----------------------------------------------------------------------===//
21 // command-line option -verify-machineinstrs, or by defining the environment
24 //===----------------------------------------------------------------------===//
90 // Add Reg and any sub-registers to RV
110 // Regs defined in MBB and live out. Note that vregs passing through may
114 // Vregs that pass through MBB untouched. This set is disjoint from
118 // Vregs that must pass through MBB because they are needed by a successor
169 if (addRequired(I->first)) in addRequired()
174 // Live-out registers are either in regsLiveOut or vregsPassed.
188 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg); in isAllocatable()
304 for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(), in verifySlotIndexes()
305 E = Indexes->MBBIndexEnd(); I != E; ++I) { in verifySlotIndexes()
306 assert(!Last.isValid() || I->first > Last); in verifySlotIndexes()
307 Last = I->first; in verifySlotIndexes()
317 MRI->getNumVirtRegs()) { in verifyProperties()
327 this->MF = &MF; in verify()
338 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>(); in verify()
341 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>(); in verify()
342 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>(); in verify()
343 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>(); in verify()
359 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(), in verify()
360 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) { in verify()
361 if (MBBI->getParent() != &*MFI) { in verify()
368 if (InBundle && !MBBI->isBundledWithPred()) in verify()
372 if (!InBundle && MBBI->isBundledWithPred()) in verify()
378 if (!MBBI->isInsideBundle()) { in verify()
386 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { in verify()
401 InBundle = MBBI->isBundledWithSucc(); in verify()
406 report("BundledSucc flag set on last instruction in block", &MFI->back()); in verify()
430 LiveInts->print(errs()); in report()
432 MF->print(errs(), Indexes); in report()
435 << "- function: " << MF->getName() << "\n"; in report()
440 report(msg, MBB->getParent()); in report()
441 errs() << "- basic block: BB#" << MBB->getNumber() in report()
442 << ' ' << MBB->getName() in report()
445 errs() << " [" << Indexes->getMBBStartIdx(MBB) in report()
446 << ';' << Indexes->getMBBEndIdx(MBB) << ')'; in report()
452 report(msg, MI->getParent()); in report()
453 errs() << "- instruction: "; in report()
454 if (Indexes && Indexes->hasIndex(*MI)) in report()
455 errs() << Indexes->getInstructionIndex(*MI) << '\t'; in report()
456 MI->print(errs(), /*SkipOpers=*/true); in report()
463 report(msg, MO->getParent()); in report()
464 errs() << "- operand " << MONum << ": "; in report()
465 MO->print(errs(), TRI); in report()
470 errs() << "- at: " << Pos << '\n'; in report_context()
474 errs() << "- interval: " << LI << '\n'; in report_context()
480 errs() << "- register: " << PrintReg(Reg, TRI) << '\n'; in report_context()
486 errs() << "- segment: " << S << '\n'; in report_context()
490 errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n"; in report_context()
494 errs() << "- liverange: " << LR << '\n'; in report_context_liverange()
498 errs() << "- v. register: " << PrintReg(VReg, TRI) << '\n'; in report_context_vreg()
505 errs() << "- regunit: " << PrintRegUnit(VRegOrUnit, TRI) << '\n'; in report_context_vreg_regunit()
510 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n'; in report_context_lanemask()
517 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), in markReachable()
518 SuE = MBB->succ_end(); SuI != SuE; ++SuI) in markReachable()
525 regsReserved = MRI->getReservedRegs(); in visitMachineFunctionBefore()
527 // A sub-register of a reserved register is also reserved in visitMachineFunctionBefore()
532 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register"); in visitMachineFunctionBefore()
537 markReachable(&MF->front()); in visitMachineFunctionBefore()
555 MRI->verifyUseLists(); in visitMachineFunctionBefore()
574 if (MRI->isSSA()) { in visitMachineBasicBlockBefore()
575 // If this block has allocatable physical registers live-in, check that in visitMachineBasicBlockBefore()
577 for (const auto &LI : MBB->liveins()) { in visitMachineBasicBlockBefore()
578 if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() && in visitMachineBasicBlockBefore()
579 MBB->getIterator() != MBB->getParent()->begin()) { in visitMachineBasicBlockBefore()
580 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB); in visitMachineBasicBlockBefore()
587 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(), in visitMachineBasicBlockBefore()
588 E = MBB->succ_end(); I != E; ++I) { in visitMachineBasicBlockBefore()
589 if ((*I)->isEHPad()) in visitMachineBasicBlockBefore()
596 << (*I)->getNumber() << ".\n"; in visitMachineBasicBlockBefore()
601 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(), in visitMachineBasicBlockBefore()
602 E = MBB->pred_end(); I != E; ++I) { in visitMachineBasicBlockBefore()
608 << (*I)->getNumber() << ".\n"; in visitMachineBasicBlockBefore()
612 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo(); in visitMachineBasicBlockBefore()
613 const BasicBlock *BB = MBB->getBasicBlock(); in visitMachineBasicBlockBefore()
614 const Function *Fn = MF->getFunction(); in visitMachineBasicBlockBefore()
617 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj && in visitMachineBasicBlockBefore()
618 BB && isa<SwitchInst>(BB->getTerminator())) && in visitMachineBasicBlockBefore()
619 !isFuncletEHPersonality(classifyEHPersonality(Fn->getPersonalityFn()))) in visitMachineBasicBlockBefore()
625 if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB, in visitMachineBasicBlockBefore()
630 // Block falls through to its successor. in visitMachineBasicBlockBefore()
631 MachineFunction::const_iterator MBBI = MBB->getIterator(); in visitMachineBasicBlockBefore()
633 if (MBBI == MF->end()) { in visitMachineBasicBlockBefore()
635 // call or an unreachable, in which case it won't actually fall in visitMachineBasicBlockBefore()
637 } else if (MBB->succ_size() == LandingPadSuccs.size()) { in visitMachineBasicBlockBefore()
639 // call or an unreachable, in which case it won't actuall fall in visitMachineBasicBlockBefore()
641 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) { in visitMachineBasicBlockBefore()
642 report("MBB exits via unconditional fall-through but doesn't have " in visitMachineBasicBlockBefore()
644 } else if (!MBB->isSuccessor(&*MBBI)) { in visitMachineBasicBlockBefore()
645 report("MBB exits via unconditional fall-through but its successor " in visitMachineBasicBlockBefore()
648 if (!MBB->empty() && MBB->back().isBarrier() && in visitMachineBasicBlockBefore()
649 !TII->isPredicated(MBB->back())) { in visitMachineBasicBlockBefore()
650 report("MBB exits via unconditional fall-through but ends with a " in visitMachineBasicBlockBefore()
654 report("MBB exits via unconditional fall-through but has a condition!", in visitMachineBasicBlockBefore()
661 if (MBB->succ_size() != 1+LandingPadSuccs.size() && in visitMachineBasicBlockBefore()
662 (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 || in visitMachineBasicBlockBefore()
663 *MBB->succ_begin() != *LandingPadSuccs.begin())) { in visitMachineBasicBlockBefore()
666 } else if (!MBB->isSuccessor(TBB)) { in visitMachineBasicBlockBefore()
670 if (MBB->empty()) { in visitMachineBasicBlockBefore()
673 } else if (!MBB->back().isBarrier()) { in visitMachineBasicBlockBefore()
676 } else if (!MBB->back().isTerminator()) { in visitMachineBasicBlockBefore()
681 // Block conditionally branches somewhere, otherwise falls through. in visitMachineBasicBlockBefore()
682 MachineFunction::const_iterator MBBI = MBB->getIterator(); in visitMachineBasicBlockBefore()
684 if (MBBI == MF->end()) { in visitMachineBasicBlockBefore()
685 report("MBB conditionally falls through out of function!", MBB); in visitMachineBasicBlockBefore()
686 } else if (MBB->succ_size() == 1) { in visitMachineBasicBlockBefore()
689 report("MBB exits via conditional branch/fall-through but only has " in visitMachineBasicBlockBefore()
691 else if (TBB != *MBB->succ_begin()) in visitMachineBasicBlockBefore()
692 report("MBB exits via conditional branch/fall-through but the CFG " in visitMachineBasicBlockBefore()
694 } else if (MBB->succ_size() != 2) { in visitMachineBasicBlockBefore()
695 report("MBB exits via conditional branch/fall-through but doesn't have " in visitMachineBasicBlockBefore()
697 } else if (!matchPair(MBB->succ_begin(), TBB, &*MBBI)) { in visitMachineBasicBlockBefore()
698 report("MBB exits via conditional branch/fall-through but the CFG " in visitMachineBasicBlockBefore()
701 if (MBB->empty()) { in visitMachineBasicBlockBefore()
702 report("MBB exits via conditional branch/fall-through but doesn't " in visitMachineBasicBlockBefore()
704 } else if (MBB->back().isBarrier()) { in visitMachineBasicBlockBefore()
705 report("MBB exits via conditional branch/fall-through but ends with a " in visitMachineBasicBlockBefore()
707 } else if (!MBB->back().isTerminator()) { in visitMachineBasicBlockBefore()
708 report("MBB exits via conditional branch/fall-through but the branch " in visitMachineBasicBlockBefore()
714 if (MBB->succ_size() == 1) { in visitMachineBasicBlockBefore()
717 report("MBB exits via conditional branch/branch through but only has " in visitMachineBasicBlockBefore()
719 else if (TBB != *MBB->succ_begin()) in visitMachineBasicBlockBefore()
720 report("MBB exits via conditional branch/branch through but the CFG " in visitMachineBasicBlockBefore()
722 } else if (MBB->succ_size() != 2) { in visitMachineBasicBlockBefore()
725 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) { in visitMachineBasicBlockBefore()
729 if (MBB->empty()) { in visitMachineBasicBlockBefore()
732 } else if (!MBB->back().isBarrier()) { in visitMachineBasicBlockBefore()
735 } else if (!MBB->back().isTerminator()) { in visitMachineBasicBlockBefore()
749 for (const auto &LI : MBB->liveins()) { in visitMachineBasicBlockBefore()
751 report("MBB live-in list contains non-physical register", MBB); in visitMachineBasicBlockBefore()
760 const MachineFrameInfo *MFI = MF->getFrameInfo(); in visitMachineBasicBlockBefore()
762 BitVector PR = MFI->getPristineRegs(*MF); in visitMachineBasicBlockBefore()
773 lastIndex = Indexes->getMBBStartIdx(MBB); in visitMachineBasicBlockBefore()
777 // stand-alone unbundled instructions.
779 if (Indexes && Indexes->hasIndex(*MI)) { in visitMachineBundleBefore()
780 SlotIndex idx = Indexes->getInstructionIndex(*MI); in visitMachineBundleBefore()
788 // Ensure non-terminators don't follow terminators. in visitMachineBundleBefore()
791 if (MI->isTerminator() && !TII->isPredicated(*MI)) { in visitMachineBundleBefore()
795 report("Non-terminator instruction after the first terminator", MI); in visitMachineBundleBefore()
804 if (MI->getNumOperands() < 2) { in verifyInlineAsm()
808 if (!MI->getOperand(0).isSymbol()) in verifyInlineAsm()
810 if (!MI->getOperand(1).isImm()) in verifyInlineAsm()
815 if (!isUInt<6>(MI->getOperand(1).getImm())) in verifyInlineAsm()
816 report("Unknown asm flags", &MI->getOperand(1), 1); in verifyInlineAsm()
822 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) { in verifyInlineAsm()
823 const MachineOperand &MO = MI->getOperand(OpNo); in verifyInlineAsm()
824 // There may be implicit ops after the fixed operands. in verifyInlineAsm()
830 if (OpNo > MI->getNumOperands()) in verifyInlineAsm()
834 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata()) in verifyInlineAsm()
837 // All trailing operands must be implicit registers. in verifyInlineAsm()
838 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) { in verifyInlineAsm()
839 const MachineOperand &MO = MI->getOperand(OpNo); in verifyInlineAsm()
841 report("Expected implicit register after groups", &MO, OpNo); in verifyInlineAsm()
846 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineInstrBefore()
847 if (MI->getNumOperands() < MCID.getNumOperands()) { in visitMachineInstrBefore()
850 << MI->getNumOperands() << " given.\n"; in visitMachineInstrBefore()
854 if (MI->isInlineAsm()) in visitMachineInstrBefore()
858 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), in visitMachineInstrBefore()
859 E = MI->memoperands_end(); I != E; ++I) { in visitMachineInstrBefore()
860 if ((*I)->isLoad() && !MI->mayLoad()) in visitMachineInstrBefore()
862 if ((*I)->isStore() && !MI->mayStore()) in visitMachineInstrBefore()
869 bool mapped = !LiveInts->isNotInMIMap(*MI); in visitMachineInstrBefore()
870 if (MI->isDebugValue()) { in visitMachineInstrBefore()
873 } else if (MI->isInsideBundle()) { in visitMachineInstrBefore()
883 if (!TII->verifyInstruction(*MI, ErrorInfo)) in visitMachineInstrBefore()
889 const MachineInstr *MI = MO->getParent(); in visitMachineOperand()
890 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineOperand()
893 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0; in visitMachineOperand()
898 if (!MO->isReg()) in visitMachineOperand()
900 else if (!MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand()
902 else if (MO->isImplicit()) in visitMachineOperand()
903 report("Explicit definition marked as implicit", MO, MONum); in visitMachineOperand()
908 if (MO->isReg() && in visitMachineOperand()
909 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) { in visitMachineOperand()
910 if (MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand()
912 if (MO->isImplicit()) in visitMachineOperand()
913 report("Explicit operand marked as implicit", MO, MONum); in visitMachineOperand()
917 if (TiedTo != -1) { in visitMachineOperand()
918 if (!MO->isReg()) in visitMachineOperand()
920 else if (!MO->isTied()) in visitMachineOperand()
922 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum)) in visitMachineOperand()
924 } else if (MO->isReg() && MO->isTied()) in visitMachineOperand()
928 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg()) in visitMachineOperand()
929 report("Extra explicit operand on non-variadic instruction", MO, MONum); in visitMachineOperand()
932 switch (MO->getType()) { in visitMachineOperand()
934 const unsigned Reg = MO->getReg(); in visitMachineOperand()
937 if (MRI->tracksLiveness() && !MI->isDebugValue()) in visitMachineOperand()
941 if (MO->isTied()) { in visitMachineOperand()
942 unsigned OtherIdx = MI->findTiedOperandIdx(MONum); in visitMachineOperand()
943 const MachineOperand &OtherMO = MI->getOperand(OtherIdx); in visitMachineOperand()
948 if (MI->findTiedOperandIdx(OtherIdx) != MONum) in visitMachineOperand()
952 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO)) in visitMachineOperand()
957 report("Explicit def should be tied to implicit use", MO, MONum); in visitMachineOperand()
962 // Verify two-address constraints after leaving SSA form. in visitMachineOperand()
964 if (!MRI->isSSA() && MO->isUse() && in visitMachineOperand()
965 MI->isRegTiedToDefOperand(MONum, &DefIdx) && in visitMachineOperand()
966 Reg != MI->getOperand(DefIdx).getReg()) in visitMachineOperand()
967 report("Two-address instruction operands must be identical", MO, MONum); in visitMachineOperand()
970 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) { in visitMachineOperand()
971 unsigned SubIdx = MO->getSubReg(); in visitMachineOperand()
979 TII->getRegClass(MCID, MONum, TRI, *MF)) { in visitMachineOperand()
980 if (!DRC->contains(Reg)) { in visitMachineOperand()
982 errs() << TRI->getName(Reg) << " is not a " in visitMachineOperand()
983 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
988 const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg); in visitMachineOperand()
992 unsigned Size = MRI->getSize(Reg); in visitMachineOperand()
998 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg); in visitMachineOperand()
999 if (RegBank && RegBank->getSize() < Size) { in visitMachineOperand()
1002 errs() << "Register bank " << RegBank->getName() << " too small(" in visitMachineOperand()
1003 << RegBank->getSize() << ") to fit " << Size << "-bits\n"; in visitMachineOperand()
1014 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()
1017 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
1023 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
1029 TII->getRegClass(MCID, MONum, TRI, *MF)) { in visitMachineOperand()
1032 TRI->getLargestLegalSuperClass(RC, *MF); in visitMachineOperand()
1037 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
1039 report("No matching super-reg register class.", MO, MONum); in visitMachineOperand()
1043 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()
1045 errs() << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
1046 << " register, but got a " << TRI->getRegClassName(RC) in visitMachineOperand()
1056 regMasks.push_back(MO->getRegMask()); in visitMachineOperand()
1060 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent())) in visitMachineOperand()
1065 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && in visitMachineOperand()
1066 LiveInts && !LiveInts->isNotInMIMap(*MI)) { in visitMachineOperand()
1067 int FI = MO->getIndex(); in visitMachineOperand()
1068 LiveInterval &LI = LiveStks->getInterval(FI); in visitMachineOperand()
1069 SlotIndex Idx = LiveInts->getInstructionIndex(*MI); in visitMachineOperand()
1071 bool stores = MI->mayStore(); in visitMachineOperand()
1072 bool loads = MI->mayLoad(); in visitMachineOperand()
1073 // For a memory-to-memory move, we need to check if the frame in visitMachineOperand()
1077 for (auto *MMO : MI->memoperands()) { in visitMachineOperand()
1078 const PseudoSourceValue *PSV = MMO->getPseudoValue(); in visitMachineOperand()
1083 if (Value->getFrameIndex() != FI) continue; in visitMachineOperand()
1085 if (MMO->isStore()) in visitMachineOperand()
1122 if (MO->isKill() && !LRQ.isKill()) { in checkLivenessAtUse()
1137 if (VNI->def != DefIdx) { in checkLivenessAtDef()
1138 report("Inconsistent valno->def", MO, MONum); in checkLivenessAtDef()
1155 if (MO->isDead()) { in checkLivenessAtDef()
1158 // In case of physregs we can have a non-dead definition on another in checkLivenessAtDef()
1162 const MachineInstr &MI = *MO->getParent(); in checkLivenessAtDef()
1188 const MachineInstr *MI = MO->getParent(); in checkLiveness()
1189 const unsigned Reg = MO->getReg(); in checkLiveness()
1192 if (MO->readsReg()) { in checkLiveness()
1195 if (MO->isKill()) in checkLiveness()
1200 MO->isKill()) { in checkLiveness()
1201 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); in checkLiveness()
1207 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) { in checkLiveness()
1208 SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI); in checkLiveness()
1212 if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units)) in checkLiveness()
1218 if (LiveInts->hasInterval(Reg)) { in checkLiveness()
1220 const LiveInterval &LI = LiveInts->getInterval(Reg); in checkLiveness()
1223 if (LI.hasSubRanges() && !MO->isDef()) { in checkLiveness()
1224 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness()
1226 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
1227 : MRI->getMaxLaneMaskForVReg(Reg); in checkLiveness()
1265 // If there is an additional implicit-use of a super register we stop in checkLiveness()
1270 for (const MachineOperand &MOP : MI->uses()) { in checkLiveness()
1286 } else if (MRI->def_empty(Reg)) { in checkLiveness()
1289 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; in checkLiveness()
1295 else if (!MI->isPHI()) in checkLiveness()
1301 if (MO->isDef()) { in checkLiveness()
1304 if (MO->isDead()) in checkLiveness()
1310 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) && in checkLiveness()
1311 std::next(MRI->def_begin(Reg)) != MRI->def_end()) in checkLiveness()
1315 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) { in checkLiveness()
1316 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI); in checkLiveness()
1317 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber()); in checkLiveness()
1320 if (LiveInts->hasInterval(Reg)) { in checkLiveness()
1321 const LiveInterval &LI = LiveInts->getInterval(Reg); in checkLiveness()
1325 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness()
1327 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
1328 : MRI->getMaxLaneMaskForVReg(Reg); in checkLiveness()
1348 // Normal stand-alone instructions are also considered 'bundles', and this
1351 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; in visitMachineBundleAfter()
1372 SlotIndex stop = Indexes->getMBBEndIdx(MBB); in visitMachineBasicBlockAfter()
1383 // can pass through an MBB live, but may not be live every time. It is assumed
1386 // First push live-out regs to successors' vregsPassed. Remember the MBBs that in calcRegsPassed()
1407 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), in calcRegsPassed()
1408 SuE = MBB->succ_end(); SuI != SuE; ++SuI) { in calcRegsPassed()
1418 // Calculate the set of virtual registers that must be passed through each basic
1422 // First push live-in regs to predecessors' vregsRequired. in calcRegsRequired()
1440 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), in calcRegsRequired()
1441 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { in calcRegsRequired()
1463 if (!Pre->isSuccessor(MBB)) in checkPHIOps()
1468 report("PHI operand is not live-out from predecessor", in checkPHIOps()
1473 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), in checkPHIOps()
1474 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { in checkPHIOps()
1477 errs() << "BB#" << (*PrI)->getNumber() in checkPHIOps()
1513 if (!MF->empty()) { in visitMachineFunctionAfter()
1514 BBInfo &MInfo = MBBInfoMap[&MF->front()]; in visitMachineFunctionAfter()
1531 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in verifyLiveVariables()
1533 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); in verifyLiveVariables()
1542 << " must be live through the block.\n"; in verifyLiveVariables()
1548 << " is not needed live through the block.\n"; in verifyLiveVariables()
1557 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in verifyLiveIntervals()
1561 if (MRI->reg_nodbg_empty(Reg)) in verifyLiveIntervals()
1564 if (!LiveInts->hasInterval(Reg)) { in verifyLiveIntervals()
1570 const LiveInterval &LI = LiveInts->getInterval(Reg); in verifyLiveIntervals()
1576 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i) in verifyLiveIntervals()
1577 if (const LiveRange *LR = LiveInts->getCachedRegUnit(i)) in verifyLiveIntervals()
1584 if (VNI->isUnused()) in verifyLiveRangeValue()
1587 const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def); in verifyLiveRangeValue()
1603 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def); in verifyLiveRangeValue()
1611 if (VNI->isPHIDef()) { in verifyLiveRangeValue()
1612 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) { in verifyLiveRangeValue()
1620 // Non-PHI def. in verifyLiveRangeValue()
1621 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def); in verifyLiveRangeValue()
1633 if (!MOI->isReg() || !MOI->isDef()) in verifyLiveRangeValue()
1636 if (MOI->getReg() != Reg) in verifyLiveRangeValue()
1639 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) || in verifyLiveRangeValue()
1640 !TRI->hasRegUnit(MOI->getReg(), Reg)) in verifyLiveRangeValue()
1644 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask) == 0) in verifyLiveRangeValue()
1647 if (MOI->isEarlyClobber()) in verifyLiveRangeValue()
1660 if (!VNI->def.isEarlyClobber()) { in verifyLiveRangeValue()
1661 report("Early clobber def must be at an early-clobber slot", MBB); in verifyLiveRangeValue()
1665 } else if (!VNI->def.isRegister()) { in verifyLiveRangeValue()
1666 report("Non-PHI, non-early clobber def must be at a register slot", MBB); in verifyLiveRangeValue()
1681 if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) { in verifyLiveRangeSegment()
1688 if (VNI->isUnused()) { in verifyLiveRangeSegment()
1694 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start); in verifyLiveRangeSegment()
1701 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB); in verifyLiveRangeSegment()
1702 if (S.start != MBBStartIdx && S.start != VNI->def) { in verifyLiveRangeSegment()
1709 LiveInts->getMBBFromIndex(S.end.getPrevSlot()); in verifyLiveRangeSegment()
1717 // No more checks for live-out segments. in verifyLiveRangeSegment()
1718 if (S.end == LiveInts->getMBBEndIdx(EndMBB)) in verifyLiveRangeSegment()
1722 if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() && in verifyLiveRangeSegment()
1723 S.start == VNI->def && S.end == VNI->def.getDeadSlot()) in verifyLiveRangeSegment()
1728 LiveInts->getInstructionFromIndex(S.end.getPrevSlot()); in verifyLiveRangeSegment()
1753 // A live segment can only end at an early-clobber slot if it is being in verifyLiveRangeSegment()
1754 // redefined by an early-clobber def. in verifyLiveRangeSegment()
1756 if (I+1 == LR.end() || (I+1)->start != S.end) { in verifyLiveRangeSegment()
1773 if (!MOI->isReg() || MOI->getReg() != Reg) in verifyLiveRangeSegment()
1776 (LaneMask & TRI->getSubRegIndexLaneMask(MOI->getSubReg())) == 0) in verifyLiveRangeSegment()
1778 if (MOI->isDef()) { in verifyLiveRangeSegment()
1779 if (MOI->getSubReg() != 0) in verifyLiveRangeSegment()
1781 if (MOI->isDead()) in verifyLiveRangeSegment()
1784 if (MOI->readsReg()) in verifyLiveRangeSegment()
1801 if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask != 0 || in verifyLiveRangeSegment()
1813 MachineFunction::const_iterator MFI = MBB->getIterator(); in verifyLiveRangeSegment()
1814 // Is this live segment the beginning of a non-PHIDef VN? in verifyLiveRangeSegment()
1815 if (S.start == VNI->def && !VNI->isPHIDef()) { in verifyLiveRangeSegment()
1816 // Not live-in to any blocks. in verifyLiveRangeSegment()
1823 assert(LiveInts->isLiveInToMBB(LR, &*MFI)); in verifyLiveRangeSegment()
1826 MFI->isEHPad()) { in verifyLiveRangeSegment()
1833 // Is VNI a PHI-def in the current block? in verifyLiveRangeSegment()
1834 bool IsPHI = VNI->isPHIDef() && in verifyLiveRangeSegment()
1835 VNI->def == LiveInts->getMBBStartIdx(&*MFI); in verifyLiveRangeSegment()
1837 // Check that VNI is live-out of all predecessors. in verifyLiveRangeSegment()
1838 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(), in verifyLiveRangeSegment()
1839 PE = MFI->pred_end(); PI != PE; ++PI) { in verifyLiveRangeSegment()
1840 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI); in verifyLiveRangeSegment()
1843 // All predecessors must have a live-out value if this is not a in verifyLiveRangeSegment()
1849 errs() << " live into BB#" << MFI->getNumber() in verifyLiveRangeSegment()
1850 << '@' << LiveInts->getMBBStartIdx(&*MFI) << ", not live before " in verifyLiveRangeSegment()
1855 // Only PHI-defs can take different predecessor values. in verifyLiveRangeSegment()
1859 errs() << "Valno #" << PVNI->id << " live out of BB#" in verifyLiveRangeSegment()
1860 << (*PI)->getNumber() << '@' << PEnd << "\nValno #" << VNI->id in verifyLiveRangeSegment()
1861 << " live into BB#" << MFI->getNumber() << '@' in verifyLiveRangeSegment()
1862 << LiveInts->getMBBStartIdx(&*MFI) << '\n'; in verifyLiveRangeSegment()
1886 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg); in verifyLiveInterval()
1919 errs() << ' ' << (*I)->id; in verifyLiveInterval()
1944 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
1948 unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode(); in verifyStackFrame()
1949 unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode(); in verifyStackFrame()
1952 SPState.resize(MF->getNumBlockIDs()); in verifyStackFrame()
1965 const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2); in verifyStackFrame()
1968 BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue; in verifyStackFrame()
1969 BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup; in verifyStackFrame()
1980 "Value should be non-negative in FrameSetup and FrameDestroy.\n"); in verifyStackFrame()
1984 BBState.ExitValue -= Size; in verifyStackFrame()
1992 "Value should be non-negative in FrameSetup and FrameDestroy.\n"); in verifyStackFrame()
1996 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue : in verifyStackFrame()
2007 SPState[MBB->getNumber()] = BBState; in verifyStackFrame()
2011 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(), in verifyStackFrame()
2012 E = MBB->pred_end(); I != E; ++I) { in verifyStackFrame()
2014 (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue || in verifyStackFrame()
2015 SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) { in verifyStackFrame()
2017 errs() << "Predecessor BB#" << (*I)->getNumber() << " has exit state (" in verifyStackFrame()
2018 << SPState[(*I)->getNumber()].ExitValue << ", " in verifyStackFrame()
2019 << SPState[(*I)->getNumber()].ExitIsSetup in verifyStackFrame()
2020 << "), while BB#" << MBB->getNumber() << " has entry state (" in verifyStackFrame()
2027 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(), in verifyStackFrame()
2028 E = MBB->succ_end(); I != E; ++I) { in verifyStackFrame()
2030 (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue || in verifyStackFrame()
2031 SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) { in verifyStackFrame()
2033 errs() << "Successor BB#" << (*I)->getNumber() << " has entry state (" in verifyStackFrame()
2034 << SPState[(*I)->getNumber()].EntryValue << ", " in verifyStackFrame()
2035 << SPState[(*I)->getNumber()].EntryIsSetup in verifyStackFrame()
2036 << "), while BB#" << MBB->getNumber() << " has exit state (" in verifyStackFrame()
2042 if (!MBB->empty() && MBB->back().isReturn()) { in verifyStackFrame()