Lines Matching +full:- +full:- +full:disable +full:- +full:static
1 //===-- TargetPassConfig.cpp - Target independent code generation passes --===//
8 //===----------------------------------------------------------------------===//
13 //===---------------------------------------------------------------------===//
41 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
42 cl::desc("Disable Post Regalloc"));
43 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
44 cl::desc("Disable branch folding"));
45 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
46 cl::desc("Disable tail duplication"));
47 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
48 cl::desc("Disable pre-register allocation tail duplication"));
49 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
50 cl::Hidden, cl::desc("Disable probability-driven block placement"));
51 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
52 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
53 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
54 cl::desc("Disable Stack Slot Coloring"));
55 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
56 cl::desc("Disable Machine Dead Code Elimination"));
57 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
58 cl::desc("Disable Early If-conversion"));
59 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
60 cl::desc("Disable Machine LICM"));
61 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
62 cl::desc("Disable Machine Common Subexpression Elimination"));
63 static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
64 "optimize-regalloc", cl::Hidden,
66 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
68 cl::desc("Disable Machine LICM"));
69 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
70 cl::desc("Disable Machine Sinking"));
71 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
72 cl::desc("Disable Loop Strength Reduction Pass"));
73 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
74 cl::Hidden, cl::desc("Disable ConstantHoisting"));
75 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
76 cl::desc("Disable Codegen Prepare"));
77 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
78 cl::desc("Disable Copy Propagation pass"));
79 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
80 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
81 static cl::opt<bool> EnableImplicitNullChecks(
82 "enable-implicit-null-checks",
85 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
86 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
87 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
89 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
91 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
96 static cl::opt<std::string>
97 PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
99 cl::value_desc("pass-name"), cl::init("option-unspecified"));
101 // Temporary option to allow experimenting with MachineScheduler as a post-RA
106 cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
110 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
113 // Experimental option to use CFL-AA in codegen
115 static cl::opt<CFLAAType> UseCFLAA(
116 "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
118 cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
120 "Enable unification-based CFL-AA"),
122 "Enable inclusion-based CFL-AA"),
124 "Enable both variants of CFL-AA"),
129 /// i.e. -disable-mypass=false has no effect.
131 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, in applyDisable()
142 /// to addPass(). It may be a target-specific ID in the case that the target
150 static IdentifyingPassPtr overridePass(AnalysisID StandardID, in overridePass()
194 //===---------------------------------------------------------------------===//
196 //===---------------------------------------------------------------------===//
236 // user interface. For example, a target may disable a standard pass by
275 TM->Options.PrintMachineCode = true; in TargetPassConfig()
279 return TM->getOptLevel(); in getOptLevel()
289 TargetPassID != InsertedPassID.getInstance()->getPassID())) && in insertPass()
291 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter, in insertPass()
295 /// createPassConfig - Create a pass configuration object to be used by
305 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly"); in TargetPassConfig()
316 Impl->TargetPasses[StandardID] = TargetID; in substitutePass()
321 I = Impl->TargetPasses.find(ID); in getPassSubstitution()
322 if (I == Impl->TargetPasses.end()) in getPassSubstitution()
324 return I->second; in getPassSubstitution()
346 AnalysisID PassID = P->getPassID(); in addPass()
352 // Construct banner message before PM->add() as that may delete the pass. in addPass()
354 Banner = std::string("After ") + std::string(P->getPassName()); in addPass()
355 PM->add(P); in addPass()
364 for (auto IP : Impl->InsertedPasses) { in addPass()
399 AnalysisID FinalID = P->getPassID(); in addPass()
411 if (TM->shouldPrintMachineCode()) in addPrintPass()
412 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner)); in addPrintPass()
417 PM->add(createMachineVerifierPass(Banner)); in addVerifyPass()
441 // support "obvious" type-punning idioms. in addIRPasses()
447 // coming from the front-end and/or optimizer is valid. in addIRPasses()
477 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) { in addPassesToHandleExceptions()
479 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both in addPassesToHandleExceptions()
492 // We support using both GCC-style and MSVC-style exceptions on Windows, so in addPassesToHandleExceptions()
521 if (TM->Options.EnableIPRA) in addISelPrepare()
539 /// Add the complete set of target-independent postISel code generator passes.
547 /// target-specific fixups just before or after major stages. Additionally,
556 /// before/after any target-independent pass. But it's currently overkill.
560 if (TM->Options.EnableIPRA) in addMachinePasses()
565 !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) { in addMachinePasses()
567 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue()); in addMachinePasses()
568 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer")); in addMachinePasses()
570 const char *TID = (const char *)(TPI->getTypeInfo()); in addMachinePasses()
571 const char *IID = (const char *)(IPI->getTypeInfo()); in addMachinePasses()
578 // Expand pseudo-instructions emitted by ISel. in addMachinePasses()
590 // Run pre-ra passes. in addMachinePasses()
600 // Run post-ra passes. in addMachinePasses()
619 // Run pre-sched2 passes. in addMachinePasses()
629 !TM->targetSchedulesPostRAScheduling()) { in addMachinePasses()
648 if (TM->Options.EnableIPRA) in addMachinePasses()
666 // Pre-ra tail duplication. in addMachineSSAOptimization()
688 // like if-conversion. Such passes will typically need dominator trees and in addMachineSSAOptimization()
697 // Clean-up the dead code that may have been generated by peephole in addMachineSSAOptimization()
702 //===---------------------------------------------------------------------===//
704 //===---------------------------------------------------------------------===//
712 llvm_unreachable("Invalid optimize-regalloc state"); in getOptimizeRegAlloc()
721 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; } in useDefaultRegisterAllocator()
722 static RegisterRegAlloc
724 "pick register allocator based on -O option",
727 /// -regalloc=... command line option.
728 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
734 static void initializeDefaultRegisterAllocatorOnce() { in initializeDefaultRegisterAllocatorOnce()
750 /// allocation may still override this for per-target regalloc
751 /// selection. But -regalloc=... always takes precedence.
777 // With no -regalloc= override, ask the target for a regalloc pass. in createRegAllocPass()
782 /// has not be overriden on the command line with '-regalloc=...'
787 /// Add the minimum set of target-independent passes that are required for
797 /// Add standard target-independent passes that are tightly coupled with
842 // Perform stack slot coloring and post-ra machine LICM. in addOptimizedRegAlloc()
844 // FIXME: Re-enable coloring with register when it's capable of adding in addOptimizedRegAlloc()
848 // Run post-ra machine LICM to hoist reloads / remats. in addOptimizedRegAlloc()
855 //===---------------------------------------------------------------------===//
857 //===---------------------------------------------------------------------===//
867 // In addition it can also make CFG irreducible. Thus we disable it. in addMachineLateOptimization()
868 if (!TM->requiresStructuredCFG()) in addMachineLateOptimization()