Lines Matching +full:bare +full:- +full:events
1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
8 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
65 /// is not 64-bit aligned.
75 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
78 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
81 /// ARMArch - ARM architecture
85 /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
101 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
109 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
114 /// UseMulOps - True if non-microcoded fused integer multiply-add and
115 /// multiply-subtract instructions should be used.
118 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
122 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
126 /// SlowFPBrcc - True if floating point compare + branch is slow.
129 /// InThumbMode - True if compiling for Thumb, false for ARM.
132 /// UseSoftFloat - True if we're using software floating point features.
135 /// HasThumb2 - True if Thumb2 instructions are supported.
138 /// NoARM - True if subtarget does not support ARM mode execution.
141 /// ReserveR9 - True if R9 is not available as a general purpose register.
144 /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
145 /// 32-bit imms (including global addresses).
148 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
153 /// HasFP16 - True if subtarget supports half-precision FP conversions
156 /// HasFullFP16 - True if subtarget supports half-precision FP operations
159 /// HasD16 - True if subtarget is limited to 16 double precision
163 /// HasHardwareDivide - True if subtarget supports [su]div
166 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
169 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
173 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
177 /// HasV7Clrex - True if the subtarget supports CLREX instructions
180 /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
184 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
185 /// over 16-bit ones.
188 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
193 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
197 /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
201 /// HasMPExtension - True if the subtarget supports Multiprocessing
205 /// HasVirtualization - True if the subtarget supports the Virtualization
209 /// FPOnlySP - If true, the floating point unit only supports single
214 /// include a generic cycle-counter as well as more fine-grained (often
215 /// implementation-specific) events.
218 /// HasTrustZone - if true, processor supports TrustZone security extensions
221 /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
224 /// HasCrypto - if true, processor supports Cryptography extensions
227 /// HasCRC - if true, processor supports CRC instructions
230 /// HasRAS - if true, the processor supports RAS extensions
280 /// StrictAlign - If true, the subtarget disallows unaligned memory
285 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
289 /// HasDSP - If true, the subtarget supports the DSP (saturating arith
302 /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
305 /// stackAlignment - The minimum alignment known to hold of the stack frame on
309 /// CPUString - String name of used CPU.
322 /// operand cycle returned by the itinerary data for pre-ISel operands.
325 /// IsLittle - The target is Little Endian
328 /// TargetTriple - What processor and OS we're targeting.
331 /// SchedModel - Processor specific instruction costs.
349 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
354 /// ParseSubtargetFeatures - Parses features string setting specified
358 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
375 return &InstrInfo->getRegisterInfo(); in getRegisterInfo()
498 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
499 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
500 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
504 // "*-*-*-macho" triples as quickly as possible.
561 /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
590 /// True for some subtargets at > -O0.
593 // enableAtomicExpand- True if we need to expand our atomics.
596 /// getInstrItins - Return the instruction itineraries based on subtarget
602 /// getStackAlignment - Returns the minimum alignment known to hold of the
622 /// True if fast-isel is used.