Lines Matching +full:check +full:- +full:32 +full:bit

1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
2 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck …
13 ; CHECK-LABEL: ldst_8bit:
15 ; No architectural support for loads to 16-bit or 8-bit since we
18 ; match a sign-extending load 8-bit -> 32-bit
22 ; CHECK: adrp {{x[0-9]+}}, var_8bit
23 ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
25 ; match a zero-extending load volatile 8-bit -> 32-bit
29 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
31 ; match an any-extending load volatile 8-bit -> 32-bit
35 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
37 ; match a sign-extending load volatile 8-bit -> 64-bit
41 ; CHECK: ldrsb {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
43 ; match a zero-extending load volatile 8-bit -> 64-bit.
44 ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
45 ; of x0 so it's identical to load volatileing to 32-bits.
49 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
51 ; truncating store volatile 32-bits to 8-bits
55 ; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
57 ; truncating store volatile 64-bits to 8-bits
61 ; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
67 ; CHECK-LABEL: ldst_16bit:
69 ; No architectural support for load volatiles to 16-bit promote i16 during
72 ; match a sign-extending load volatile 16-bit -> 32-bit
76 ; CHECK: adrp {{x[0-9]+}}, var_16bit
77 ; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
79 ; match a zero-extending load volatile 16-bit -> 32-bit
83 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
85 ; match an any-extending load volatile 16-bit -> 32-bit
89 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
91 ; match a sign-extending load volatile 16-bit -> 64-bit
95 ; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
97 ; match a zero-extending load volatile 16-bit -> 64-bit.
98 ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
99 ; of x0 so it's identical to load volatileing to 32-bits.
103 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
105 ; truncating store volatile 32-bits to 16-bits
109 ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
111 ; truncating store volatile 64-bits to 16-bits
115 ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
121 ; CHECK-LABEL: ldst_32bit:
123 ; Straight 32-bit load/store
126 ; CHECK: adrp {{x[0-9]+}}, var_32bit
127 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
128 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
130 ; Zero-extension to 64-bits
134 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
135 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
137 ; Sign-extension to 64-bits
141 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
142 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
144 ; Truncation from 64-bits
148 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
149 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
159 ; Now check that our selection copes with accesses more complex than a
162 ; check the various access-sizes involved.
165 ; CHECK: ldst_complex_offsets
167 ; CHECK: adrp {{x[0-9]+}}, arr8
168 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr8]
173 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #1]
178 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #4095]
182 ; CHECK: adrp {{x[0-9]+}}, arr16
183 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr16]
188 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #2]
193 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #8190]
197 ; CHECK: adrp {{x[0-9]+}}, arr32
198 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr32]
203 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #4]
208 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #16380]
212 ; CHECK: adrp {{x[0-9]+}}, arr64
213 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr64]
218 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #8]
223 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #32760]
229 ; CHECK-LABEL: ldst_float:
232 ; CHECK: adrp {{x[0-9]+}}, var_float
233 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_float]
234 ; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
237 ; CHECK: str {{s[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_float]
238 ; CHECK-NOFP-NOT: str {{s[0-9]+}},
244 ; CHECK-LABEL: ldst_double:
247 ; CHECK: adrp {{x[0-9]+}}, var_double
248 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_double]
249 ; CHECK-NOFP-NOT: ldr {{d[0-9]+}},
252 ; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_double]
253 ; CHECK-NOFP-NOT: str {{d[0-9]+}},