Lines Matching +full:d3 +full:- +full:force
1 ; RUN: llc < %s -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s
2 ; RUN: llc < %s -arm-assume-misaligned-load-store -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck…
5 ; begin in the most-significant half of a q register. These require more
6 ; micro-ops on swift and so aren't worth combining.
8 ; CHECK-LABEL: test_vldm
9 ; CHECK: vldmia r{{[0-9]+}}, {d2, d3, d4}
10 ; CHECK-NOT: vldmia r{{[0-9]+}}, {d1, d2, d3, d4}
12 declare fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
22 %d3 = load double , double * %addr2
24 ; We are trying to force x[0-3] in registers d1 to d4 so that we can test we
25 ; don't form a "vldmia rX, {d1, d2, d3, d4}".
28 call fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)