Lines Matching +full:check +full:- +full:all
1 ; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s
2 ; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s
3 ; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s
4 ; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s
6 ; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
7 ; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
8 ; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV…
9 ; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-I…
11 ; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
12 ; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
13 ; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s
14 ; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s
16 ; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
17 ; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
18 ; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
19 ; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
21 …-march=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump -no-show-raw-in…
23 ; Test the the callee-saved registers are callee-saved as specified by section
32 ; ALL-LABEL: fpu_clobber:
33 ; ALL-INV-NOT: sdc1 $f0,
34 ; ALL-INV-NOT: sdc1 $f1,
35 ; ALL-INV-NOT: sdc1 $f2,
36 ; ALL-INV-NOT: sdc1 $f3,
37 ; ALL-INV-NOT: sdc1 $f4,
38 ; ALL-INV-NOT: sdc1 $f5,
39 ; ALL-INV-NOT: sdc1 $f6,
40 ; ALL-INV-NOT: sdc1 $f7,
41 ; ALL-INV-NOT: sdc1 $f8,
42 ; ALL-INV-NOT: sdc1 $f9,
43 ; ALL-INV-NOT: sdc1 $f10,
44 ; ALL-INV-NOT: sdc1 $f11,
45 ; ALL-INV-NOT: sdc1 $f12,
46 ; ALL-INV-NOT: sdc1 $f13,
47 ; ALL-INV-NOT: sdc1 $f14,
48 ; ALL-INV-NOT: sdc1 $f15,
49 ; ALL-INV-NOT: sdc1 $f16,
50 ; ALL-INV-NOT: sdc1 $f17,
51 ; ALL-INV-NOT: sdc1 $f18,
52 ; ALL-INV-NOT: sdc1 $f19,
53 ; ALL-INV-NOT: sdc1 $f21,
54 ; ALL-INV-NOT: sdc1 $f23,
56 ; O32: addiu $sp, $sp, -48
57 ; O32-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
58 ; O32-DAG: sdc1 [[F22:\$f22]], [[OFF22:[0-9]+]]($sp)
59 ; O32-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
60 ; O32-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)
61 ; O32-DAG: sdc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp)
62 ; O32-DAG: sdc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp)
63 ; O32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
64 ; O32-DAG: ldc1 [[F22]], [[OFF22]]($sp)
65 ; O32-DAG: ldc1 [[F24]], [[OFF24]]($sp)
66 ; O32-INV-NOT: sdc1 $f25,
67 ; O32-DAG: ldc1 [[F26]], [[OFF26]]($sp)
68 ; O32-INV-NOT: sdc1 $f27,
69 ; O32-DAG: ldc1 [[F28]], [[OFF28]]($sp)
70 ; O32-INV-NOT: sdc1 $f29,
71 ; O32-DAG: ldc1 [[F30]], [[OFF30]]($sp)
72 ; O32-INV-NOT: sdc1 $f31,
75 ; N32: addiu $sp, $sp, -48
76 ; N32-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
77 ; N32-DAG: sdc1 [[F22:\$f22]], [[OFF22:[0-9]+]]($sp)
78 ; N32-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
79 ; N32-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)
80 ; N32-DAG: sdc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp)
81 ; N32-DAG: sdc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp)
82 ; N32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
83 ; N32-DAG: ldc1 [[F22]], [[OFF22]]($sp)
84 ; N32-DAG: ldc1 [[F24]], [[OFF24]]($sp)
85 ; N32-INV-NOT: sdc1 $f25,
86 ; N32-DAG: ldc1 [[F26]], [[OFF26]]($sp)
87 ; N32-INV-NOT: sdc1 $f27,
88 ; N32-DAG: ldc1 [[F28]], [[OFF28]]($sp)
89 ; N32-INV-NOT: sdc1 $f29,
90 ; N32-DAG: ldc1 [[F30]], [[OFF30]]($sp)
91 ; N32-INV-NOT: sdc1 $f31,
94 ; N64: addiu $sp, $sp, -64
95 ; N64-INV-NOT: sdc1 $f20,
96 ; N64-INV-NOT: sdc1 $f22,
97 ; N64-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
98 ; N64-DAG: sdc1 [[F25:\$f25]], [[OFF25:[0-9]+]]($sp)
99 ; N64-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)
100 ; N64-DAG: sdc1 [[F27:\$f27]], [[OFF27:[0-9]+]]($sp)
101 ; N64-DAG: sdc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp)
102 ; N64-DAG: sdc1 [[F29:\$f29]], [[OFF29:[0-9]+]]($sp)
103 ; N64-DAG: sdc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp)
104 ; N64-DAG: sdc1 [[F31:\$f31]], [[OFF31:[0-9]+]]($sp)
105 ; N64-DAG: ldc1 [[F24]], [[OFF24]]($sp)
106 ; N64-DAG: ldc1 [[F25]], [[OFF25]]($sp)
107 ; N64-DAG: ldc1 [[F26]], [[OFF26]]($sp)
108 ; N64-DAG: ldc1 [[F27]], [[OFF27]]($sp)
109 ; N64-DAG: ldc1 [[F28]], [[OFF28]]($sp)
110 ; N64-DAG: ldc1 [[F29]], [[OFF29]]($sp)
111 ; N64-DAG: ldc1 [[F30]], [[OFF30]]($sp)
112 ; N64-DAG: ldc1 [[F31]], [[OFF31]]($sp)
115 ; Check the mapping between LDC164 and LDC1_64_MMR6.