Lines Matching +full:d3 +full:- +full:hierarchy
1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
8 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
27 #define DEBUG_TYPE "regalloc-emitter"
29 //===----------------------------------------------------------------------===//
31 //===----------------------------------------------------------------------===//
35 Name = R->getName(); in CodeGenSubRegIndex()
36 if (R->getValue("Namespace")) in CodeGenSubRegIndex()
37 Namespace = R->getValueAsString("Namespace"); in CodeGenSubRegIndex()
38 Size = R->getValueAsInt("Size"); in CodeGenSubRegIndex()
39 Offset = R->getValueAsInt("Offset"); in CodeGenSubRegIndex()
44 : TheDef(nullptr), Name(N), Namespace(Nspace), Size(-1), Offset(-1), in CodeGenSubRegIndex()
60 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf"); in updateComponents()
63 PrintFatalError(TheDef->getLoc(), in updateComponents()
67 CodeGenSubRegIndex *X = A->addComposite(B, this); in updateComponents()
69 PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries"); in updateComponents()
73 TheDef->getValueAsListOfDefs("CoveringSubRegIndices"); in updateComponents()
76 PrintFatalError(TheDef->getLoc(), in updateComponents()
93 // The lane mask is simply the union of all sub-indices. in computeLaneMask()
96 M |= C.second->computeLaneMask(); in computeLaneMask()
97 assert(M && "Missing lane mask, sub-register cycle?"); in computeLaneMask()
102 //===----------------------------------------------------------------------===//
104 //===----------------------------------------------------------------------===//
109 CostPerUse(R->getValueAsInt("CostPerUse")), in CodeGenRegister()
110 CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")), in CodeGenRegister()
118 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices"); in buildObjectGraph()
119 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs"); in buildObjectGraph()
122 PrintFatalError(TheDef->getLoc(), in buildObjectGraph()
130 // Also compute leading super-registers. Each register has a list of in buildObjectGraph()
131 // covered-by-subregs super-registers where it appears as the first explicit in buildObjectGraph()
132 // sub-register. in buildObjectGraph()
136 ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this); in buildObjectGraph()
140 std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases"); in buildObjectGraph()
144 Reg->ExplicitAliases.push_back(this); in buildObjectGraph()
150 return TheDef->getName(); in getName()
164 UnitI = (*RegI)->getRegUnits().begin(); in RegUnitIterator()
165 UnitE = (*RegI)->getRegUnits().end(); in RegUnitIterator()
188 UnitI = (*RegI)->getRegUnits().begin(); in advance()
189 UnitE = (*RegI)->getRegUnits().end(); in advance()
206 CodeGenRegister *SR = I->second; in inheritRegUnits()
208 changed |= (RegUnits |= SR->RegUnits); in inheritRegUnits()
228 PrintFatalError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() + in computeSubRegs()
230 // Map explicit sub-registers first, so the names take precedence. in computeSubRegs()
231 // The inherited sub-registers are mapped below. in computeSubRegs()
239 // Here the order is important - earlier subregs take precedence. in computeSubRegs()
242 const SubRegMap &Map = SR->computeSubRegs(RegBank); in computeSubRegs()
243 HasDisjunctSubRegs |= SR->HasDisjunctSubRegs; in computeSubRegs()
248 Orphans.insert(SI->second); in computeSubRegs()
259 const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites(); in computeSubRegs()
261 const SubRegMap &Map = SR->computeSubRegs(RegBank); in computeSubRegs()
267 SubRegMap::const_iterator SRI = Map.find(I->first); in computeSubRegs()
269 continue; // Idx + I->first doesn't exist in SR. in computeSubRegs()
270 // Add I->second as a name for the subreg SRI->second, assuming it is in computeSubRegs()
272 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second)) in computeSubRegs()
274 // We found a new name for the orphaned sub-register. in computeSubRegs()
275 SubRegs.insert(std::make_pair(I->second, SRI->second)); in computeSubRegs()
276 Indices.push_back(I->second); in computeSubRegs()
282 // Work backwards in the Indices vector in order to compose subregs bottom-up. in computeSubRegs()
285 // qsub_1 -> dsub_0 -> ssub_0 in computeSubRegs()
287 // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register in computeSubRegs()
290 // qsub_1 -> ssub_0 in computeSubRegs()
291 // dsub_2 -> ssub_0 in computeSubRegs()
295 // dsub_2 -> ssub_0 composition can be shared. in computeSubRegs()
299 const SubRegMap &Map = SR->computeSubRegs(RegBank); in computeSubRegs()
302 if (Orphans.erase(SI->second)) in computeSubRegs()
303 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SI->first)] = SI->second; in computeSubRegs()
306 // Compute the inverse SubReg -> Idx map. in computeSubRegs()
309 if (SI->second == this) { in computeSubRegs()
312 Loc = TheDef->getLoc(); in computeSubRegs()
314 " has itself as a sub-register"); in computeSubRegs()
319 SI->first->AllSuperRegsCovered = false; in computeSubRegs()
321 // Ensure that every sub-register has a unique name. in computeSubRegs()
323 SubReg2Idx.insert(std::make_pair(SI->second, SI->first)).first; in computeSubRegs()
324 if (Ins->second == SI->first) in computeSubRegs()
326 // Trouble: Two different names for SI->second. in computeSubRegs()
329 Loc = TheDef->getLoc(); in computeSubRegs()
330 PrintFatalError(Loc, "Sub-register can't have two names: " + in computeSubRegs()
331 SI->second->getName() + " available as " + in computeSubRegs()
332 SI->first->getName() + " and " + Ins->second->getName()); in computeSubRegs()
335 // Derive possible names for sub-register concatenations from any explicit in computeSubRegs()
336 // sub-registers. By doing this before computeSecondarySubRegs(), we ensure in computeSubRegs()
341 if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1) in computeSubRegs()
344 // SR is composed of multiple sub-regs. Find their names in this register. in computeSubRegs()
346 for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j) in computeSubRegs()
347 Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j])); in computeSubRegs()
354 // processes the register hierarchy in postorder. in computeSubRegs()
356 // Inherit all sub-register units. It is good enough to look at the explicit in computeSubRegs()
357 // sub-registers, the other registers won't contribute any more units. in computeSubRegs()
360 RegUnits |= SR->RegUnits; in computeSubRegs()
375 if (AR->SubRegsComplete) in computeSubRegs()
381 AR->RegUnits.set(Unit); in computeSubRegs()
385 // a leaf register with ad hoc aliases doesn't get its own unit - it isn't in computeSubRegs()
397 // In a register that is covered by its sub-registers, try to find redundant
398 // sub-registers. For example:
402 // Q1 = {D2, D3}
404 // We can infer that D1_D2 is also a sub-register, even if it wasn't named in
408 // sub-register relationships that would force a DAG.
411 // Collect new sub-registers first, add them later. in computeSecondarySubRegs()
414 // Look at the leading super-registers of each sub-register. Those are the in computeSecondarySubRegs()
415 // candidates for new sub-registers, assuming they are fully contained in in computeSecondarySubRegs()
418 const CodeGenRegister *SubReg = I->second; in computeSecondarySubRegs()
419 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs; in computeSecondarySubRegs()
422 // Already got this sub-register? in computeSecondarySubRegs()
425 // Check if each component of Cand is already a sub-register. in computeSecondarySubRegs()
426 // We know that the first component is I->second, and is present with the in computeSecondarySubRegs()
427 // name I->first. in computeSecondarySubRegs()
428 SmallVector<CodeGenSubRegIndex*, 8> Parts(1, I->first); in computeSecondarySubRegs()
429 assert(!Cand->ExplicitSubRegs.empty() && in computeSecondarySubRegs()
430 "Super-register has no sub-registers"); in computeSecondarySubRegs()
431 for (unsigned j = 1, e = Cand->ExplicitSubRegs.size(); j != e; ++j) { in computeSecondarySubRegs()
432 if (CodeGenSubRegIndex *Idx = getSubRegIndex(Cand->ExplicitSubRegs[j])) in computeSecondarySubRegs()
435 // Sub-register doesn't exist. in computeSecondarySubRegs()
440 // If some Cand sub-register is not part of this register, or if Cand only in computeSecondarySubRegs()
441 // has one sub-register, there is nothing to do. in computeSecondarySubRegs()
445 // Each part of Cand is a sub-register of this. Make the full Cand also in computeSecondarySubRegs()
446 // a sub-register with a concatenated sub-register index. in computeSecondarySubRegs()
452 // Now add all the new sub-registers. in computeSecondarySubRegs()
454 // Don't add Cand if another sub-register is already using the index. in computeSecondarySubRegs()
463 // Create sub-register index composition maps for the synthesized indices. in computeSecondarySubRegs()
467 for (SubRegMap::const_iterator SI = NewSubReg->SubRegs.begin(), in computeSecondarySubRegs()
468 SE = NewSubReg->SubRegs.end(); SI != SE; ++SI) { in computeSecondarySubRegs()
469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs()
471 PrintFatalError(TheDef->getLoc(), "No SubRegIndex for " + in computeSecondarySubRegs()
472 SI->second->getName() + " in " + getName()); in computeSecondarySubRegs()
473 NewIdx->addComposite(SI->first, SubIdx); in computeSecondarySubRegs()
484 // Make sure all sub-registers have been visited first, so the super-reg in computeSuperRegs()
488 I->second->computeSuperRegs(RegBank); in computeSuperRegs()
490 // Now add this as a super-register on all sub-registers. in computeSuperRegs()
491 // Also compute the TopoSigId in post-order. in computeSuperRegs()
497 Id.push_back(I->first->EnumValue); in computeSuperRegs()
498 Id.push_back(I->second->TopoSig); in computeSuperRegs()
501 if (!I->second->SuperRegs.empty() && I->second->SuperRegs.back() == this) in computeSuperRegs()
503 I->second->SuperRegs.push_back(this); in computeSuperRegs()
511 assert(SubRegsComplete && "Must precompute sub-registers"); in addSubRegsPreOrder()
515 SR->addSubRegsPreOrder(OSet, RegBank); in addSubRegsPreOrder()
517 // Add any secondary sub-registers that weren't part of the explicit tree. in addSubRegsPreOrder()
520 OSet.insert(I->second); in addSubRegsPreOrder()
533 //===----------------------------------------------------------------------===//
535 //===----------------------------------------------------------------------===//
537 // A RegisterTuples def is used to generate pseudo-registers from lists of
538 // sub-registers. We provide a SetTheory expander class that returns the new
543 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices"); in expand()
545 ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); in expand()
546 if (Dim != SubRegs->size()) in expand()
547 PrintFatalError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch"); in expand()
549 PrintFatalError(Def->getLoc(), in expand()
550 "Tuples must have at least 2 sub-registers"); in expand()
552 // Evaluate the sub-register lists to be zipped. in expand()
556 ST.evaluate(SubRegs->getElement(i), Lists[i], Def->getLoc()); in expand()
564 Record *RegisterCl = Def->getRecords().getClass("Register"); in expand()
577 Name += Reg->getName(); in expand()
580 unsigned(Reg->getValueAsInt("CostPerUse"))); in expand()
586 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords()); in expand()
589 // Copy Proto super-classes. in expand()
590 ArrayRef<std::pair<Record *, SMRange>> Supers = Proto->getSuperClasses(); in expand()
592 NewReg->addSuperClass(SuperPair.first, SuperPair.second); in expand()
595 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) { in expand()
596 RecordVal RV = Proto->getValues()[i]; in expand()
599 if (NewReg->getValue(RV.getNameInit())) in expand()
604 // Replace the sub-register list with Tuple. in expand()
616 // Composite registers are always covered by sub-registers. in expand()
623 NewReg->addValue(*Def->getValue(Field)); in expand()
631 if (const RecordVal *DefRV = RegisterCl->getValue(Field)) in expand()
632 NewReg->addValue(*DefRV); in expand()
637 NewReg->addValue(RV); in expand()
644 //===----------------------------------------------------------------------===//
646 //===----------------------------------------------------------------------===//
655 Name(R->getName()), in CodeGenRegisterClass()
657 EnumValue(-1), in CodeGenRegisterClass()
660 if (R->getName().size() > 9 && R->getName()[9] == '.') { in CodeGenRegisterClass()
662 R->setName("AnonRegClass_" + utostr(AnonCounter++)); in CodeGenRegisterClass()
665 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); in CodeGenRegisterClass()
668 if (!Type->isSubClassOf("ValueType")) in CodeGenRegisterClass()
669 PrintFatalError("RegTypes list member '" + Type->getName() + in CodeGenRegisterClass()
677 ListInit *AltOrders = R->getValueAsListInit("AltOrders"); in CodeGenRegisterClass()
678 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
681 for (unsigned i = 0, e = Elements->size(); i != e; ++i) { in CodeGenRegisterClass()
685 TopoSigs.set(Reg->getTopoSig()); in CodeGenRegisterClass()
691 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { in CodeGenRegisterClass()
692 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc()); in CodeGenRegisterClass()
699 PrintFatalError(R->getLoc(), " AltOrder register " + Reg->getName() + in CodeGenRegisterClass()
705 unsigned Size = R->getValueAsInt("Size"); in CodeGenRegisterClass()
707 Namespace = R->getValueAsString("Namespace"); in CodeGenRegisterClass()
709 SpillAlignment = R->getValueAsInt("Alignment"); in CodeGenRegisterClass()
710 CopyCost = R->getValueAsInt("CopyCost"); in CodeGenRegisterClass()
711 Allocatable = R->getValueAsBit("isAllocatable"); in CodeGenRegisterClass()
712 AltOrderSelect = R->getValueAsString("AltOrderSelect"); in CodeGenRegisterClass()
713 int AllocationPriority = R->getValueAsInt("AllocationPriority"); in CodeGenRegisterClass()
715 PrintFatalError(R->getLoc(), "AllocationPriority out of range [0,63]"); in CodeGenRegisterClass()
716 this->AllocationPriority = AllocationPriority; in CodeGenRegisterClass()
720 // Most properties will be inherited from the closest super-class after the
728 EnumValue(-1), in CodeGenRegisterClass()
735 TopoSigs.set(R->getTopoSig()); in CodeGenRegisterClass()
743 // The last super-class is the smallest one. in inheritProperties()
756 // super-class. in inheritProperties()
773 OS << ", " << R->getName(); in operator <<()
788 // RC is a sub-class of this class if it is a valid replacement for any
798 return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 && in testSubClass()
799 A->SpillSize <= B->SpillSize && in testSubClass()
800 std::includes(A->getMembers().begin(), A->getMembers().end(), in testSubClass()
801 B->getMembers().begin(), B->getMembers().end(), in testSubClass()
806 /// ordering that arranges all register classes before their sub-classes.
819 if (A->SpillSize < B->SpillSize) in TopoOrderRC()
821 if (A->SpillSize > B->SpillSize) in TopoOrderRC()
825 if (A->SpillAlignment < B->SpillAlignment) in TopoOrderRC()
827 if (A->SpillAlignment > B->SpillAlignment) in TopoOrderRC()
832 if (A->getMembers().size() > B->getMembers().size()) in TopoOrderRC()
834 if (A->getMembers().size() < B->getMembers().size()) in TopoOrderRC()
838 return StringRef(A->getName()) < B->getName(); in TopoOrderRC()
848 // Compute sub-classes of all register classes.
853 // Visit backwards so sub-classes are seen first. in computeSubClasses()
866 // SubRC is a sub-class. Grap all its sub-classes so we won't have to in computeSubClasses()
873 RC.SubClasses.set(I2->EnumValue); in computeSubClasses()
880 for (int s = 0, next_s = SC.find_first(); next_s != -1; in computeSubClasses()
882 std::advance(I, next_s - s); in computeSubClasses()
886 I->SuperClasses.push_back(&RC); in computeSubClasses()
890 // With the class hierarchy in place, let synthesized register classes inherit in computeSubClasses()
891 // properties from their closest super-class. The iteration order here can in computeSubClasses()
903 for (CodeGenRegisterClass *RC : FindI->second) in getSuperRegClasses()
904 Out.set(RC->EnumValue); in getSuperRegClasses()
918 //===----------------------------------------------------------------------===//
920 //===----------------------------------------------------------------------===//
928 // Read in the user-defined (named) sub-register indices. in CodeGenRegBank()
957 // register-register references. in CodeGenRegBank()
964 // causes some failures in MIPS - perhaps they have duplicate register name in CodeGenRegBank()
965 // entries? (or maybe there's a reason for it - I don't know much about this in CodeGenRegBank()
966 // code, just drive-by refactoring) in CodeGenRegBank()
968 std::make_pair(Reg.TheDef->getValueAsString("AsmName"), &Reg)); in CodeGenRegBank()
970 // Precompute all sub-register maps. in CodeGenRegBank()
971 // This will create Composite entries for all inferred sub-register indices. in CodeGenRegBank()
975 // Infer even more sub-registers by combining leading super-registers. in CodeGenRegBank()
980 // After the sub-register graph is complete, compute the topologically in CodeGenRegBank()
994 // Allocate user-defined register classes. in CodeGenRegBank()
1037 if (Record *Def = RC->getDef()) in addToMaps()
1046 // Create a synthetic sub-class if it is missing.
1051 // Synthetic sub-class has the same size and alignment as RC. in getOrCreateSubClass()
1052 CodeGenRegisterClass::Key K(Members, RC->SpillSize, RC->SpillAlignment); in getOrCreateSubClass()
1055 return FoundI->second; in getOrCreateSubClass()
1057 // Sub-class doesn't exist, create a new one. in getOrCreateSubClass()
1067 PrintFatalError(Def->getLoc(), "Not a known RegisterClass!"); in getRegClass()
1074 CodeGenSubRegIndex *Comp = A->compose(B); in getCompositeSubRegIndex()
1079 std::string Name = A->getName() + "_then_" + B->getName(); in getCompositeSubRegIndex()
1080 Comp = createSubRegIndex(Name, A->getNamespace()); in getCompositeSubRegIndex()
1081 A->addComposite(B, Comp); in getCompositeSubRegIndex()
1095 std::string Name = Parts.front()->getName(); in getConcatSubRegIndex()
1098 unsigned Size = Parts.front()->Size; in getConcatSubRegIndex()
1099 unsigned LastOffset = Parts.front()->Offset; in getConcatSubRegIndex()
1100 unsigned LastSize = Parts.front()->Size; in getConcatSubRegIndex()
1103 Name += Parts[i]->getName(); in getConcatSubRegIndex()
1104 Size += Parts[i]->Size; in getConcatSubRegIndex()
1105 if (Parts[i]->Offset != (LastOffset + LastSize)) in getConcatSubRegIndex()
1107 LastOffset = Parts[i]->Offset; in getConcatSubRegIndex()
1108 LastSize = Parts[i]->Size; in getConcatSubRegIndex()
1110 Idx = createSubRegIndex(Name, Parts.front()->getNamespace()); in getConcatSubRegIndex()
1111 Idx->Size = Size; in getConcatSubRegIndex()
1112 Idx->Offset = isContinuous ? Parts.front()->Offset : -1; in getConcatSubRegIndex()
1130 CodeGenSubRegIndex *Idx1 = i1->first; in computeComposites()
1131 CodeGenRegister *Reg2 = i1->second; in computeComposites()
1135 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
1139 CodeGenSubRegIndex *Idx2 = i2->first; in computeComposites()
1140 CodeGenRegister *Reg3 = i2->second; in computeComposites()
1146 assert(Idx3 && "Sub-register doesn't have an index"); in computeComposites()
1149 if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3)) in computeComposites()
1150 PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() + in computeComposites()
1151 " and " + Idx2->getQualifiedName() + in computeComposites()
1152 " compose ambiguously as " + Prev->getQualifiedName() + in computeComposites()
1153 " or " + Idx3->getQualifiedName()); in computeComposites()
1160 // sub-register index level. Each bit in the lane mask is like a register unit
1161 // class, and two lane masks will have a bit in common if two sub-register
1164 // Conservatively share a lane mask bit if two sub-register indices overlap in
1211 // Skip non-leaf subregisters. in computeSubRegLaneMasks()
1225 const CodeGenSubRegIndex *Composite = C->second; in computeSubRegLaneMasks()
1227 assert(Composite->getComposites().empty()); in computeSubRegLaneMasks()
1230 unsigned DstBit = Log2_32(Composite->LaneMask); in computeSubRegLaneMasks()
1231 int Shift = DstBit - SrcBit; in computeSubRegLaneMasks()
1261 // FIXME: What if ad-hoc aliasing introduces overlaps that aren't represented in computeSubRegLaneMasks()
1262 // by the sub-register graph? This doesn't occur in any known targets. in computeSubRegLaneMasks()
1267 // If some super-registers without CoveredBySubRegs use this index, we can in computeSubRegLaneMasks()
1303 // A Weight field caches the max per-register unit weight in each UberRegSet.
1320 // UberRegSets[0] is a special non-allocatable set.
1342 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue); in computeUberSets()
1345 AllocatableRegs.insert((*Regs.begin())->EnumValue); in computeUberSets()
1347 AllocatableRegs.insert((*I)->EnumValue); in computeUberSets()
1348 UberSetIDs.join(USetID, (*I)->EnumValue); in computeUberSets()
1351 // Combine non-allocatable regs. in computeUberSets()
1364 // Insert Registers into the UberSets formed by union-find. in computeUberSets()
1376 USet->Regs.push_back(&Reg); in computeUberSets()
1377 sortAndUniqueRegisters(USet->Regs); in computeUberSets()
1392 for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) { in computeUberWeights()
1408 if (I->Weight != MaxWeight) { in computeUberWeights()
1410 dbgs() << "UberSet " << I - UberSets.begin() << " Weight " << MaxWeight; in computeUberWeights()
1411 for (auto &Unit : I->Regs) in computeUberWeights()
1412 dbgs() << " " << Unit->getName(); in computeUberWeights()
1415 I->Weight = MaxWeight; in computeUberWeights()
1419 for (const auto R : I->Regs) { in computeUberWeights()
1420 if (R->getRegUnits().count() == 1 && R->getWeight(RegBank) == I->Weight) { in computeUberWeights()
1421 I->SingularDeterminants |= R->getRegUnits(); in computeUberWeights()
1429 // UberSet. Self-recursion processes the subregister tree in postorder so
1433 // - creates new adopted register units
1434 // - causes superregisters to inherit adopted units
1435 // - increases the weight of "singular" units
1436 // - induces recomputation of UberWeights.
1443 if (NormalRegs.test(Reg->EnumValue)) in normalizeWeight()
1445 NormalRegs.set(Reg->EnumValue); in normalizeWeight()
1448 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs(); in normalizeWeight()
1451 if (SRI->second == Reg) in normalizeWeight()
1452 continue; // self-cycles happen in normalizeWeight()
1454 Changed |= normalizeWeight(SRI->second, UberSets, RegSets, in normalizeWeight()
1460 if (Reg->inheritRegUnits(RegBank)) in normalizeWeight()
1466 unsigned RegWeight = Reg->getWeight(RegBank); in normalizeWeight()
1467 if (UberSet->Weight > RegWeight) { in normalizeWeight()
1471 unsigned AdjustUnit = *Reg->getRegUnits().begin(); in normalizeWeight()
1472 if (Reg->getRegUnits().count() != 1 in normalizeWeight()
1474 || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) { in normalizeWeight()
1476 AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight); in normalizeWeight()
1477 Reg->adoptRegUnit(AdjustUnit); in normalizeWeight()
1482 RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight); in normalizeWeight()
1490 NormalUnits |= Reg->getRegUnits(); in normalizeWeight()
1530 if (I->Units == Set.Units) in findRegUnitSet()
1546 /// special-purpose register subsets, such as tail-call and Thumb
1550 /// the allocatable registers and marking other classes as non-allocatable and
1551 /// (2) having a way to mark special purpose classes as "don't-care" classes for
1558 /// Q-tuples with ssub index 0 include all S regs but also include D16+. We
1639 dbgs() << " " << RegUnits[U].Roots[0]->getName(); in computeRegUnitSets()
1652 dbgs() << " " << RegUnits[U].Roots[0]->getName(); in computeRegUnitSets()
1695 DEBUG(dbgs() << "UnitSet " << RegUnitSets.size()-1 in computeRegUnitSets()
1698 dbgs() << " " << RegUnits[U].Roots[0]->getName(); in computeRegUnitSets()
1713 dbgs() << " " << RegUnits[U].Roots[0]->getName(); in computeRegUnitSets()
1719 int RCIdx = -1; in computeRegUnitSets()
1735 dbgs() << RegUnits[U].getRoots()[0]->getName() << " "; in computeRegUnitSets()
1790 CodeGenRegister *SubReg = S->second; in computeRegUnitLaneMasks()
1791 // Ignore non-leaf subregisters, their lane masks are fully covered by in computeRegUnitLaneMasks()
1793 if (SubReg->getSubRegs().size() != 0) in computeRegUnitLaneMasks()
1795 CodeGenSubRegIndex *SubRegIndex = S->first; in computeRegUnitLaneMasks()
1796 const CodeGenRegister *SubRegister = S->second; in computeRegUnitLaneMasks()
1797 unsigned LaneMask = SubRegIndex->LaneMask; in computeRegUnitLaneMasks()
1799 for (unsigned SUI : SubRegister->getRegUnits()) { in computeRegUnitLaneMasks()
1837 RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs; in computeDerivedInfo()
1838 RC.CoveredBySubRegs &= Reg->CoveredBySubRegs; in computeDerivedInfo()
1864 // Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
1879 const CodeGenRegister::Vec &Memb1 = RC1->getMembers(); in inferCommonSubClass()
1880 const CodeGenRegister::Vec &Memb2 = RC2->getMembers(); in inferCommonSubClass()
1891 // larger size for sub-classing. If they are equal, prefer RC1. in inferCommonSubClass()
1892 if (RC2->SpillSize > RC1->SpillSize || in inferCommonSubClass()
1893 (RC2->SpillSize == RC1->SpillSize && in inferCommonSubClass()
1894 RC2->SpillAlignment > RC1->SpillAlignment)) in inferCommonSubClass()
1898 RC1->getName() + "_and_" + RC2->getName()); in inferCommonSubClass()
1903 // Synthesize missing sub-classes for getSubClassWithSubReg().
1905 // Make sure that the set of registers in RC with a given SubIdx sub-register
1906 // form a register class. Update RC->SubClassWithSubReg.
1915 for (const auto R : RC->getMembers()) { in inferSubClassWithSubReg()
1916 const CodeGenRegister::SubRegMap &SRM = R->getSubRegs(); in inferSubClassWithSubReg()
1919 SRSets[I->first].push_back(R); in inferSubClassWithSubReg()
1933 if (I->second.size() == RC->getMembers().size()) { in inferSubClassWithSubReg()
1934 RC->setSubClassWithSubReg(&SubIdx, RC); in inferSubClassWithSubReg()
1939 getOrCreateSubClass(RC, &I->second, in inferSubClassWithSubReg()
1940 RC->getName() + "_with_" + I->first->getName()); in inferSubClassWithSubReg()
1941 RC->setSubClassWithSubReg(&SubIdx, SubRC); in inferSubClassWithSubReg()
1946 // Synthesize missing sub-classes of RC for getMatchingSuperRegClass().
1948 // Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X)
1963 if (RC->getSubClassWithSubReg(&SubIdx) != RC) in inferMatchingSuperRegClass()
1969 for (const auto Super : RC->getMembers()) { in inferMatchingSuperRegClass()
1970 const CodeGenRegister *Sub = Super->getSubRegs().find(&SubIdx)->second; in inferMatchingSuperRegClass()
1971 assert(Sub && "Missing sub-register"); in inferMatchingSuperRegClass()
1973 TopoSigs.set(Sub->getTopoSig()); in inferMatchingSuperRegClass()
1976 // Iterate over sub-register class candidates. Ignore classes created by in inferMatchingSuperRegClass()
2005 getOrCreateSubClass(RC, &SubSetVec, RC->getName() + "_with_" + in inferMatchingSuperRegClass()
2022 // Use one-before-the-end so it doesn't move forward when new elements are in computeInferredRegisterClasses()
2042 // to match old super-register classes with sub-register classes created in computeInferredRegisterClasses()
2056 /// getRegisterClassForRegister - Find the register class that contains the
2059 /// superset-subset relationship and the same set of types, return the
2077 if (RC.getValueTypes() != FoundRC->getValueTypes()) in getRegClassForRegister()
2091 if (FoundRC->hasSubClass(&RC)) in getRegClassForRegister()
2104 // First add Regs with all sub-registers. in computeCoveredRegisters()
2108 // Reg is new, add all sub-registers. in computeCoveredRegisters()
2109 // The pre-ordering is not important here. in computeCoveredRegisters()
2110 Reg->addSubRegsPreOrder(Set, *this); in computeCoveredRegisters()
2113 // Second, find all super-registers that are completely covered by the set. in computeCoveredRegisters()
2115 const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs(); in computeCoveredRegisters()
2118 if (!Super->CoveredBySubRegs || Set.count(Super)) in computeCoveredRegisters()
2120 // This new super-register is covered by its sub-registers. in computeCoveredRegisters()
2122 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs(); in computeCoveredRegisters()
2125 if (!Set.count(I->second)) { in computeCoveredRegisters()
2129 // All sub-registers in Set, add Super as well. in computeCoveredRegisters()
2130 // We will visit Super later to recheck its super-registers. in computeCoveredRegisters()
2139 BV.set(Set[i]->EnumValue); in computeCoveredRegisters()