Lines Matching +full:arr +full:- +full:flatten

4 Some notes about ir3, the compiler and machine-specific IR for the shader ISA introduced with Adren…
15 So the current compiler instead, in the frontend, generates a directed-acyclic-graph of instruction…
18 <https://github.com/freedreno/freedreno/wiki/A3xx-shader-instruction-set-architecture>`__.
21 ------------------
30     on other GL state (two-sided-color, render-to-alpha, etc) or render
31     stages (binning-pass vertex shader) different shader variants are
42 ------
44 …tions.  And additionally, for normal (non-const, etc) src registers, the ``IR3_REG_SSA`` flag is s…
70   inputdce198:<in2>:w -> instrdcedd0:<src0>
71   inputdce198:<in6>:w -> instrdcedd0:<src1>
73   inputdce198:<in1>:w -> instrdcec30:<src0>
74   inputdce198:<in5>:w -> instrdcec30:<src1>
76   inputdce198:<in0>:w -> instrdceb60:<src0>
77   inputdce198:<in4>:w -> instrdceb60:<src1>
78   instrdceb60:<dst0> -> instrdcec30:<src2>
79   instrdcec30:<dst0> -> instrdcedd0:<src2>
80   instrdcedd0:<dst0> -> instrdcf348:<src0>
82   instrdcedd0:<dst0> -> instrdcf400:<src0>
84   instrdcedd0:<dst0> -> instrdcf4b8:<src0>
86   instrdcf348:<dst0> -> outputdce198:<out0>:e
87   instrdcf400:<dst0> -> outputdce198:<out1>:e
88   instrdcf4b8:<dst0> -> outputdce198:<out2>:e
89   instrdcedd0:<dst0> -> outputdce198:<out3>:e
128     non-SSA sources (consts, etc), but includes virtual sources (such as the
136 .. code-block:: c
152     Used for shader inputs (registers configured in the command-stream
211     sam -> collect [label="regs[1]"];
212     collect -> coord_x [label="regs[1]"];
213     collect -> coord_y [label="regs[2]"];
214     coord_x -> coord_y [label="right",style=dotted];
215     coord_y -> coord_x [label="left",style=dotted];
237     A -> split_0;
238     B -> split_1;
239     C -> split_2;
241     split_0 -> sam;
243     split_1 -> sam;
245     split_2 -> sam;
246     split_0 -> split_1 [label="right",style=dotted];
247     split_1 -> split_0 [label="left",style=dotted];
248     split_1 -> split_2 [label="right",style=dotted];
249     split_2 -> split_1 [label="left",style=dotted];
288     add -> mova;
289     add -> sub;
290     add -> const [label="off=2"];
314 …0000:0000:002:  mov.u32u32 ssa_21, arr[id=1, offset=0, size=4, ssa_12], address=_[0000:0000:002:  …
315 …0000:0000:002:  mov.u32u32 ssa_22, arr[id=1, offset=1, size=4, ssa_12], address=_[0000:0000:002:  …
318 Array writes write to the array in ``instr->regs[0]->array.id``.  A NIR indirect
333 …0000:0000:001:  mov.u32u32 arr[id=1, offset=0, size=4, ssa_17], c2.y, address=_[0000:0000:002:  mo…
334 …0000:0000:004:  mov.u32u32 arr[id=1, offset=1, size=4, ssa_31], c2.z, address=_[0000:0000:002:  mo…
339 ir3 array accesses in the DAG get serialized by the ``instr->barrier_class`` and
343 -------------
345 After the frontend has generated the use-def graph of instructions, they are run through various pa…
354 Flatten  section in Shader Passes
365 …es.  And the CP pass simply removes all simple ``mov``\s (i.e. src-type is same as dst-type, no ab…
367 The eventual plan is to invert that, with the front-end inserting no ``mov``\s and CP legalize thin…