Lines Matching +full:vega +full:- +full:runtime
71 storage_task_payload = 0x20, /* Task-Mesh payload */
81 * atomics/control_barriers/sendmsg_gs_done/position-primitive-export before the barrier */
85 * atomics/control_barriers/sendmsg_gs_done/position-primitive-export after the barrier */
133 /* Also check storage so that zero-initialized memory_sync_info can be in can_reorder()
171 /* if false, optimizations which may remove infs/nan/-0.0 can be done */
273 /* byte-sized register class */
401 static constexpr PhysReg flat_scr_lo{102}; /* GFX8-GFX9, encoded differently on GFX6-7 */
402 static constexpr PhysReg flat_scr_hi{103}; /* GFX8-GFX9, encoded differently on GFX6-7 */
405 static constexpr PhysReg tba{108}; /* GFX6-GFX8 */
406 static constexpr PhysReg tma{110}; /* GFX6-GFX8 */
423 static constexpr PhysReg pops_exiting_wave_id{239}; /* GFX9-GFX10.3 */
460 /* 8-bit constant */
463 /* 8-bit constants are only used for copies and copies from any 8-bit in c8()
475 /* 16-bit constant */
485 else if (v >= 0xFFF0) /* [-16 .. -1] */ in c16()
486 op.setFixed(PhysReg{(unsigned)(192 - (int16_t)v)}); in c16()
489 else if (v == 0xB800) /* -0.5 */ in c16()
493 else if (v == 0xBC00) /* -1.0 */ in c16()
497 else if (v == 0xC000) /* -2.0 */ in c16()
501 else if (v == 0xC400) /* -4.0 */ in c16()
510 /* 32-bit constant */
513 /* 64-bit constant */
523 } else if (v >= 0xFFFFFFFFFFFFFFF0) { /* [-16 .. -1] */ in c64()
525 op.setFixed(PhysReg{192 - (uint32_t)v}); in c64()
529 } else if (v == 0xBFE0000000000000) { /* -0.5 */ in c64()
535 } else if (v == 0xBFF0000000000000) { /* -1.0 */ in c64()
541 } else if (v == 0xC000000000000000) { /* -2.0 */ in c64()
547 } else if (v == 0xC010000000000000) { /* -4.0 */ in c64()
555 "attempt to create a unrepresentable 64-bit literal constant"); in c64()
560 /* 32-bit constant stored as a 32-bit or 64-bit operand */
570 else if (v >= 0xFFFFFFF0) /* [-16 .. -1] */ in c32_or_c64()
571 op.setFixed(PhysReg{192 - v}); in c32_or_c64()
574 else if (v == 0xbf000000) /* -0.5 */ in c32_or_c64()
578 else if (v == 0xbf800000) /* -1.0 */ in c32_or_c64()
582 else if (v == 0xc0000000) /* -2.0 */ in c32_or_c64()
586 else if (v == 0xc0800000) /* -4.0 */ in c32_or_c64()
589 assert(!is64bit && "attempt to create a 64-bit literal constant"); in c32_or_c64()
664 return val >= 0xFFFFFFFFFFFFFFF0 || val <= 64 || /* [-16 .. 64] */
666 val == 0xBFE0000000000000 || /* -0.5 */
668 val == 0xBFF0000000000000 || /* -1.0 */
670 val == 0xC000000000000000 || /* -2.0 */
672 val == 0xC010000000000000; /* -4.0 */
714 isFixed_ = reg != unsigned(-1); in setFixed()
735 return reg_ - 128; in constantValue64()
737 return 0xFFFFFFFFFFFFFFFF - (reg_ - 193); in constantValue64()
751 unreachable("invalid register for 64-bit constant"); in constantValue64()
762 if (bytes() == 2 && int16_t(data_.i) >= -16 && int16_t(data_.i) <= 64 && !isLiteral()) in constantValue16()
764 16; /* 16-bit inline integers are sign-extended, even with fp16 instrs */ in constantValue16()
856 /* can't initialize bit-fields in c++11, so work around using a union */
934 /* can't initialize bit-fields in c++11, so work around using a union */
1338 * Operand(0): SBASE - SGPR-pair which provides base address
1339 * Operand(1): Offset - immediate (un)signed offset or SGPR
1340 * Operand(2) / Definition(0): SDATA - SGPR for read / write result
1341 * Operand(n-1): SOffset - SGPR offset (Vega only)
1350 bool nv : 1; /* VEGA only: Non-volatile */
1464 * Sub-Dword Addressing Format:
1489 * Operand(0): ADDR - VGPR which supplies the address.
1490 * Operand(1): DATA0 - First data VGPR.
1491 * Operand(2): DATA1 - Second data VGPR.
1492 * Operand(n-1): M0 - LDS size.
1493 * Definition(0): VDST - Destination VGPR when results returned to VGPRs.
1508 * Definition(0): VDST - Destination VGPR
1520 * Vector Memory Untyped-buffer Instructions
1521 * Operand(0): SRSRC - Specifies which SGPR supplies T# (resource constant)
1522 * Operand(1): VADDR - Address source. Can carry an index and/or offset
1523 * Operand(2): SOFFSET - SGPR to supply unsigned byte offset. (SGPR, M0, or inline constant)
1524 * Operand(3) / Definition(0): VDATA - Vector GPR for write result / read data
1531 bool addr64 : 1; /* SI, CIK: Address size is 64-bit */
1536 bool lds : 1; /* Return read-data to LDS instead of VGPRs */
1538 uint16_t offset : 12; /* Unsigned byte offset - 12 bit */
1546 * Vector Memory Typed-buffer Instructions
1547 * Operand(0): SRSRC - Specifies which SGPR supplies T# (resource constant)
1548 * Operand(1): VADDR - Address source. Can carry an index and/or offset
1549 * Operand(2): SOFFSET - SGPR to supply unsigned byte offset. (SGPR, M0, or inline constant)
1550 * Operand(3) / Definition(0): VDATA - Vector GPR for write result / read data
1565 uint16_t offset; /* Unsigned byte offset - 12 bit */
1571 * Operand(0) SRSRC - Scalar GPR that specifies the resource constant.
1572 * Operand(1): SSAMP - Scalar GPR that specifies sampler constant.
1573 * Operand(2): VDATA - Vector GPR for write data or zero if TFE/LWE=1.
1574 * Operand(3): VADDR - Address source. Can carry an offset or an index.
1575 * Definition(0): VDATA - Vector GPR for read result.
1582 bool unrm : 1; /* Force address to be un-normalized */
1590 bool a16 : 1; /* VEGA, NAVI: Address components are 16-bits */
1591 bool d16 : 1; /* Convert 32-bit data to 16-bit data */
1616 int16_t offset; /* Vega/Navi only */
1642 * For conditional branches, target[1] contains the fall-through alternative.
1661 // clang-format off
1676 // clang-format on
1708 if (this->isSDWA() && idx0 != idx1) { in swapOperands()
1710 std::swap(this->sdwa().sel[0], this->sdwa().sel[1]); in swapOperands()
1713 std::swap(this->operands[idx0], this->operands[idx1]); in swapOperands()
1714 this->neg[idx0].swap(this->neg[idx1]); in swapOperands()
1715 this->abs[idx0].swap(this->abs[idx1]); in swapOperands()
1716 this->opsel[idx0].swap(this->opsel[idx1]); in swapOperands()
1717 this->opsel_lo[idx0].swap(this->opsel_lo[idx1]); in swapOperands()
1718 this->opsel_hi[idx0].swap(this->opsel_hi[idx1]); in swapOperands()
1724 /* Don't yet free any instructions. They will be de-allocated
1739 void* data = instruction_buffer->allocate(size, alignof(uint32_t)); in create_instruction()
1743 inst->opcode = opcode; in create_instruction()
1744 inst->format = format; in create_instruction()
1746 uint16_t operands_offset = sizeof(T) - offsetof(Instruction, operands); in create_instruction()
1747 inst->operands = aco::span<Operand>(operands_offset, num_operands); in create_instruction()
1748 uint16_t definitions_offset = (char*)inst->operands.end() - (char*)&inst->definitions; in create_instruction()
1749 inst->definitions = aco::span<Definition>(definitions_offset, num_definitions); in create_instruction()
1761 const VALU_instruction& vop3p = this->valu(); in usesModifiers()
1762 /* opsel_hi must be 1 to not be considered a modifier - even for constants */ in usesModifiers()
1766 const VALU_instruction& vop3 = this->valu(); in usesModifiers()
1775 return instr->opcode == aco_opcode::p_phi || instr->opcode == aco_opcode::p_linear_phi; in is_phi()
1789 if (instr->definitions.empty() || instr->isBranch() || instr->opcode == aco_opcode::p_startpgm || in is_dead()
1790 instr->opcode == aco_opcode::p_init_scratch || in is_dead()
1791 instr->opcode == aco_opcode::p_dual_src_export_gfx11) in is_dead()
1794 if (std::any_of(instr->definitions.begin(), instr->definitions.end(), in is_dead()
1887 constexpr RegisterDemand operator-(const RegisterDemand other) const noexcept
1889 return RegisterDemand(vgpr - other.vgpr, sgpr - other.sgpr);
1899 constexpr RegisterDemand& operator-=(const RegisterDemand other) noexcept
1901 vgpr -= other.vgpr;
1902 sgpr -= other.sgpr;
1915 constexpr RegisterDemand& operator-=(const Temp t) noexcept
1918 sgpr -= t.size();
1920 vgpr -= t.size();
1943 int32_t logical_idom = -1;
1944 int32_t linear_idom = -1;
2028 /* pre-GFX9 */
2239 * Returns true if print_asm can disassemble the given program for the current build/runtime
2298 /* number of sgprs that need to be allocated but might notbe addressable as s0-s105 */