cpu-specific-build-macros.rst - OpenGrok cross reference for /external/trusty/arm-trusted-firmware/docs/design/cpu-specific-build-macros.rst

Lines Matching full:needs
76    CPU. This needs to be enabled for all revisions of the CPU.
81    CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
84    CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
89    CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
92    CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
97    CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
102    CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
105    CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
108    CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
111    CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
114    link time to Cortex-A53 CPU. This needs to be enabled for some variants of
119    CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
124    to Cortex-A53 CPU.  This needs to be enabled for some variants of revision
141    CPU. This needs to be enabled only for revision r0p0 of the CPU.
144    CPU. This needs to be enabled only for revision r0p0 of the CPU.
147    CPU. This needs to be enabled only for revision r0p0 of the CPU.
150    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
153    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
156    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
164    CPU. This needs to be enabled only for revision r0p0 of the CPU.
167    CPU. This needs to be enabled only for revision r0p0 of the CPU.
170    CPU. This needs to be enabled only for revision r0p0 of the CPU.
173    CPU. This needs to be enabled only for revision r0p0 of the CPU.
176    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
179    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
182    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
185    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
188    CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
191    CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
194    CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
202    CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
210    CPU. This needs to be enabled only for revision r0p0 of the CPU.
213    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
218    CPU. This needs to be enabled only for revision r0p0 of the CPU.
221     CPU. This needs to be enabled only for revision r0p0 of the CPU.
226    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
229    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
232    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
235    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
238    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
241    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
244    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
247    CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
255    CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
258    CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.
261    CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is
267    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
270    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
273    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
276    CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
279    CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
282     CPU. This needs to be enabled for revisions <= r1p1 of the CPU.
285     CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
290    CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
293    CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
296    CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
300    CPU. This needs to be enabled for revisions r0p0 and r1p0.
303    CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
306    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It
310    CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue
314    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
318    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
323    interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1
327    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
331    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
335    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
341    Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1.
345   Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
349   Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
353   Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
358   an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and
364   Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is
368   Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is
372   Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
376   Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
380   Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
384   Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
389   an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2
393   Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
397   Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2.
403    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
406    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
409    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
414    CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.
417    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
420    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
423    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
426    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
429    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
432    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
435    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
438    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
441    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
444    CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU.
447    CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
450    CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
454    CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is
460    CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
464    CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
468    CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
472    CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
476    CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
479    CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
483    CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
488    CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
492    CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
496    CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
501    CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of
505    CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
510    interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1.
514    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the
518    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the
522    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the
528    CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still
533    IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed
537    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
541    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
545    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
549    CPU, this affects all configurations. This needs to be enabled for revisions
555    Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
559    Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
563    Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
567    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
571    Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
575    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
579    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
583    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
587    Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU
591    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
595    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
599    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
603    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
607    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
612    interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and
616    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
620    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
626    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
629    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
632    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
635    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
638    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
641    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
644    CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open.
647    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
650    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
653    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
656    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
659    CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
663    CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
667    CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU,
671    CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open.
674    CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
678    CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
682    CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
687    interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
691    CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
697    CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
701    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU,
705    CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
708    CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
712    CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
716    CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
720    CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed
724    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
728    CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU
733    This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is
737    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
741    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
747   CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of
751   Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0
755   CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
759   Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
765    Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is
769    Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1,
773    Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and
777    Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed
782    Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is
787    Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
792    Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
796    Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
800    Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
804    Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2,
808    Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2,
812    Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2,
819    IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed
875    flag enforces this behaviour. This needs to be enabled only for revisions
879    ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be