1 /* 2 * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above 10 * copyright notice, this list of conditions and the following 11 * disclaimer in the documentation and/or other materials provided 12 * with the distribution. 13 * * Neither the name of The Linux Foundation nor the names of its 14 * contributors may be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 24 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 26 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 27 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef __DRM_INTERFACE_H__ 31 #define __DRM_INTERFACE_H__ 32 33 #include <map> 34 #include <string> 35 #include <utility> 36 #include <vector> 37 #include <array> 38 39 #include "xf86drm.h" 40 #include "xf86drmMode.h" 41 #include <drm/msm_drm.h> 42 #include <drm/msm_drm_pp.h> 43 44 #ifdef KERNEL_5_4 45 #include <drm/sde_drm.h> 46 #endif 47 48 namespace sde_drm { 49 50 typedef std::map<std::pair<uint32_t, uint64_t>, float> CompRatioMap; 51 52 /* 53 * Drm Atomic Operation Codes 54 */ 55 enum struct DRMOps { 56 /* 57 * Op: Sets plane source crop 58 * Arg: uint32_t - Plane ID 59 * DRMRect - Source Rectangle 60 */ 61 PLANE_SET_SRC_RECT, 62 /* 63 * Op: Sets plane destination rect 64 * Arg: uint32_t - Plane ID 65 * DRMRect - Dst Rectangle 66 */ 67 PLANE_SET_DST_RECT, 68 /* 69 * Op: Sets plane exclusion rect 70 * Arg: uint32_t - Plane ID 71 * drm_clip_rect - Exclusion Rectangle 72 */ 73 PLANE_SET_EXCL_RECT, 74 /* 75 * Op: Sets plane zorder 76 * Arg: uint32_t - Plane ID 77 * uint32_t - zorder 78 */ 79 PLANE_SET_ZORDER, 80 /* 81 * Op: Sets plane rotation flags 82 * Arg: uint32_t - Plane ID 83 * uint32_t - bit mask of rotation flags (See drm_mode.h for enums) 84 */ 85 PLANE_SET_ROTATION, 86 /* 87 * Op: Sets plane alpha 88 * Arg: uint32_t - Plane ID 89 * uint32_t - alpha value 90 */ 91 PLANE_SET_ALPHA, 92 /* 93 * Op: Sets the blend type 94 * Arg: uint32_t - Plane ID 95 * uint32_t - blend type (see DRMBlendType) 96 */ 97 PLANE_SET_BLEND_TYPE, 98 /* 99 * Op: Sets horizontal decimation 100 * Arg: uint32_t - Plane ID 101 * uint32_t - decimation factor 102 */ 103 PLANE_SET_H_DECIMATION, 104 /* 105 * Op: Sets vertical decimation 106 * Arg: uint32_t - Plane ID 107 * uint32_t - decimation factor 108 */ 109 PLANE_SET_V_DECIMATION, 110 /* 111 * Op: Sets source config flags 112 * Arg: uint32_t - Plane ID 113 * uint32_t - flags to enable or disable a specific op. E.g. deinterlacing 114 */ 115 PLANE_SET_SRC_CONFIG, 116 /* 117 * Op: Sets frame buffer ID for plane. Set together with CRTC. 118 * Arg: uint32_t - Plane ID 119 * uint32_t - Framebuffer ID 120 */ 121 PLANE_SET_FB_ID, 122 /* 123 * Op: Sets the crtc for this plane. Set together with FB_ID. 124 * Arg: uint32_t - Plane ID 125 * uint32_t - CRTC ID 126 */ 127 PLANE_SET_CRTC, 128 /* 129 * Op: Sets acquire fence for this plane's buffer. Set together with FB_ID, CRTC. 130 * Arg: uint32_t - Plane ID 131 * uint32_t - Input fence 132 */ 133 PLANE_SET_INPUT_FENCE, 134 /* 135 * Op: Sets scaler config on this plane. 136 * Arg: uint32_t - Plane ID 137 * uint64_t - Address of the scaler config object (version based) 138 */ 139 PLANE_SET_SCALER_CONFIG, 140 /* 141 * Op: Sets FB Secure mode for this plane. 142 * Arg: uint32_t - Plane ID 143 * uint32_t - Value of the FB Secure mode. 144 */ 145 PLANE_SET_FB_SECURE_MODE, 146 /* 147 * Op: Sets csc config on this plane. 148 * Arg: uint32_t - Plane ID 149 * uint32_t* - pointer to csc type 150 */ 151 PLANE_SET_CSC_CONFIG, 152 /* 153 * Op: Sets multirect mode on this plane. 154 * Arg: uint32_t - Plane ID 155 * uint32_t - multirect mode 156 */ 157 PLANE_SET_MULTIRECT_MODE, 158 /* 159 * Op: Sets sspp layout on this plane. 160 * Arg: uint32_t - Plane ID 161 * uint32_t - SSPP Layout Index 162 */ 163 PLANE_SET_SSPP_LAYOUT, 164 /* 165 * Op: Sets rotator output frame buffer ID for plane. 166 * Arg: uint32_t - Plane ID 167 * uint32_t - Framebuffer ID 168 */ 169 PLANE_SET_ROT_FB_ID, 170 /* 171 * Op: Sets inverse pma mode on this plane. 172 * Arg: uint32_t - Plane ID 173 * uint32_t - enable/disable inverse pma. 174 */ 175 PLANE_SET_INVERSE_PMA, 176 /* 177 * Op: Sets csc config on this plane. 178 * Arg: uint32_t - Plane ID 179 * uint64_t - Address of the csc config object(version based) 180 */ 181 PLANE_SET_DGM_CSC_CONFIG, 182 /* 183 * Op: Sets SSPP Feature 184 * Arg: uint32_t - Plane ID 185 * DRMPPFeatureInfo * - PP feature data pointer 186 */ 187 PLANE_SET_POST_PROC, 188 /* 189 * Op: Activate or deactivate a CRTC 190 * Arg: uint32_t - CRTC ID 191 * uint32_t - 1 to enable, 0 to disable 192 */ 193 CRTC_SET_ACTIVE, 194 /* 195 * Op: Sets display mode 196 * Arg: uint32_t - CRTC ID 197 * drmModeModeInfo* - Pointer to display mode 198 */ 199 CRTC_SET_MODE, 200 /* 201 * Op: Sets an offset indicating when a release fence should be signalled. 202 * Arg: uint32_t - offset 203 * 0: non-speculative, default 204 * 1: speculative 205 */ 206 CRTC_SET_OUTPUT_FENCE_OFFSET, 207 /* 208 * Op: Sets overall SDE core clock 209 * Arg: uint32_t - CRTC ID 210 * uint32_t - core_clk 211 */ 212 CRTC_SET_CORE_CLK, 213 /* 214 * Op: Sets MNOC bus average bandwidth 215 * Arg: uint32_t - CRTC ID 216 * uint32_t - core_ab 217 */ 218 CRTC_SET_CORE_AB, 219 /* 220 * Op: Sets MNOC bus instantaneous bandwidth 221 * Arg: uint32_t - CRTC ID 222 * uint32_t - core_ib 223 */ 224 CRTC_SET_CORE_IB, 225 /* 226 * Op: Sets LLCC Bus average bandwidth 227 * Arg: uint32_t - CRTC ID 228 * uint32_t - llcc_ab 229 */ 230 CRTC_SET_LLCC_AB, 231 /* 232 * Op: Sets LLCC Bus instantaneous bandwidth 233 * Arg: uint32_t - CRTC ID 234 * uint32_t - llcc_ib 235 */ 236 CRTC_SET_LLCC_IB, 237 /* 238 * Op: Sets DRAM bus average bandwidth 239 * Arg: uint32_t - CRTC ID 240 * uint32_t - dram_ab 241 */ 242 CRTC_SET_DRAM_AB, 243 /* 244 * Op: Sets DRAM bus instantaneous bandwidth 245 * Arg: uint32_t - CRTC ID 246 * uint32_t - dram_ib 247 */ 248 CRTC_SET_DRAM_IB, 249 /* 250 * Op: Sets Rotator BW for inline rotation 251 * Arg: uint32_t - CRTC ID 252 * uint32_t - rot_bw 253 */ 254 CRTC_SET_ROT_PREFILL_BW, 255 /* 256 * Op: Sets rotator clock for inline rotation 257 * Arg: uint32_t - CRTC ID 258 * uint32_t - rot_clk 259 */ 260 CRTC_SET_ROT_CLK, 261 /* 262 * Op: Sets destination scalar data 263 * Arg: uint32_t - CRTC ID 264 * uint64_t - Pointer to destination scalar data 265 */ 266 CRTC_SET_DEST_SCALER_CONFIG, 267 /* 268 * Op: Returns release fence for this frame. Should be called after Commit() on 269 * DRMAtomicReqInterface. 270 * Arg: uint32_t - CRTC ID 271 * int * - Pointer to an integer that will hold the returned fence 272 */ 273 CRTC_GET_RELEASE_FENCE, 274 /* 275 * Op: Sets PP feature 276 * Arg: uint32_t - CRTC ID 277 * DRMPPFeatureInfo * - PP feature data pointer 278 */ 279 CRTC_SET_POST_PROC, 280 /* 281 * Op: Sets CRTC ROIs. 282 * Arg: uint32_t - CRTC ID 283 * uint32_t - number of ROIs 284 * DRMRect * - Array of CRTC ROIs 285 */ 286 CRTC_SET_ROI, 287 /* 288 * Op: Sets Security level for CRTC. 289 * Arg: uint32_t - CRTC ID 290 * uint32_t - Security level 291 */ 292 CRTC_SET_SECURITY_LEVEL, 293 /* 294 * Op: sets solid fill stages 295 * Arg: uint32_t - CRTC ID 296 * Vector of DRMSolidfillStage 297 */ 298 CRTC_SET_SOLIDFILL_STAGES, 299 /* 300 * Op: Sets idle timeout. 301 * Arg: uint32_t - CRTC ID 302 * uint32_t - idle timeout in ms 303 */ 304 CRTC_SET_IDLE_TIMEOUT, 305 /* 306 * Op: Sets Capture mode for Concurrent Writeback feature. 307 * Arg: uint32_t - CRTC ID 308 * uint32_t - Capture mode 309 */ 310 CRTC_SET_CAPTURE_MODE, 311 /* 312 * Op: Sets Idle PC state for CRTC. 313 * Arg: uint32_t - CRTC ID 314 * uint32_t - idle pc state 315 */ 316 CRTC_SET_IDLE_PC_STATE, 317 /* 318 * Op: Returns retire fence for this commit. Should be called after Commit() on 319 * DRMAtomicReqInterface. 320 * Arg: uint32_t - Connector ID 321 * int * - Pointer to an integer that will hold the returned fence 322 */ 323 CONNECTOR_GET_RETIRE_FENCE, 324 /* 325 * Op: Sets writeback connector destination rect 326 * Arg: uint32_t - Connector ID 327 * DRMRect - Dst Rectangle 328 */ 329 CONNECTOR_SET_OUTPUT_RECT, 330 /* 331 * Op: Sets frame buffer ID for writeback connector. 332 * Arg: uint32_t - Connector ID 333 * uint32_t - Framebuffer ID 334 */ 335 CONNECTOR_SET_OUTPUT_FB_ID, 336 /* 337 * Op: Sets power mode for connector. 338 * Arg: uint32_t - Connector ID 339 * uint32_t - Power Mode 340 */ 341 CONNECTOR_SET_POWER_MODE, 342 /* 343 * Op: Sets panel ROIs. 344 * Arg: uint32_t - Connector ID 345 * uint32_t - number of ROIs 346 * DRMRect * - Array of Connector ROIs 347 */ 348 CONNECTOR_SET_ROI, 349 /* 350 * Op: Sets the connector to autorefresh mode. 351 * Arg: uint32_t - Connector ID 352 * uint32_t - Enable-1, Disable-0 353 */ 354 CONNECTOR_SET_AUTOREFRESH, 355 /* 356 * Op: Set FB secure mode for Writeback connector. 357 * Arg: uint32_t - Connector ID 358 * uint32_t - FB Secure mode 359 */ 360 CONNECTOR_SET_FB_SECURE_MODE, 361 /* 362 * Op: Sets a crtc id to this connector 363 * Arg: uint32_t - Connector ID 364 * uint32_t - CRTC ID 365 */ 366 CONNECTOR_SET_CRTC, 367 /* 368 * Op: Sets PP feature 369 * Arg: uint32_t - Connector ID 370 * DRMPPFeatureInfo * - PP feature data pointer 371 */ 372 CONNECTOR_SET_POST_PROC, 373 /* 374 * Op: Sets connector hdr metadata 375 * Arg: uint32_t - Connector ID 376 * drm_msm_ext_hdr_metadata - hdr_metadata 377 */ 378 CONNECTOR_SET_HDR_METADATA, 379 /* 380 * Op: Cache Dpps features. 381 * Arg: uint32_t - Object ID 382 uint32_t - Feature ID 383 * uint64_t - Pointer to feature config data 384 */ 385 DPPS_CACHE_FEATURE, 386 /* 387 * Op: Commit Dpps features. 388 * Arg: drmModeAtomicReq - Atomic request 389 */ 390 DPPS_COMMIT_FEATURE, 391 /* 392 * Op: Commit panel features. 393 * Arg: drmModeAtomicReq - Atomic request 394 */ 395 COMMIT_PANEL_FEATURES, 396 /* 397 * Op: Sets qsync mode on connector 398 * Arg: uint32_t - Connector ID 399 * uint32_t - qsync mode 400 */ 401 CONNECTOR_SET_QSYNC_MODE, 402 /* 403 * Op: Sets topology control on this connector 404 * Arg: uint32_t - Connector ID 405 * uint32_t - Topology control bit-mask 406 */ 407 CONNECTOR_SET_TOPOLOGY_CONTROL, 408 /* 409 * Op: Sets frame trigger mode on this connector 410 * Arg: uint32_t - Connector ID 411 * uint32_t - Frame trigger mode 412 */ 413 CONNECTOR_SET_FRAME_TRIGGER, 414 /* 415 * Op: Sets colorspace on DP connector 416 * Arg: uint32_t - Connector ID 417 * uint32_t - colorspace value bit-mask 418 */ 419 CONNECTOR_SET_COLORSPACE, 420 }; 421 422 enum struct DRMRotation { 423 FLIP_H = 0x1, 424 FLIP_V = 0x2, 425 ROT_180 = FLIP_H | FLIP_V, 426 ROT_90 = 0x4, 427 }; 428 429 enum struct DRMPowerMode { 430 ON, 431 DOZE, 432 DOZE_SUSPEND, 433 OFF, 434 }; 435 436 enum struct DRMBlendType { 437 UNDEFINED = 0, 438 OPAQUE = 1, 439 PREMULTIPLIED = 2, 440 COVERAGE = 3, 441 }; 442 443 enum struct DRMSrcConfig { 444 DEINTERLACE = 0, 445 }; 446 447 enum struct DRMIdlePCState { 448 NONE, 449 ENABLE, 450 DISABLE, 451 }; 452 453 454 /* Display type to identify a suitable connector */ 455 enum struct DRMDisplayType { 456 PERIPHERAL, 457 TV, 458 VIRTUAL, 459 }; 460 461 struct DRMRect { 462 uint32_t left; // Left-most pixel coordinate. 463 uint32_t top; // Top-most pixel coordinate. 464 uint32_t right; // Right-most pixel coordinate. 465 uint32_t bottom; // Bottom-most pixel coordinate. 466 }; 467 468 //------------------------------------------------------------------------ 469 // DRM Info Query Types 470 //------------------------------------------------------------------------ 471 472 enum struct QSEEDVersion { 473 V1, 474 V2, 475 V3, 476 V3LITE, 477 }; 478 479 /* QSEED3 Step version */ 480 enum struct QSEEDStepVersion { 481 V2, 482 V3, 483 V4, 484 V3LITE_V4, 485 V3LITE_V5, 486 }; 487 488 enum struct SmartDMARevision { 489 V1, 490 V2, 491 V2p5 492 }; 493 494 /* Inline Rotation version */ 495 enum struct InlineRotationVersion { 496 kInlineRotationNone, 497 kInlineRotationV1, 498 kInlineRotationV2, 499 }; 500 501 /* Per CRTC Resource Info*/ 502 struct DRMCrtcInfo { 503 bool has_src_split; 504 bool has_hdr; 505 uint32_t max_blend_stages; 506 uint32_t max_solidfill_stages; 507 QSEEDVersion qseed_version; 508 SmartDMARevision smart_dma_rev; 509 float ib_fudge_factor; 510 float clk_fudge_factor; 511 uint32_t dest_scale_prefill_lines; 512 uint32_t undersized_prefill_lines; 513 uint32_t macrotile_prefill_lines; 514 uint32_t nv12_prefill_lines; 515 uint32_t linear_prefill_lines; 516 uint32_t downscale_prefill_lines; 517 uint32_t extra_prefill_lines; 518 uint32_t amortized_threshold; 519 uint64_t max_bandwidth_low; 520 uint64_t max_bandwidth_high; 521 uint32_t max_sde_clk; 522 CompRatioMap comp_ratio_rt_map; 523 CompRatioMap comp_ratio_nrt_map; 524 uint32_t hw_version; 525 uint32_t dest_scaler_count = 0; 526 uint32_t max_dest_scaler_input_width = 0; 527 uint32_t max_dest_scaler_output_width = 0; 528 uint32_t max_dest_scale_up = 1; 529 uint32_t min_prefill_lines = 0; 530 int secure_disp_blend_stage = -1; 531 bool concurrent_writeback = false; 532 uint32_t vig_limit_index = 0; 533 uint32_t dma_limit_index = 0; 534 uint32_t scaling_limit_index = 0; 535 uint32_t rotation_limit_index = 0; 536 uint32_t line_width_constraints_count = 0; 537 std::vector< std::pair <uint32_t, uint32_t> > line_width_limits; 538 uint32_t num_mnocports; 539 uint32_t mnoc_bus_width; 540 bool use_baselayer_for_stage = false; 541 bool has_micro_idle = false; 542 uint32_t ubwc_version = 1; 543 uint64_t rc_total_mem_size = 0; 544 }; 545 546 enum struct DRMPlaneType { 547 // Has CSC and scaling capability 548 VIG = 0, 549 // Has scaling capability but no CSC 550 RGB, 551 // No scaling support 552 DMA, 553 // Supports a small dimension and doesn't use a CRTC stage 554 CURSOR, 555 MAX, 556 }; 557 558 enum struct DRMTonemapLutType { 559 DMA_1D_GC, 560 DMA_1D_IGC, 561 VIG_1D_IGC, 562 VIG_3D_GAMUT, 563 }; 564 565 struct DRMPlaneTypeInfo { 566 DRMPlaneType type; 567 uint32_t master_plane_id; 568 // FourCC format enum and modifier 569 std::vector<std::pair<uint32_t, uint64_t>> formats_supported; 570 uint32_t max_linewidth; 571 uint32_t max_scaler_linewidth; 572 uint32_t max_rotation_linewidth; // inline rotation limitation 573 uint32_t max_upscale; 574 uint32_t max_downscale; 575 uint32_t max_horizontal_deci; 576 uint32_t max_vertical_deci; 577 uint64_t max_pipe_bandwidth; 578 uint64_t max_pipe_bandwidth_high; 579 uint32_t cache_size; // cache size in bytes for inline rotation support. 580 bool has_excl_rect = false; 581 QSEEDStepVersion qseed3_version; 582 bool multirect_prop_present = false; 583 InlineRotationVersion inrot_version; // inline rotation version 584 std::vector<std::pair<uint32_t, uint64_t>> inrot_fmts_supported; 585 float true_inline_dwnscale_rt_num = 11.0; 586 float true_inline_dwnscale_rt_denom = 5.0; 587 bool inverse_pma = false; 588 uint32_t dgm_csc_version = 0; // csc used with DMA 589 std::map<DRMTonemapLutType, uint32_t> tonemap_lut_version_map = {}; 590 bool block_sec_ui = false; 591 }; 592 593 // All DRM Planes as map<Plane_id , plane_type_info> listed from highest to lowest priority 594 typedef std::vector<std::pair<uint32_t, DRMPlaneTypeInfo>> DRMPlanesInfo; 595 596 enum struct DRMTopology { 597 UNKNOWN, // To be compat with driver defs in sde_rm.h 598 SINGLE_LM, 599 SINGLE_LM_DSC, 600 DUAL_LM, 601 DUAL_LM_DSC, 602 DUAL_LM_MERGE, 603 DUAL_LM_MERGE_DSC, 604 DUAL_LM_DSCMERGE, 605 QUAD_LM_MERGE, 606 QUAD_LM_DSCMERGE, 607 QUAD_LM_MERGE_DSC, 608 PPSPLIT, 609 }; 610 611 enum struct DRMPanelMode { 612 VIDEO, 613 COMMAND, 614 }; 615 616 /* Per mode info */ 617 struct DRMModeInfo { 618 drmModeModeInfo mode; 619 DRMTopology topology; 620 // Valid only if mode is command 621 int num_roi; 622 int xstart; 623 int ystart; 624 int walign; 625 int halign; 626 int wmin; 627 int hmin; 628 bool roi_merge; 629 uint64_t bit_clk_rate; 630 uint32_t transfer_time_us; 631 }; 632 633 /* Per Connector Info*/ 634 struct DRMConnectorInfo { 635 uint32_t mmWidth; 636 uint32_t mmHeight; 637 uint32_t type; 638 uint32_t type_id; 639 std::vector<DRMModeInfo> modes; 640 std::string panel_name; 641 DRMPanelMode panel_mode; 642 bool is_primary; 643 // Valid only if DRMPanelMode is VIDEO 644 bool dynamic_fps; 645 // FourCC format enum and modifier 646 std::vector<std::pair<uint32_t, uint64_t>> formats_supported; 647 // Valid only if type is DRM_MODE_CONNECTOR_VIRTUAL 648 uint32_t max_linewidth; 649 DRMRotation panel_orientation; 650 drm_panel_hdr_properties panel_hdr_prop; 651 drm_msm_ext_hdr_properties ext_hdr_prop; 652 bool qsync_support; 653 // Connection status of this connector 654 bool is_connected; 655 bool is_wb_ubwc_supported; 656 uint32_t topology_control; 657 bool dyn_bitclk_support; 658 std::vector<uint8_t> edid; 659 uint32_t supported_colorspaces; 660 }; 661 662 // All DRM Connectors as map<Connector_id , connector_info> 663 typedef std::map<uint32_t, DRMConnectorInfo> DRMConnectorsInfo; 664 665 /* Per Encoder Info */ 666 struct DRMEncoderInfo { 667 uint32_t type; 668 }; 669 670 // All DRM Encoders as map<Encoder_id , encoder_info> 671 typedef std::map<uint32_t, DRMEncoderInfo> DRMEncodersInfo; 672 673 /* Identifier token for a display */ 674 struct DRMDisplayToken { 675 uint32_t conn_id; 676 uint32_t crtc_id; 677 uint32_t crtc_index; 678 uint32_t encoder_id; 679 uint8_t hw_port; 680 }; 681 682 enum DRMPPFeatureID { 683 kFeaturePcc, 684 kFeatureIgc, 685 kFeaturePgc, 686 kFeatureMixerGc, 687 kFeaturePaV2, 688 kFeatureDither, 689 kFeatureGamut, 690 kFeaturePADither, 691 kFeaturePAHsic, 692 kFeaturePASixZone, 693 kFeaturePAMemColSkin, 694 kFeaturePAMemColSky, 695 kFeaturePAMemColFoliage, 696 kFeaturePAMemColProt, 697 kFeatureDgmIgc, 698 kFeatureDgmGc, 699 kFeatureVigIgc, 700 kFeatureVigGamut, 701 kPPFeaturesMax, 702 }; 703 704 enum DRMPropType { 705 kPropEnum, 706 kPropRange, 707 kPropBlob, 708 kPropTypeMax, 709 }; 710 711 struct DRMPPFeatureInfo { 712 DRMPPFeatureID id; 713 DRMPropType type; 714 uint32_t version; 715 uint32_t payload_size; 716 void *payload; 717 uint32_t object_type; 718 }; 719 720 enum DRMDPPSFeatureID { 721 // Ad4 properties 722 kFeatureAd4Mode, 723 kFeatureAd4Init, 724 kFeatureAd4Cfg, 725 kFeatureAd4Input, 726 kFeatureAd4Roi, 727 kFeatureAd4Backlight, 728 kFeatureAd4Assertiveness, 729 kFeatureAd4ManualStrength, 730 // ABA properties 731 kFeatureAbaHistCtrl, 732 kFeatureAbaHistIRQ, 733 kFeatureAbaLut, 734 // BL scale properties 735 kFeatureSvBlScale, 736 kFeatureBacklightScale, 737 // Events 738 kFeaturePowerEvent, 739 kFeatureAbaHistEvent, 740 kFeatureBackLightEvent, 741 kFeatureAdAttBlEvent, 742 kFeatureLtmHistEvent, 743 kFeatureLtmWbPbEvent, 744 kFeatureLtmOffEvent, 745 // LTM properties 746 kFeatureLtm, 747 kFeatureLtmInit, 748 kFeatureLtmCfg, 749 kFeatureLtmNoiseThresh, 750 kFeatureLtmBufferCtrl, 751 kFeatureLtmQueueBuffer, 752 kFeatureLtmQueueBuffer2, 753 kFeatureLtmQueueBuffer3, 754 kFeatureLtmHistCtrl, 755 kFeatureLtmVlut, 756 // Insert features above 757 kDppsFeaturesMax, 758 }; 759 760 struct DppsFeaturePayload { 761 uint32_t object_type; 762 uint32_t feature_id; 763 uint64_t value; 764 }; 765 766 struct DRMDppsLtmBuffers { 767 uint32_t num_of_buffers; 768 uint32_t buffer_size; 769 std::array<int, LTM_BUFFER_SIZE> ion_buffer_fd; 770 std::array<int, LTM_BUFFER_SIZE> drm_fb_id; 771 std::array<void*, LTM_BUFFER_SIZE> uva; 772 int status; 773 }; 774 775 struct DRMDppsFeatureInfo { 776 DRMDPPSFeatureID id; 777 uint32_t obj_id; 778 uint32_t version; 779 uint32_t payload_size; 780 void *payload; 781 }; 782 783 enum DRMPanelFeatureID { 784 kDRMPanelFeatureRCInit, 785 kDRMPanelFeatureDsppRCInfo, 786 kDRMPanelFeatureMax, 787 }; 788 789 struct DRMPanelFeatureInfo { 790 DRMPanelFeatureID prop_id; 791 uint32_t obj_type; 792 uint32_t obj_id; 793 uint32_t version; 794 uint32_t prop_size; 795 uint64_t prop_ptr; 796 }; 797 798 enum AD4Modes { 799 kAd4Off, 800 kAd4AutoStrength, 801 kAd4Calibration, 802 kAd4Manual, 803 kAd4ModeMax, 804 }; 805 806 enum HistModes { 807 kHistDisabled, 808 kHistEnabled, 809 }; 810 811 struct DRMDppsEventInfo { 812 uint32_t object_type; 813 uint32_t event_type; 814 int drm_fd; 815 bool enable; 816 }; 817 818 enum DRMCscType { 819 kCscYuv2Rgb601L, 820 kCscYuv2Rgb601FR, 821 kCscYuv2Rgb709L, 822 kCscYuv2Rgb2020L, 823 kCscYuv2Rgb2020FR, 824 kCscTypeMax, 825 }; 826 827 struct DRMScalerLUTInfo { 828 uint32_t dir_lut_size = 0; 829 uint32_t cir_lut_size = 0; 830 uint32_t sep_lut_size = 0; 831 uint64_t dir_lut = 0; 832 uint64_t cir_lut = 0; 833 uint64_t sep_lut = 0; 834 }; 835 836 enum struct DRMSecureMode { 837 NON_SECURE, 838 SECURE, 839 NON_SECURE_DIR_TRANSLATION, 840 SECURE_DIR_TRANSLATION, 841 }; 842 843 enum struct DRMSecurityLevel { 844 SECURE_NON_SECURE, 845 SECURE_ONLY, 846 }; 847 848 enum struct DRMMultiRectMode { 849 NONE = 0, 850 PARALLEL = 1, 851 SERIAL = 2, 852 }; 853 854 enum struct DRMSSPPLayoutIndex { 855 NONE = 0, 856 LEFT = 1, 857 RIGHT = 2, 858 }; 859 860 enum struct DRMCWbCaptureMode { 861 MIXER_OUT = 0, 862 DSPP_OUT = 1, 863 }; 864 865 enum struct DRMQsyncMode { 866 NONE = 0, 867 CONTINUOUS, 868 ONESHOT, 869 }; 870 871 enum struct DRMTopologyControl { 872 NONE = 0, 873 RESERVE_LOCK = 1 << 0, 874 RESERVE_CLEAR = 1 << 1, 875 DSPP = 1 << 2, 876 DEST_SCALER = 1 << 3, 877 }; 878 879 struct DRMSolidfillStage { 880 DRMRect bounding_rect {}; 881 bool is_exclusion_rect = false; 882 uint32_t color = 0xff000000; // in 8bit argb 883 uint32_t red = 0; 884 uint32_t blue = 0; 885 uint32_t green = 0; 886 uint32_t alpha = 0xff; 887 uint32_t color_bit_depth = 0; 888 uint32_t z_order = 0; 889 uint32_t plane_alpha = 0xff; 890 }; 891 892 enum struct DRMFrameTriggerMode { 893 FRAME_DONE_WAIT_DEFAULT = 0, 894 FRAME_DONE_WAIT_SERIALIZE, 895 FRAME_DONE_WAIT_POSTED_START, 896 }; 897 898 /* DRM Color spaces exposed by the DP connector */ 899 enum struct DRMColorspace { 900 DEFAULT = 0, 901 SMPTE_170M_YCC, 902 BT709_YCC, 903 XVYCC_601, 904 XVYCC_709, 905 SYCC_601, 906 OPYCC_601, 907 OPRGB, 908 BT2020_CYCC, 909 BT2020_RGB, 910 BT2020_YCC, 911 DCI_P3_RGB_D65, 912 DCI_P3_RGB_THEATER, 913 }; 914 915 /* DRM Atomic Request Property Set. 916 * 917 * Helper class to create and populate atomic properties of DRM components 918 * when rendered in DRM atomic mode */ 919 class DRMAtomicReqInterface { 920 public: ~DRMAtomicReqInterface()921 virtual ~DRMAtomicReqInterface() {} 922 /* Perform request operation. 923 * 924 * [input]: opcode: operation code from DRMOps list. 925 * obj_id: Relevant crtc, connector, plane id 926 * var_arg: arguments for DRMOps's can differ in number and 927 * data type. Refer above DRMOps to details. 928 * [return]: Error code if the API fails, 0 on success. 929 */ 930 virtual int Perform(DRMOps opcode, uint32_t obj_id, ...) = 0; 931 932 /* 933 * Commit the params set via Perform(). Also resets the properties after commit. Needs to be 934 * called every frame. 935 * [input]: synchronous: Determines if the call should block until a h/w flip 936 * [input]: retain_planes: Retains already staged planes. Useful when not explicitly programming 937 * planes but still need the previously staged ones to not be unstaged 938 * [return]: Error code if the API fails, 0 on success. 939 */ 940 virtual int Commit(bool synchronous, bool retain_planes) = 0; 941 942 /* 943 * Validate the params set via Perform(). 944 * [return]: Error code if the API fails, 0 on success. 945 */ 946 virtual int Validate() = 0; 947 }; 948 949 class DRMManagerInterface; 950 951 /* Populates a singleton instance of DRMManager */ 952 typedef int (*GetDRMManager)(int fd, DRMManagerInterface **intf); 953 954 /* Destroy DRMManager instance */ 955 typedef int (*DestroyDRMManager)(); 956 957 /* 958 * DRM Manager Interface - Any class which plans to implement helper function for vendor 959 * specific DRM driver implementation must implement the below interface routines to work 960 * with SDM. 961 */ 962 963 class DRMManagerInterface { 964 public: ~DRMManagerInterface()965 virtual ~DRMManagerInterface() {} 966 967 /* 968 * Since SDM completely manages the planes. GetPlanesInfo will provide all 969 * the plane information. 970 * [output]: DRMPlanesInfo: Resource Info for planes. 971 */ 972 virtual void GetPlanesInfo(DRMPlanesInfo *info) = 0; 973 974 /* 975 * Will provide all the information of a selected crtc. 976 * [input]: Use crtc id 0 to obtain system wide info 977 * [output]: DRMCrtcInfo: Resource Info for the given CRTC id. 978 * [return]: 0 on success, a negative error value otherwise. 979 */ 980 virtual int GetCrtcInfo(uint32_t crtc_id, DRMCrtcInfo *info) = 0; 981 982 /* 983 * Will provide all the information of a selected connector. 984 * [output]: DRMConnectorInfo: Resource Info for the given connector id 985 * [return]: 0 on success, a negative error value otherwise. 986 */ 987 virtual int GetConnectorInfo(uint32_t conn_id, DRMConnectorInfo *info) = 0; 988 989 /* 990 * Provides information on all connectors. 991 * [output]: DRMConnectorsInfo: Resource info for connectors. 992 * [return]: 0 on success, a negative error value otherwise. 993 */ 994 virtual int GetConnectorsInfo(DRMConnectorsInfo *info) = 0; 995 996 /* 997 * Provides information on a selected encoder. 998 * [output]: DRMEncoderInfo: Resource info for the given encoder id. 999 * [return]: 0 on success, a negative error value otherwise. 1000 */ 1001 virtual int GetEncoderInfo(uint32_t encoder_id, DRMEncoderInfo *info) = 0; 1002 1003 /* 1004 * Provides information on all encoders. 1005 * [output]: DRMEncodersInfo: Resource info for encoders. 1006 * [return]: 0 on success, a negative error value otherwise. 1007 */ 1008 virtual int GetEncodersInfo(DRMEncodersInfo *info) = 0; 1009 1010 /* 1011 * Will query post propcessing feature info of a CRTC. 1012 * [output]: DRMPPFeatureInfo: CRTC post processing feature info 1013 */ 1014 virtual void GetCrtcPPInfo(uint32_t crtc_id, DRMPPFeatureInfo *info) = 0; 1015 1016 /* 1017 * Register a logical display to receive a token. 1018 * Each display pipeline in DRM is identified by its CRTC and Connector(s). On display connect 1019 * (bootup or hotplug), clients should invoke this interface to establish the pipeline for the 1020 * display and should get a DisplayToken populated with crtc, encoder and connnector(s) id's. Here 1021 * onwards, Client should use this token to represent the display for any Perform operations if 1022 * needed. 1023 * 1024 * [input]: disp_type - Peripheral / TV / Virtual 1025 * [output]: DRMDisplayToken - CRTC and Connector IDs for the display. 1026 * [return]: 0 on success, a negative error value otherwise. 1027 */ 1028 virtual int RegisterDisplay(DRMDisplayType disp_type, DRMDisplayToken *tok) = 0; 1029 1030 /* 1031 * Register a logical display to receive a token. 1032 * Each display pipeline in DRM is identified by its CRTC and Connector(s). On display connect 1033 * (bootup or hotplug), clients should invoke this interface to establish the pipeline for the 1034 * display and should get a DisplayToken populated with crtc, encoder and connnector(s) id's. Here 1035 * onwards, Client should use this token to represent the display for any Perform operations if 1036 * needed. 1037 * 1038 * [input]: display_id - Connector ID 1039 * [output]: DRMDisplayToken - CRTC and Connector id's for the display. 1040 * [return]: 0 on success, a negative error value otherwise. 1041 */ 1042 virtual int RegisterDisplay(int32_t display_id, DRMDisplayToken *token) = 0; 1043 1044 /* Client should invoke this interface on display disconnect. 1045 * [input]: DRMDisplayToken - identifier for the display. 1046 */ 1047 virtual void UnregisterDisplay(DRMDisplayToken *token) = 0; 1048 1049 /* 1050 * Creates and returns an instance of DRMAtomicReqInterface corresponding to a display token 1051 * returned as part of RegisterDisplay API. Needs to be called per display. 1052 * [input]: DRMDisplayToken that identifies a display pipeline 1053 * [output]: Pointer to an instance of DRMAtomicReqInterface. 1054 * [return]: Error code if the API fails, 0 on success. 1055 */ 1056 virtual int CreateAtomicReq(const DRMDisplayToken &token, DRMAtomicReqInterface **intf) = 0; 1057 1058 /* 1059 * Destroys the instance of DRMAtomicReqInterface 1060 * [input]: Pointer to a DRMAtomicReqInterface 1061 * [return]: Error code if the API fails, 0 on success. 1062 */ 1063 virtual int DestroyAtomicReq(DRMAtomicReqInterface *intf) = 0; 1064 1065 /* 1066 * Sets the global scaler LUT 1067 * [input]: LUT Info 1068 * [return]: Error code if the API fails, 0 on success. 1069 */ 1070 virtual int SetScalerLUT(const DRMScalerLUTInfo &lut_info) = 0; 1071 1072 /* 1073 * Unsets the global scaler LUT 1074 * [input]: None 1075 * [return]: Error code if the API fails, 0 on success. 1076 */ 1077 virtual int UnsetScalerLUT() = 0; 1078 1079 /* 1080 * Get the DPPS feature info 1081 * [input]: Dpps feature id, info->id 1082 * [output]: Dpps feature version, info->version 1083 */ 1084 virtual void GetDppsFeatureInfo(DRMDppsFeatureInfo *info) = 0; 1085 1086 /* 1087 * Get the Panel feature info 1088 * [output]: panel feature info data 1089 */ 1090 virtual void GetPanelFeature(DRMPanelFeatureInfo *info) = 0; 1091 1092 /* 1093 * Set the Panel feature 1094 * [input]: panel feature info data 1095 */ 1096 virtual void SetPanelFeature(const DRMPanelFeatureInfo &info) = 0; 1097 }; 1098 1099 } // namespace sde_drm 1100 #endif // __DRM_INTERFACE_H__ 1101