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Searched defs:IsWrite (Results 1 – 25 of 31) sorted by relevance

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/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/Transforms/Instrumentation/
DAddressSanitizerCommon.h28 bool IsWrite; variable
38 : IsWrite(IsWrite), OpType(OpType), Alignment(Alignment), in IsWrite() argument
DAddressSanitizer.h58 const bool IsWrite; member
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmInstrumentation.cpp280 X86Operand &Op, unsigned AccessSize, bool IsWrite, in InstrumentMemOperand()
412 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore(); in InstrumentMOV() local
595 void EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx, in EmitCallAsanReport()
617 X86Operand &Op, unsigned AccessSize, bool IsWrite, in InstrumentMemOperandSmall()
692 X86Operand &Op, unsigned AccessSize, bool IsWrite, in InstrumentMemOperandLarge()
864 void EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx, in EmitCallAsanReport()
888 X86Operand &Op, unsigned AccessSize, bool IsWrite, in InstrumentMemOperandSmall()
964 X86Operand &Op, unsigned AccessSize, bool IsWrite, in InstrumentMemOperandLarge()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Transforms/Instrumentation/
DMemProfiler.cpp157 bool IsWrite; member
369 Type *AccessTy, bool IsWrite) { in instrumentMaskedLoadOrStore()
430 uint32_t TypeSize, bool IsWrite) { in instrumentAddress()
DAddressSanitizer.cpp618 ASanAccessInfo::ASanAccessInfo(bool IsWrite, bool CompileKernel, in ASanAccessInfo()
1331 bool IsWrite = CI->getIntrinsicID() == Intrinsic::masked_store; in getInterestingMemoryOperands() local
1419 uint32_t TypeSize, bool IsWrite, in doInstrumentAddress()
1438 bool IsWrite, Value *SizeArgument, in instrumentMaskedLoadOrStore()
1528 Value *Addr, bool IsWrite, in generateCrashCode()
1575 uint32_t TypeSize, bool IsWrite, Value *SizeArgument) { in instrumentAMDGPUAddress()
1598 uint32_t TypeSize, bool IsWrite, in instrumentAddress()
1677 bool IsWrite, Value *SizeArgument, bool UseCalls, uint32_t Exp) { in instrumentUnusualSizeOrAlignment()
DThreadSanitizer.cpp424 const bool IsWrite = isa<StoreInst>(*I); in chooseInstructionsToInstrument() local
592 const bool IsWrite = isa<StoreInst>(*II.Inst); in instrumentLoadOrStore() local
DHWAddressSanitizer.cpp817 int64_t HWAddressSanitizer::getAccessInfo(bool IsWrite, in getAccessInfo()
827 void HWAddressSanitizer::instrumentMemAccessOutline(Value *Ptr, bool IsWrite, in instrumentMemAccessOutline()
842 void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite, in instrumentMemAccessInline()
/external/compiler-rt/lib/esan/
Desan.cpp65 void processRangeAccess(uptr PC, uptr Addr, int Size, bool IsWrite) { in processRangeAccess()
Dworking_set.cpp82 bool IsWrite) { in processRangeAccessWorkingSet()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Instrumentation/
DHWAddressSanitizer.cpp504 bool *IsWrite, in isInterestingMemoryAccess()
607 void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite, in instrumentMemAccessInline()
718 bool IsWrite = false; in instrumentMemAccess() local
1119 bool IsWrite; in sanitizeFunction() local
DAddressSanitizer.cpp1345 bool *IsWrite, in isInterestingMemoryAccess()
1495 uint32_t TypeSize, bool IsWrite, in doInstrumentAddress()
1514 bool IsWrite, Value *SizeArgument, in instrumentMaskedLoadOrStore()
1551 bool IsWrite = false; in instrumentMop() local
1609 Value *Addr, bool IsWrite, in generateCrashCode()
1659 uint32_t TypeSize, bool IsWrite, in instrumentAddress()
1741 bool IsWrite, Value *SizeArgument, bool UseCalls, uint32_t Exp) { in instrumentUnusualSizeOrAlignment()
2651 bool IsWrite; in instrumentFunction() local
DThreadSanitizer.cpp522 bool IsWrite = isa<StoreInst>(*I); in instrumentLoadOrStore() local
/external/llvm/lib/Transforms/Instrumentation/
DAddressSanitizer.cpp938 bool *IsWrite, in isInterestingMemoryAccess()
1031 bool IsWrite = false; in instrumentMop() local
1088 Value *Addr, bool IsWrite, in generateCrashCode()
1138 uint32_t TypeSize, bool IsWrite, in instrumentAddress()
1199 Instruction *I, Value *Addr, uint32_t TypeSize, bool IsWrite, in instrumentUnusualSizeOrAlignment()
1797 bool IsWrite; in runOnFunction() local
DThreadSanitizer.cpp461 bool IsWrite = isa<StoreInst>(*I); in instrumentLoadOrStore() local
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/
DAArch64LegalizerInfo.cpp1091 int64_t IsWrite = MI.getOperand(2).getImm(); in legalizeIntrinsic() local
1115 int64_t IsWrite = MI.getOperand(2).getImm(); in legalizeIntrinsic() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
DLoopAccessAnalysis.cpp688 bool IsWrite = Access.getInt(); in createCheckForAccess() local
725 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); in canCheckPtrAtRT() local
867 bool IsWrite = AC.getInt(); in processMemAccesses() local
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Analysis/
DLoopAccessAnalysis.cpp1029 bool IsWrite = Access.getInt(); in createCheckForAccess() local
1072 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); in canCheckPtrAtRT() local
1243 bool IsWrite = AC.first.getInt(); in processMemAccesses() local
/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/Analysis/
DLoopAccessAnalysis.h250 ArrayRef<unsigned> getOrderForAccess(Value *Ptr, bool IsWrite) const { in getOrderForAccess()
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/analysis/
Dside_effect_analysis.cc89 bool IsWrite() const { return effects_.test(kWrite); } in IsWrite() function in mlir::TF::__anonb2ee10730111::SideEffects
/external/llvm/lib/Analysis/
DLoopAccessAnalysis.cpp609 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); in canCheckPtrAtRT() local
749 bool IsWrite = AC.getInt(); in processMemAccesses() local
/external/compiler-rt/lib/tsan/rtl/
Dtsan_rtl.h250 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } in IsWrite() function
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Transforms/IPO/
DFunctionAttrs.cpp589 bool IsWrite = false; in determinePointerAccessAttrs() local
/external/pdfium/third_party/lcms/src/
Dlcms2_internal.h840 cmsBool IsWrite; member
/external/crosvm/hypervisor/src/whpx/whpx_sys/
DWinHvPlatformDefs.h1004 UINT32 IsWrite : 1; member
1042 UINT32 IsWrite : 1; member
Dbindings.rs6513 pub fn IsWrite(&self) -> UINT32 { in IsWrite() method
6577 let IsWrite: u32 = unsafe { ::std::mem::transmute(IsWrite) }; localVariable
6854 pub fn IsWrite(&self) -> UINT32 { in IsWrite() method
6882 let IsWrite: u32 = unsafe { ::std::mem::transmute(IsWrite) }; localVariable

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