1 /* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef _EXYNOSMPPTYPE_H 18 #define _EXYNOSMPPTYPE_H 19 20 #include <system/graphics.h> 21 #include <utils/String8.h> 22 23 #include <unordered_map> 24 25 #include "DeconHeader.h" 26 27 using namespace android; 28 29 /* 30 * physical types 31 * Resources are sorted by physical type. 32 * Resource that has smaller type value is assigned first. 33 */ 34 typedef enum { 35 MPP_DPP_G = 0, 36 MPP_DPP_GF, 37 MPP_DPP_GFS, 38 MPP_DPP_VG, 39 MPP_DPP_VGS, 40 MPP_DPP_VGF, 41 MPP_DPP_VGFS, 42 MPP_DPP_VGRFS, 43 MPP_DPP_NUM, 44 45 MPP_MSC, 46 MPP_G2D, 47 MPP_P_TYPE_MAX 48 } mpp_phycal_type_t; 49 50 /* logical types */ 51 typedef enum { 52 MPP_LOGICAL_DPP_G = 0x01, 53 MPP_LOGICAL_DPP_GF = 0x02, 54 MPP_LOGICAL_DPP_GFS = 0x03, 55 MPP_LOGICAL_DPP_VG = 0x04, 56 MPP_LOGICAL_DPP_VGS = 0x08, 57 MPP_LOGICAL_DPP_VGF = 0x10, 58 MPP_LOGICAL_DPP_VGFS = 0x20, 59 MPP_LOGICAL_DPP_VGRFS = 0x40, 60 MPP_LOGICAL_MSC = 0x100, 61 MPP_LOGICAL_MSC_YUV = 0x200, 62 MPP_LOGICAL_G2D_YUV = 0x1000, 63 MPP_LOGICAL_G2D_RGB = 0x2000, 64 MPP_LOGICAL_G2D_COMBO = 0x4000, 65 /* 66 * Increase MPP_LOGICAL_TYPE_NUM 67 * if type is added 68 */ 69 MPP_LOGICAL_TYPE_NUM = 13 70 } mpp_logical_type_t; 71 72 enum { 73 MPP_ATTR_AFBC = 0x00000001, 74 MPP_ATTR_WINDOW_UPDATE = 0x00000002, 75 MPP_ATTR_BLOCK_MODE = 0x00000004, 76 MPP_ATTR_USE_CAPA = 0x00000008, 77 MPP_ATTR_FLIP_H = 0x00000020, 78 MPP_ATTR_FLIP_V = 0x00000040, 79 MPP_ATTR_ROT_90 = 0x00000080, 80 MPP_ATTR_SCALE = 0x00000800, 81 MPP_ATTR_DIM = 0x00001000, 82 MPP_ATTR_LAYER_TRANSFORM = 0x00002000, 83 84 MPP_ATTR_WCG = 0x00100000, 85 MPP_ATTR_HDR10 = 0x00200000, 86 87 MPP_ATTR_HDR10PLUS = 0x10000000, 88 }; 89 90 // Resource TDM (Time-Division Muliplexing) 91 typedef enum { 92 TDM_ATTR_SRAM_AMOUNT, 93 TDM_ATTR_AFBC, 94 TDM_ATTR_SBWC, 95 TDM_ATTR_ITP, // CSC // 96 TDM_ATTR_ROT_90, 97 TDM_ATTR_SCALE, 98 TDM_ATTR_WCG, 99 TDM_ATTR_MAX, 100 } tdm_attr_t; 101 102 typedef enum { 103 LS_DPUF, 104 LS_DPUF_AXI 105 } LoadSharing_t; 106 107 typedef struct { 108 String8 name; 109 LoadSharing_t loadSharing; 110 } TDMInfo_t; 111 112 extern std::unordered_map<tdm_attr_t, TDMInfo_t> HWAttrs; 113 114 typedef struct feature_support_t { 115 mpp_phycal_type_t hwType; /* MPP_DPP_VG, MPP_DPP_VGFS, ... */ 116 uint64_t attr; 117 } feature_support_t; 118 119 typedef struct transform_map { 120 android_transform_t hal_tr; 121 uint32_t hwc_tr; 122 } transform_map_t; 123 124 const transform_map_t transform_map_table [] = 125 { 126 {HAL_TRANSFORM_FLIP_H, MPP_ATTR_FLIP_H}, 127 {HAL_TRANSFORM_FLIP_V, MPP_ATTR_FLIP_V}, 128 {HAL_TRANSFORM_ROT_90, MPP_ATTR_ROT_90}, 129 }; 130 131 typedef struct dpu_attr_map { 132 uint32_t dpp_attr; 133 uint32_t hwc_attr = 0; 134 } dpu_attr_map_t; 135 136 typedef struct dpp_channel_map { 137 mpp_phycal_type_t type; 138 uint32_t index; 139 uint32_t idma; // DECON_IDMA 140 decon_idma_type channel; 141 } dpp_channel_map_t; 142 143 /* 144 * pre_assign_info: all display_descriptors that want to reserve 145 */ 146 struct exynos_mpp_t { 147 int physicalType; 148 int logicalType; 149 char name[16]; 150 uint32_t physical_index; 151 uint32_t logical_index; 152 uint32_t pre_assign_info; 153 // For TDM 154 uint32_t hw_block_index; 155 uint32_t axi_port_index; 156 }; 157 158 #endif 159