1 /* 2 * Copyright 2021-2023 NXP 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef _PHNXPUCIHAL_FW_H 18 #define _PHNXPUCIHAL_FW_H 19 #include <stdint.h> 20 21 #define PHHDLL_LEN_LRC (1U) 22 #define PHHDLL_MAX_MISO_DATA_LEN (256U) 23 #define PHHDLL_MAX_LEN_PAYLOAD_MISO (PHHDLL_MAX_MISO_DATA_LEN + PHHDLL_LEN_LRC) 24 25 #define FILEPATH_MAXLEN 500 26 #define FILENAME_MAXLEN 260 27 28 #define HCP_MSG_HEADER_LEN 2 29 #define HDLL_HEADER_LEN 2 30 #define HDLL_FOOTER_LEN 2 31 #define HDLL_CRC_LEN 2 32 #define HDLL_PKT_CHUNK_BITMASK 0x2000 33 #define HDLL_PKT_LEN_BITMASK 0x1FFF 34 #define HCP_GROUP_LEN 6 // bits 35 36 #define HDLL_CHUNK_OFFSET 0 37 #define HDLL_LEN_OFFSET 1 38 #define HDLL_TYPE_OFFSET 2 39 #define HDLL_GROUP_OFFSET 2 40 #define HDLL_OPERATION_OFFSET 3 41 #define HDLL_PAYLOAD_OFFSET 4 42 43 #define HDLL_RSP_STATUS_OFFSET 4 44 #define HDLL_RSP_PAYLOAD_OFFSET 5 45 46 #define HDLL_RSP_GROUP_BIT_MASK 0x3F 47 #define HDLL_MIN_RSP_LEN 8 48 #define MW_MAJOR_FW_VER_OFFSET 4 49 #define MW_MINOR_FW_VER_OFFSET 5 50 51 #define HDLL_READ_BUFF_SIZE 64 52 #define HDLL_READ_OP_TIMEOUT 2000 /* 2 seconds timeout */ 53 54 #define BIN_FILE_BASED_FW_DOWNLOAD 0x00 55 #define SO_FILE_BASED_FW_DOWNLOAD 0x01 56 #define SESSION_CONTROL_OPEN 0x55 57 58 /* Struct to frame HDLL command */ 59 typedef struct phHDLLCmd { 60 uint8_t group; 61 uint8_t operation; 62 uint8_t chunk_size; 63 uint16_t payload_len; 64 uint16_t frame_size; 65 uint8_t *payload; 66 } phHDLLCmd_t; 67 68 /* Struct to process HDLL response */ 69 typedef struct phHDLLCmdRsp { 70 uint8_t *rsp_buf; 71 uint8_t rsp_buf_len; 72 uint8_t group; 73 uint8_t operation; 74 uint8_t status; 75 uint8_t type; 76 } phHDLLCmdRsp_t; 77 78 /* HCP Operation Group */ 79 typedef enum { 80 HCP_OPERATION_GROUP_PROTOCOL = 0x01, 81 HCP_OPERATION_GROUP_GENERIC, 82 HCP_OPERATION_GROUP_EDL 83 } eHCP_OPERATION_GROUP_t; 84 85 /* operation codes under protocol group */ 86 typedef enum { 87 PROTOCOL_GROUP_OP_CODE_HDLL = 0x01, 88 PROTOCOL_GROUP_OP_CODE_HCP, 89 PROTOCOL_GROUP_OP_CODE_EDL 90 } ePROTOCOL_GROUP_OP_CODE_t; 91 92 /* operation codes under generic group */ 93 typedef enum { 94 GENERIC_GROUP_OP_CODE_RESET = 0x01, 95 GENERIC_GROUP_OP_CODE_GETINFO 96 } eGENERIC_GROUP_OP_CODE_t; 97 98 /* operation code under EDL group */ 99 typedef enum { 100 EDL_DOWNLOAD_CERTIFICATE = 0x01, 101 EDL_DOWNLOAD_FLASH_WRITE_FIRST = 0x02, 102 EDL_DOWNLOAD_FLASH_WRITE = 0x03, 103 EDL_DOWNLOAD_FLASH_WRITE_LAST = 0x04, 104 EDL_DOWNLOAD_SRAM_WRITE_FIRST = 0x05, 105 EDL_DOWNLOAD_SRAM_WRITE = 0x06, 106 EDL_DOWNLOAD_SRAM_WRITE_LAST = 0x07, 107 EDL_LIFECYCLE_CERTIFICATE = 0x11, 108 EDL_LIFECYCLE_WRITE_FIRST = 0x12, 109 EDL_LIFECYCLE_WRITE_LAST = 0x13, 110 EDL_PATCH_SRAM_WRITE = 0x21, 111 EDL_PATCH_SRAM_WRITE_LAST = 0x22, 112 EDL_PATCH_FLASH_WRITE = 0x23 113 } eEDL_GROUP_OP_CODE_t; 114 115 /* UWB Device ROM Version */ 116 typedef enum { 117 VER_A1V1 = 0x02, 118 VER_A1V2 = 0x03, 119 } eUWBD_Rom_Version_t; 120 121 /* UWB AT page status */ 122 typedef enum { 123 STATUS_PAGE_OK = 0x55, 124 STATUS_RECOVERED_N_1 = 0x5A, 125 STATUS_RECOVERED_N_2 = 0xA5, 126 STATUS_PAGE_ERROR = 0xAA, 127 } eUWBD_AT_Page_status_t; 128 129 /* UWB Device lifecycle mode */ 130 typedef enum { 131 UNKNOWN = 0xCCCCCCCC, 132 DEGRADED_MODE = 0x5C5C5C5C, 133 FLASH_TEST_MODE = 0xAAAAAAAA, 134 DEVELOPMENT_MODE = 0xC5C5C5C5, 135 CUSTOMER_MODE = 0xA5A5A5A5, 136 PROTECTED_MODE = 0x55555555, 137 NXP_RMA_MODE = 0x5A5A5A5A, 138 } eUWBD_LC_mode_t; 139 140 /* Struct to store the getinfo response */ 141 typedef struct phHDLLGetInfo { 142 uint8_t boot_status; 143 uint8_t session_control; 144 uint8_t session_type; 145 eUWBD_Rom_Version_t rom_version; 146 eUWBD_AT_Page_status_t AT_page_status; 147 uint8_t chip_major_ver; 148 uint8_t chip_minor_ver; 149 uint8_t fw_minor_ver; 150 uint8_t fw_major_ver; 151 uint8_t chip_variant[4]; 152 eUWBD_LC_mode_t device_life_cycle; 153 uint8_t chip_id[16]; 154 uint8_t chip_id_crc[4]; 155 } phHDLLGetInfo_t; 156 157 /* HCP type */ 158 typedef enum { 159 HCP_TYPE_COMMAND = 0x00, 160 HCP_TYPE_RESPONSE, 161 HCP_TYPE_NOTIFICATION 162 } eHCP_TYPE_t; 163 164 /* Application status codes */ 165 typedef enum { 166 /* Success */ 167 GENERIC_SUCCESS = 0x00, 168 ACKNOWLEDGE = 0x01, 169 READY = 0x02, 170 171 /* Generic errors */ 172 GENERIC_ERROR = 0x80, 173 MEMORY_ERROR = 0x81, 174 TIMEOUT_ERROR = 0x82, 175 CRC_ERROR = 0x83, 176 INVALID_ERROR = 0x84, 177 178 /* Verification errors */ 179 INVALID_LENGTH_ERROR = 0x90, 180 INVALID_ADDRESS_ERROR = 0x91, 181 ECC_SIGNATURE_ERROR = 0x92, 182 SHA384_HASH_ERROR = 0x93, 183 LIFECYCLE_VALIDITY_ERROR = 0x94, 184 CHIP_ID_ERROR = 0x95, 185 CHIP_VERSION_ERROR = 0x96, 186 CERTIFICATE_VERSION_ERROR = 0x97, 187 FIRMWARE_VERSION_ERROR = 0x98, 188 SRAM_DOWNLOAD_ALLOW_ERROR = 0x99, 189 190 /* Encryption errors */ 191 KEY_DERIVATION_ERROR = 0xA0, 192 ENCRYPTED_PAYLOAD_DECRYPTION_ERROR = 0xA1, 193 INVALID_ENCRYPTED_PAYLOAD_ERROR = 0xA2, 194 195 /* N-1 & N-2 errors */ 196 PROTECTED_CACHE_LOAD_ERROR = 0xB0, 197 PROTECTED_CACHE_DEPLOY_ERROR = 0xB1, 198 LIFECYCLE_UPDATE_ERROR = 0xB2, 199 200 /* Flash errors */ 201 FLASH_BLANK_PAGE_ERROR = 0xC0, 202 FLASH_CHECK_MARGIN_ERROR = 0xC1 203 } eAPPLICATION_STATUS_CODES_t; 204 205 /* FW download status */ 206 typedef enum phFWD_Status { 207 FW_DNLD_SUCCESS = 0x00, 208 FW_DNLD_FAILURE = 0x01, 209 FW_DNLD_REQUIRED = 0x02, 210 FW_DNLD_NOT_REQUIRED = 0x03, 211 FW_DNLD_FILE_NOT_FOUND = 0x14, 212 } phFWD_Status_t; 213 214 /* FW download flash config status */ 215 typedef enum phFWD_flash_Status { 216 FLASH_UPPER_VER_UPDATE = 0x01, 217 FLASH_FORCE_UPDATE = 0x02, 218 FLASH_DIFFERENT_VER_UPDATE = 0x03, 219 } phFWD_flash_Status_t; 220 221 typedef struct phUwbFWImageContext 222 { 223 /* pointer to the FW image to be used */ 224 uint8_t *fwImage; 225 /* size of fw image */ 226 uint32_t fwImgSize; 227 /* FW FLASH update Options Configurations */ 228 uint8_t fw_flash_config; 229 /* FW Download file Options Configurations */ 230 uint8_t fw_dnld_config; 231 /* FW recovery */ 232 bool fwRecovery; 233 void *gFwLib; 234 /* default fw file path */ 235 char default_fw_path[FILEPATH_MAXLEN]; 236 /* Device Info */ 237 phHDLLGetInfo_t *deviceInfo; 238 } phUwbFWImageContext_t; 239 240 /* SR200 device config */ 241 typedef struct phPalSr200_Config { 242 void* pDevHandle; 243 } phPalSr200_Config_t; 244 245 /* PWR States */ 246 typedef enum phSetPwrState{ 247 PWR_DISABLE = 0, 248 PWR_ENABLE, 249 ABORT_READ_PENDING 250 } phSetPwrState_t; 251 252 phPalSr200_Config_t tPalConfig; 253 254 phFWD_Status_t phHdll_GetApdu(uint8_t *pApdu, uint16_t sz, 255 uint16_t *rsp_buf_len); 256 phFWD_Status_t phHdll_PutApdu(uint8_t *pApdu, uint16_t sz); 257 258 #endif /* _PHNXPUCIHAL_FW_H */ 259