1 /* 2 * Copyright (c) 2012-2016, Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * o Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * o Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef __CAAM_INTERNAL_H__ 33 #define __CAAM_INTERNAL_H__ 34 35 static uint8_t* caam_base; 36 static uint8_t* ccm_base; 37 static uint8_t* sram_base; 38 39 /* 4kbyte pages */ 40 #define CAAM_SEC_RAM_START_ADDR (sram_base) 41 42 #define SEC_MEM_PAGE0 CAAM_SEC_RAM_START_ADDR 43 #define SEC_MEM_PAGE1 (CAAM_SEC_RAM_START_ADDR + 0x1000) 44 #define SEC_MEM_PAGE2 (CAAM_SEC_RAM_START_ADDR + 0x2000) 45 #define SEC_MEM_PAGE3 (CAAM_SEC_RAM_START_ADDR + 0x3000) 46 47 /* Configuration and special key registers */ 48 #define CAAM_MCFGR (0x0004 + caam_base) 49 #define CAAM_SCFGR (0x000c + caam_base) 50 #define CAAM_JR0MIDR (0x0010 + caam_base) 51 #define CAAM_JR1MIDR (0x0018 + caam_base) 52 #define CAAM_DECORR (0x009c + caam_base) 53 #define CAAM_DECO0MID (0x00a0 + caam_base) 54 #define CAAM_DAR (0x0120 + caam_base) 55 #define CAAM_DRR (0x0124 + caam_base) 56 #define CAAM_JDKEKR (0x0400 + caam_base) 57 #define CAAM_TDKEKR (0x0420 + caam_base) 58 #define CAAM_TDSKR (0x0440 + caam_base) 59 #define CAAM_SKNR (0x04e0 + caam_base) 60 #define CAAM_SMSTA (0x0FB4 + caam_base) 61 #define CAAM_STA (0x0FD4 + caam_base) 62 #define CAAM_SMPO_0 (0x1FBC + caam_base) 63 64 /* RNG registers */ 65 #define CAAM_RTMCTL (0x0600 + caam_base) 66 #define CAAM_RTSDCTL (0x0610 + caam_base) 67 #define CAAM_RTFRQMIN (0x0618 + caam_base) 68 #define CAAM_RTFRQMAX (0x061C + caam_base) 69 #define CAAM_RTSTATUS (0x063C + caam_base) 70 #define CAAM_RDSTA (0x06C0 + caam_base) 71 72 /* Job Ring 0 registers */ 73 #define CAAM_IRBAR0 (0x1004 + caam_base) 74 #define CAAM_IRSR0 (0x100c + caam_base) 75 #define CAAM_IRSAR0 (0x1014 + caam_base) 76 #define CAAM_IRJAR0 (0x101c + caam_base) 77 #define CAAM_ORBAR0 (0x1024 + caam_base) 78 #define CAAM_ORSR0 (0x102c + caam_base) 79 #define CAAM_ORJRR0 (0x1034 + caam_base) 80 #define CAAM_ORSFR0 (0x103c + caam_base) 81 #define CAAM_JRSTAR0 (0x1044 + caam_base) 82 #define CAAM_JRINTR0 (0x104c + caam_base) 83 #define CAAM_JRCFGR0_MS (0x1050 + caam_base) 84 #define CAAM_JRCFGR0_LS (0x1054 + caam_base) 85 #define CAAM_IRRIR0 (0x105c + caam_base) 86 #define CAAM_ORWIR0 (0x1064 + caam_base) 87 #define CAAM_JRCR0 (0x106c + caam_base) 88 #define CAAM_SMCJR0 (0x10f4 + caam_base) 89 #define CAAM_SMCSJR0 (0x10fc + caam_base) 90 #if 0 91 #define CAAM_SMAPJR0(y) (CAAM_BASE_ADDR + 0x1104 + y * 16) 92 #define CAAM_SMAG2JR0(y) (CAAM_BASE_ADDR + 0x1108 + y * 16) 93 #define CAAM_SMAG1JR0(y) (CAAM_BASE_ADDR + 0x110C + y * 16) 94 #define CAAM_SMAPJR0_PRTN1 CAAM_BASE_ADDR + 0x1114 95 #define CAAM_SMAG2JR0_PRTN1 CAAM_BASE_ADDR + 0x1118 96 #define CAAM_SMAG1JR0_PRTN1 CAAM_BASE_ADDR + 0x111c 97 #define CAAM_SMPO CAAM_BASE_ADDR + 0x1fbc 98 #endif 99 100 #define JRCFG_LS_IMSK 0x00000001 101 #define JR_MID 2 102 #define KS_G1 (1 << JR_MID) 103 #define PERM 0x0000B008 104 105 #define CMD_PAGE_ALLOC 0x1 106 #define CMD_PAGE_DEALLOC 0x2 107 #define CMD_PART_DEALLOC 0x3 108 #define CMD_INQUIRY 0x5 109 #define PAGE(x) (x << 16) 110 #define PARTITION(x) (x << 8) 111 112 #define SMCSJR_AERR (3 << 12) 113 #define SMCSJR_CERR (3 << 14) 114 #define CMD_COMPLETE (3 << 14) 115 116 #define SMCSJR_PO (3 << 6) 117 #define PAGE_AVAILABLE 0 118 #define PAGE_OWNED (3 << 6) 119 120 #define PARTITION_OWNER(x) (0x3 << (x * 2)) 121 122 #define CAAM_BUSY_MASK 0x00000001 123 #define CAAM_IDLE_MASK 0x00000002 124 #define JOB_RING_ENTRIES 1 125 #define JOB_RING_STS (0xF << 28) 126 127 #define RNG_TRIM_OSC_DIV 0 128 #define RNG_TRIM_ENT_DLY 3200 129 130 #define RTMCTL_PGM (1 << 16) 131 #define RTMCTL_ERR (1 << 12) 132 #define RDSTA_IF0 1 133 #define RDSTA_SKVN (1 << 30) 134 135 #define DECAP_BLOB_DESC1 0xB0800009 136 #define DECAP_BLOB_DESC2 0x14C00C08 137 #define DECAP_BLOB_DESC3 0x00105566 138 #define DECAP_BLOB_DESC4 0x00000000 139 #define DECAP_BLOB_DESC5 0xF0000400 140 #define DECAP_BLOB_DESC6 0x00000000 141 #define DECAP_BLOB_DESC7 0xF80003d0 142 #define DECAP_BLOB_DESC8 SEC_MEM_PAGE1 143 #define DECAP_BLOB_DESC9 0x860D0008 144 145 #define ENCAP_BLOB_DESC1 0xB0800009 146 #define ENCAP_BLOB_DESC2 0x14C00C08 147 #define ENCAP_BLOB_DESC3 0x00105566 148 #define ENCAP_BLOB_DESC4 0x00000000 149 #define ENCAP_BLOB_DESC5 0xF00003d0 150 #define ENCAP_BLOB_DESC6 SEC_MEM_PAGE1 151 #define ENCAP_BLOB_DESC7 0xF8000400 152 #define ENCAP_BLOB_DESC8 0x00000000 153 #define ENCAP_BLOB_DESC9 0x870D0008 154 155 #define RNG_INST_DESC1 0xB0800009 156 #define RNG_INST_DESC2 0x12A00008 157 #define RNG_INST_DESC3 0x01020304 158 #define RNG_INST_DESC4 0x05060708 159 #define RNG_INST_DESC5 0x82500404 160 #define RNG_INST_DESC6 0xA2000001 161 #define RNG_INST_DESC7 0x10880004 162 #define RNG_INST_DESC8 0x00000001 163 #define RNG_INST_DESC9 0x82501000 164 165 #endif /* __CAAM_INTERNAL_H__ */ 166