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Searched defs:RegisterInfo (Results 1 – 8 of 8) sorted by relevance

/external/ot-br-posix/src/trel_dnssd/
Dtrel_dnssd.hpp123 struct RegisterInfo struct in otbr::TrelDnssd::TrelDnssd
125 uint16_t mPort = 0;
126 Mdns::Publisher::TxtData mTxtData;
127 std::string mInstanceName;
129 bool IsValid(void) const { return mPort > 0; } in IsValid()
130 bool IsPublished(void) const { return !mInstanceName.empty(); } in IsPublished()
/external/mesa3d/src/amd/compiler/
Daco_scheduler_ilp.cpp50 struct RegisterInfo { struct
51 mask_t read_mask; /* bitmask of nodes which have to be scheduled before the next write. */
52 int8_t latency; /* estimated latency of last register write. */
53 uint8_t direct_dependency : 4; /* node that has to be scheduled before any other access. */
54 uint8_t has_direct_dependency : 1; /* whether there is an unscheduled direct dependency. */
55 uint8_t padding : 3;
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.h26 const LanaiRegisterInfo RegisterInfo; variable
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.h26 const LanaiRegisterInfo RegisterInfo; variable
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.h26 const LanaiRegisterInfo RegisterInfo; variable
/external/llvm/docs/TableGen/
DBackEnds.rst83 RegisterInfo section in LLVM BackEnds
/external/rust/crates/gdbstub/src/
Darch.rs199 pub enum RegisterInfo<'a> { enum
/external/swiftshader/third_party/llvm-16.0/llvm/lib/DebugInfo/LogicalView/Readers/
DLVBinaryReader.cpp202 MCRegisterInfo *RegisterInfo = TheTarget->createMCRegInfo(TheTriple); in loadGenericTargetInfo() local