| /external/rust/crates/rayon/src/iter/ |
| D | rev.rs | 12 pub struct Rev<I: IndexedParallelIterator> { struct
16 impl<I> Rev<I> implementation
26 impl<I> ParallelIterator for Rev<I> implementation
44 impl<I> IndexedParallelIterator for Rev<I> implementation
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| /external/toolchain-utils/llvm_tools/ |
| D | get_upstream_patch.py | 78 start_version: git_llvm_rev.Rev,
80 rev: t.Union[git_llvm_rev.Rev, str],
237 start_rev: git_llvm_rev.Rev,
238 rev: t.Union[git_llvm_rev.Rev, str],
289 start_rev: git_llvm_rev.Rev,
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| D | git_llvm_rev.py | 57 class Rev(NamedTuple("Rev", (("branch", str), ("number", int)))): class
262 def translate_prebase_rev_to_sha(llvm_config: LLVMConfig, rev: Rev) -> str:
369 def translate_rev_to_sha(llvm_config: LLVMConfig, rev: Rev) -> str:
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| D | setup_for_workon.py | 36 current_rev: git_llvm_rev.Rev,
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| D | git_llvm_rev_test.py | 23 def rev_to_sha_with_round_trip(self, rev: git_llvm_rev.Rev) -> str:
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| D | get_patch_unittest.py | 48 def _mock_from_rev(_, rev: git_llvm_rev.Rev) -> get_patch.LLVMGitRef:
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| D | get_patch.py | 63 def from_rev(cls, llvm_dir: Path, rev: git_llvm_rev.Rev) -> "LLVMGitRef":
|
| /external/python/cpython2/Demo/classes/ |
| D | Rev.py | 62 class Rev: class
|
| /external/vixl/benchmarks/aarch64/ |
| D | bench-utils.cc | 207 __ Rev(PickR(size), PickR(size)); in GenerateTrivialSequence() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 512 const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer); in getSingleInstruction() local
|
| /external/clang/utils/TableGen/ |
| D | NeonEmitter.cpp | 1601 class Rev : public SetTheory::Operator { in emitDagShuffle() class
1605 Rev(unsigned ElementSize) : ElementSize(ElementSize) {} in emitDagShuffle() function in Intrinsic::DagEmitter::emitDagShuffle::Rev
|
| /external/bazelbuild-rules_rust/crate_universe/src/ |
| D | config.rs | 164 Rev(String), enumerator
|
| /external/vixl/test/aarch64/ |
| D | test-assembler-sve-aarch64.cc | 5618 __ Rev(z5.VnB(), z9.VnB()); in TEST_SVE() local
5619 __ Rev(z6.VnH(), z9.VnH()); in TEST_SVE() local
5620 __ Rev(z7.VnS(), z9.VnS()); in TEST_SVE() local
5621 __ Rev(z8.VnD(), z9.VnD()); in TEST_SVE() local
13761 __ Rev(p1.VnB(), p0.VnB()); in TEST_SVE() local
13762 __ Rev(p2.VnH(), p0.VnH()); in TEST_SVE() local
13763 __ Rev(p3.VnS(), p0.VnS()); in TEST_SVE() local
13764 __ Rev(p4.VnD(), p0.VnD()); in TEST_SVE() local
14030 __ Rev(p1.VnB(), p0.VnB()); in TEST_SVE() local
16591 __ Rev(z1.VnH(), z0.VnH()); in TEST_SVE() local
[all …]
|
| D | test-assembler-aarch64.cc | 1507 __ Rev(w4, w24); in TEST() local
1510 __ Rev(x7, x24); in TEST() local
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 412 Rev, enumerator
|
| /external/clang/lib/Basic/ |
| D | Targets.cpp | 142 unsigned Maj, Min, Rev; in getDarwinDefines() local
452 unsigned Maj, Min, Rev; in getOSDefines() local
|
| /external/python/cpython3/Lib/test/ |
| D | test_collections.py | 1038 class Rev: class
|
| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 2182 void Rev(const Register& rd, const Register& rn) { in Rev() function
5602 void Rev(const PRegisterWithLaneSize& pd, const PRegisterWithLaneSize& pn) { in Rev() function
5607 void Rev(const ZRegister& zd, const ZRegister& zn) { in Rev() function
|
| /external/tensorflow/tensorflow/compiler/xla/client/ |
| D | xla_builder.cc | 2151 XlaOp XlaBuilder::Rev(XlaOp operand, absl::Span<const int64_t> dimensions) { in Rev() function in xla::XlaBuilder
4837 XlaOp Rev(const XlaOp operand, absl::Span<const int64_t> dimensions) { in Rev() function
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 10238 SDValue Rev = DAG.getNode(RevOpcode, dl, VT, Op0); in LowerVecReduce() local
16538 auto isVMOVNShuffle = [&](ShuffleVectorSDNode *SVN, bool Rev) { in PerformSplittingToNarrowingStores()
18583 unsigned Rev = VT == MVT::v4i32 ? ARMISD::VREV32 : ARMISD::VREV16; in PerformMVEExtCombine() local
|
| /external/bazelbuild-rules_rust/examples/crate_universe/cargo_aliases/ |
| D | cargo-bazel-lock.json | 1257 "Rev": "760516503b89ddc8bc2ab42d579d4566cfb1054f" string
|
| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 3080 void Rev(Condition cond, Register rd, Register rm) { in Rev() function
3089 void Rev(Register rd, Register rm) { Rev(al, rd, rm); } in Rev() function
|
| /external/bazelbuild-rules_rust/examples/crate_universe/multi_package/ |
| D | cargo-bazel-lock.json | 3655 "Rev": "9ecf35255ee154986bc36d06473f1fa088586ad9" string
4486 "Rev": "096aff7b13f4ff5bb474fdc27bc30b297a2968f6" string
|
| /external/bazelbuild-rules_rust/crate_universe/test_data/cargo_bazel_lockfile/ |
| D | multi_package-cargo-bazel-lock.json | 3655 "Rev": "9ecf35255ee154986bc36d06473f1fa088586ad9" string
4486 "Rev": "096aff7b13f4ff5bb474fdc27bc30b297a2968f6" string
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 11537 SDValue Rev = DAG.getNode(AArch64ISD::REV64, dl, VT, V1); in LowerVECTOR_SHUFFLE() local
|