1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 /** 10 **************************************************************************************************** 11 * @file addrlib.h 12 * @brief Contains the Addr::Lib base class definition. 13 **************************************************************************************************** 14 */ 15 16 #ifndef __ADDR_LIB_H__ 17 #define __ADDR_LIB_H__ 18 19 #include "addrinterface.h" 20 #include "addrtypes.h" 21 #include "addrobject.h" 22 #include "addrelemlib.h" 23 24 #include "amdgpu_asic_addr.h" 25 26 #ifndef CIASICIDGFXENGINE_R600 27 #define CIASICIDGFXENGINE_R600 0x00000006 28 #endif 29 30 #ifndef CIASICIDGFXENGINE_R800 31 #define CIASICIDGFXENGINE_R800 0x00000008 32 #endif 33 34 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND 35 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A 36 #endif 37 38 #ifndef CIASICIDGFXENGINE_ARCTICISLAND 39 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D 40 #endif 41 42 namespace Addr 43 { 44 45 /** 46 **************************************************************************************************** 47 * @brief Neutral enums that define pipeinterleave 48 **************************************************************************************************** 49 */ 50 enum PipeInterleave 51 { 52 ADDR_PIPEINTERLEAVE_256B = 256, 53 ADDR_PIPEINTERLEAVE_512B = 512, 54 ADDR_PIPEINTERLEAVE_1KB = 1024, 55 ADDR_PIPEINTERLEAVE_2KB = 2048, 56 }; 57 58 /** 59 **************************************************************************************************** 60 * @brief Neutral enums that define DRAM row size 61 **************************************************************************************************** 62 */ 63 enum RowSize 64 { 65 ADDR_ROWSIZE_1KB = 1024, 66 ADDR_ROWSIZE_2KB = 2048, 67 ADDR_ROWSIZE_4KB = 4096, 68 ADDR_ROWSIZE_8KB = 8192, 69 }; 70 71 /** 72 **************************************************************************************************** 73 * @brief Neutral enums that define bank interleave 74 **************************************************************************************************** 75 */ 76 enum BankInterleave 77 { 78 ADDR_BANKINTERLEAVE_1 = 1, 79 ADDR_BANKINTERLEAVE_2 = 2, 80 ADDR_BANKINTERLEAVE_4 = 4, 81 ADDR_BANKINTERLEAVE_8 = 8, 82 }; 83 84 /** 85 **************************************************************************************************** 86 * @brief Neutral enums that define shader engine tile size 87 **************************************************************************************************** 88 */ 89 enum ShaderEngineTileSize 90 { 91 ADDR_SE_TILESIZE_16 = 16, 92 ADDR_SE_TILESIZE_32 = 32, 93 }; 94 95 /** 96 **************************************************************************************************** 97 * @brief Neutral enums that define bank swap size 98 **************************************************************************************************** 99 */ 100 enum BankSwapSize 101 { 102 ADDR_BANKSWAP_128B = 128, 103 ADDR_BANKSWAP_256B = 256, 104 ADDR_BANKSWAP_512B = 512, 105 ADDR_BANKSWAP_1KB = 1024, 106 }; 107 108 /** 109 **************************************************************************************************** 110 * @brief Enums that define max compressed fragments config 111 **************************************************************************************************** 112 */ 113 enum NumMaxCompressedFragmentsConfig 114 { 115 ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000, 116 ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001, 117 ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002, 118 ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003, 119 }; 120 121 /** 122 **************************************************************************************************** 123 * @brief Enums that define num pipes config 124 **************************************************************************************************** 125 */ 126 enum NumPipesConfig 127 { 128 ADDR_CONFIG_1_PIPE = 0x00000000, 129 ADDR_CONFIG_2_PIPE = 0x00000001, 130 ADDR_CONFIG_4_PIPE = 0x00000002, 131 ADDR_CONFIG_8_PIPE = 0x00000003, 132 ADDR_CONFIG_16_PIPE = 0x00000004, 133 ADDR_CONFIG_32_PIPE = 0x00000005, 134 ADDR_CONFIG_64_PIPE = 0x00000006, 135 }; 136 137 /** 138 **************************************************************************************************** 139 * @brief Enums that define num banks config 140 **************************************************************************************************** 141 */ 142 enum NumBanksConfig 143 { 144 ADDR_CONFIG_1_BANK = 0x00000000, 145 ADDR_CONFIG_2_BANK = 0x00000001, 146 ADDR_CONFIG_4_BANK = 0x00000002, 147 ADDR_CONFIG_8_BANK = 0x00000003, 148 ADDR_CONFIG_16_BANK = 0x00000004, 149 }; 150 151 /** 152 **************************************************************************************************** 153 * @brief Enums that define num rb per shader engine config 154 **************************************************************************************************** 155 */ 156 enum NumRbPerShaderEngineConfig 157 { 158 ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000, 159 ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001, 160 ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002, 161 }; 162 163 /** 164 **************************************************************************************************** 165 * @brief Enums that define num shader engines config 166 **************************************************************************************************** 167 */ 168 enum NumShaderEnginesConfig 169 { 170 ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000, 171 ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001, 172 ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002, 173 ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003, 174 }; 175 176 /** 177 **************************************************************************************************** 178 * @brief Enums that define pipe interleave size config 179 **************************************************************************************************** 180 */ 181 enum PipeInterleaveSizeConfig 182 { 183 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000, 184 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001, 185 ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002, 186 ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003, 187 }; 188 189 /** 190 **************************************************************************************************** 191 * @brief Enums that define row size config 192 **************************************************************************************************** 193 */ 194 enum RowSizeConfig 195 { 196 ADDR_CONFIG_1KB_ROW = 0x00000000, 197 ADDR_CONFIG_2KB_ROW = 0x00000001, 198 ADDR_CONFIG_4KB_ROW = 0x00000002, 199 }; 200 201 /** 202 **************************************************************************************************** 203 * @brief Enums that define bank interleave size config 204 **************************************************************************************************** 205 */ 206 enum BankInterleaveSizeConfig 207 { 208 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000, 209 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001, 210 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002, 211 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003, 212 }; 213 214 /** 215 **************************************************************************************************** 216 * @brief Enums that define engine tile size config 217 **************************************************************************************************** 218 */ 219 enum ShaderEngineTileSizeConfig 220 { 221 ADDR_CONFIG_SE_TILE_16 = 0x00000000, 222 ADDR_CONFIG_SE_TILE_32 = 0x00000001, 223 }; 224 225 /** 226 **************************************************************************************************** 227 * @brief This class contains asic independent address lib functionalities 228 **************************************************************************************************** 229 */ 230 class Lib : public Object 231 { 232 public: 233 virtual ~Lib(); 234 235 static ADDR_E_RETURNCODE Create( 236 const ADDR_CREATE_INPUT* pCreateInfo, ADDR_CREATE_OUTPUT* pCreateOut); 237 238 /// Pair of Create Destroy()239 VOID Destroy() 240 { 241 delete this; 242 } 243 244 static Lib* GetLib(ADDR_HANDLE hLib); 245 246 /// Returns AddrLib version (from compiled binary instead include file) GetVersion()247 UINT_32 GetVersion() 248 { 249 return m_version; 250 } 251 252 /// Returns asic chip family name defined by AddrLib GetChipFamily()253 ChipFamily GetChipFamily() const 254 { 255 return m_chipFamily; 256 } 257 258 ADDR_E_RETURNCODE Flt32ToDepthPixel( 259 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn, 260 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const; 261 262 ADDR_E_RETURNCODE Flt32ToColorPixel( 263 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn, 264 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const; 265 266 BOOL_32 GetExportNorm(const ELEM_GETEXPORTNORM_INPUT* pIn) const; 267 268 ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const; 269 270 ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const; 271 272 UINT_32 GetBpe(AddrFormat format) const; 273 274 protected: 275 Lib(); // Constructor is protected 276 Lib(const Client* pClient); 277 278 /// Pure virtual function to get max base alignments 279 virtual UINT_32 HwlComputeMaxBaseAlignments() const = 0; 280 281 /// Gets maximum alignements for metadata HwlComputeMaxMetaBaseAlignments()282 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const 283 { 284 ADDR_NOT_IMPLEMENTED(); 285 286 return 0; 287 } 288 ValidBaseAlignments(UINT_32 alignment)289 VOID ValidBaseAlignments(UINT_32 alignment) const 290 { 291 #if DEBUG 292 ADDR_ASSERT(alignment <= m_maxBaseAlign); 293 #endif 294 } 295 ValidMetaBaseAlignments(UINT_32 metaAlignment)296 VOID ValidMetaBaseAlignments(UINT_32 metaAlignment) const 297 { 298 #if DEBUG 299 ADDR_ASSERT(metaAlignment <= m_maxMetaBaseAlign); 300 #endif 301 } 302 IsTex1d(AddrResourceType resourceType)303 static BOOL_32 IsTex1d(AddrResourceType resourceType) 304 { 305 return (resourceType == ADDR_RSRC_TEX_1D); 306 } 307 IsTex2d(AddrResourceType resourceType)308 static BOOL_32 IsTex2d(AddrResourceType resourceType) 309 { 310 return (resourceType == ADDR_RSRC_TEX_2D); 311 } 312 IsTex3d(AddrResourceType resourceType)313 static BOOL_32 IsTex3d(AddrResourceType resourceType) 314 { 315 return (resourceType == ADDR_RSRC_TEX_3D); 316 } 317 318 // 319 // Initialization 320 // 321 /// Pure Virtual function for Hwl computing internal global parameters from h/w registers 322 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn) = 0; 323 324 /// Pure Virtual function for Hwl converting chip family 325 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0; 326 327 /// Get equation table pointer and number of equations HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)328 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 329 { 330 *ppEquationTable = NULL; 331 332 return 0; 333 } 334 335 // 336 // Misc helper 337 // 338 static UINT_32 Bits2Number(UINT_32 bitNum, ...); 339 GetNumFragments(UINT_32 numSamples,UINT_32 numFrags)340 static UINT_32 GetNumFragments(UINT_32 numSamples, UINT_32 numFrags) 341 { 342 return (numFrags != 0) ? numFrags : Max(1u, numSamples); 343 } 344 345 /// Returns pointer of ElemLib GetElemLib()346 ElemLib* GetElemLib() const 347 { 348 return m_pElemLib; 349 } 350 351 /// Returns fillSizeFields flag GetFillSizeFieldsFlags()352 UINT_32 GetFillSizeFieldsFlags() const 353 { 354 return m_configFlags.fillSizeFields; 355 } 356 357 private: 358 // Disallow the copy constructor 359 Lib(const Lib& a); 360 361 // Disallow the assignment operator 362 Lib& operator=(const Lib& a); 363 364 VOID SetChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 365 366 VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels); 367 368 VOID SetMaxAlignments(); 369 370 protected: 371 ChipFamily m_chipFamily; ///< Chip family translated from the one in atiid.h 372 373 UINT_32 m_chipRevision; ///< Revision id from xxx_id.h 374 375 UINT_32 m_version; ///< Current version 376 377 // 378 // Global parameters 379 // 380 ConfigFlags m_configFlags; ///< Global configuration flags. Note this is setup by 381 /// AddrLib instead of Client except forceLinearAligned 382 383 UINT_32 m_pipes; ///< Number of pipes 384 UINT_32 m_banks; ///< Number of banks 385 /// For r800 this is MC_ARB_RAMCFG.NOOFBANK 386 /// Keep it here to do default parameter calculation 387 388 UINT_32 m_pipeInterleaveBytes; 389 ///< Specifies the size of contiguous address space 390 /// within each tiling pipe when making linear 391 /// accesses. (Formerly Group Size) 392 393 UINT_32 m_rowSize; ///< DRAM row size, in bytes 394 395 UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels 396 UINT_32 m_maxSamples; ///< Max numSamples 397 398 UINT_32 m_maxBaseAlign; ///< Max base alignment for data surface 399 UINT_32 m_maxMetaBaseAlign; ///< Max base alignment for metadata 400 401 private: 402 ElemLib* m_pElemLib; ///< Element Lib pointer 403 }; 404 405 Lib* SiHwlInit (const Client* pClient); 406 Lib* CiHwlInit (const Client* pClient); 407 Lib* Gfx9HwlInit (const Client* pClient); 408 Lib* Gfx10HwlInit(const Client* pClient); 409 Lib* Gfx11HwlInit(const Client* pClient); 410 } // Addr 411 412 #endif 413