1 /* 2 * Copyright (C) 2019 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ANDROID_EXYNOS_HWC_MODULE_H_ 18 #define ANDROID_EXYNOS_HWC_MODULE_H_ 19 20 #include <array> 21 22 #include "ExynosHWC.h" 23 24 #define G2D_MAX_SRC_NUM 3 25 26 #define VSYNC_DEV_PREFIX "/sys/devices/platform/" 27 #define PSR_DEV_NAME "1c300000.decon_f/psr_info" 28 #define VSYNC_DEV_NAME_EXT "19050000.decon_t/vsync" 29 #define DP_LINK_NAME "130b0000.displayport" 30 #define DP_UEVENT_NAME "change@/devices/platform/%s/extcon/extcon0" 31 #define DP_CABLE_STATE_NAME "/sys/devices/platform/%s/extcon/extcon0/cable.0/state" 32 #define BRIGHTNESS_SYSFS_NODE "/sys/class/backlight/panel%d-backlight/brightness" 33 #define MAX_BRIGHTNESS_SYSFS_NODE "/sys/class/backlight/panel%d-backlight/max_brightness" 34 35 #define IDMA(x) static_cast<decon_idma_type>(x) 36 37 #define MPP_G2D_CAPACITY 3.5 38 39 enum { 40 HWC_DISPLAY_NONE_BIT = 0 41 }; 42 43 #define MAX_NAME_SIZE 32 44 struct exynos_display_t { 45 uint32_t type; 46 uint32_t index; 47 std::string display_name; 48 std::string decon_node_name; 49 std::string vsync_node_name; 50 }; 51 52 #define PRIMARY_MAIN_BASE_WIN 2 53 #define EXTERNAL_MAIN_BASE_WIN 4 54 55 /******** Description about display bit ********/ 56 /* DISPLAY BIT = 1 << (DISPLAY_MODE_MASK_LEN * display mode 57 * + SECOND_DISPLAY_START_BIT * display index 58 * + display type); 59 * ex) HWC_DISPLAY_EXTERNAL2_BIT = 1 << (DISPLAY_MODE_MASK_LEN * display mode(0) 60 * + SECOND_DISPLAY_START_BIT * display index(1) 61 * + displayy type(1)) 62 * = 1 << 5 63 * PRIMARY MAIN MODE : 64 * 0 bit : HWC_DISPLAY_PRIMARY_BIT, 65 * 1 bit : HWC_DISPLAY_EXTERNAL_BIT, 66 * 2 bit : HWC_DISPLAY_VIRTUAL_BIT, 67 * 5 bit : HWC_DISPLAY_EXTERNAL2_BIT, 68 * EXTERNAL MAIN MODE : 69 * 8 bit : EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT, 70 * 9 bit : EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT, 71 * 10 bit : EXTERNAL_MAIN_DISPLAY_VIRTUAL_BIT, 72 ***************************************************/ 73 74 #define DISPLAY_MODE_MASK_LEN 8 75 #define DISPLAY_MODE_MASK_BIT 0xff 76 #define SECOND_DISPLAY_START_BIT 4 77 78 enum { 79 DISPLAY_MODE_PRIMARY_MAIN = 0, /* This is default mode */ 80 DISPLAY_MODE_EXTERNAL_MAIN, 81 DISPLAY_MODE_NUM 82 }; 83 84 /* 85 * This is base window index of primary display for each display mode. 86 * External display base window is always 0 87 */ 88 const uint32_t PRIMARY_DISP_BASE_WIN[] = {PRIMARY_MAIN_BASE_WIN, EXTERNAL_MAIN_BASE_WIN}; 89 90 #define EXTERNAL_MAIN_DISPLAY_START_BIT (DISPLAY_MODE_MASK_LEN * DISPLAY_MODE_EXTERNAL_MAIN) 91 enum { 92 EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT = 1 << (EXTERNAL_MAIN_DISPLAY_START_BIT + HWC_DISPLAY_PRIMARY), 93 EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT = 1 << (EXTERNAL_MAIN_DISPLAY_START_BIT + HWC_DISPLAY_EXTERNAL), 94 EXTERNAL_MAIN_DISPLAY_VIRTUAL_BIT = 1 << (EXTERNAL_MAIN_DISPLAY_START_BIT + HWC_DISPLAY_VIRTUAL), 95 }; 96 97 enum { 98 HWC_RESERVE_DISPLAY_MAIN_BIT = 1, 99 HWC_RESERVE_DISPLAY_MINOR_BIT = 2 100 }; 101 102 namespace gs101 { 103 104 static const char *early_wakeup_node_0_base = 105 "/sys/devices/platform/1c300000.drmdecon/early_wakeup"; 106 107 static const dpp_channel_map_t idma_channel_map[] = { 108 /* GF physical index is switched to change assign order */ 109 /* DECON_IDMA is not used */ 110 {MPP_DPP_GF, 0, IDMA(0), IDMA(0)}, 111 {MPP_DPP_VGRFS, 0, IDMA(1), IDMA(1)}, 112 {MPP_DPP_GF, 1, IDMA(2), IDMA(2)}, 113 {MPP_DPP_VGRFS, 1, IDMA(3), IDMA(3)}, 114 {MPP_DPP_GF, 2, IDMA(4), IDMA(4)}, 115 {MPP_DPP_VGRFS, 2, IDMA(5), IDMA(5)}, 116 {MPP_P_TYPE_MAX, 0, IDMA(6), IDMA(6)}, // not idma but.. 117 {static_cast<mpp_phycal_type_t>(MAX_DECON_DMA_TYPE), 0, MAX_DECON_DMA_TYPE, IDMA(7)} 118 }; 119 120 static const exynos_mpp_t available_otf_mpp_units[] = { 121 {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF0", 0, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 0, 0}, 122 {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF1", 1, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 0, 0}, 123 {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF2", 2, 0, HWC_RESERVE_DISPLAY_MINOR_BIT, 0, 0}, 124 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 0, 0}, 125 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS1", 1, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 0, 0}, 126 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS2", 2, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 0, 0}}; 127 128 static const std::array<exynos_display_t, 2> AVAILABLE_DISPLAY_UNITS = {{ 129 {HWC_DISPLAY_PRIMARY, 0, "PrimaryDisplay", "/dev/dri/card0", ""}, 130 {HWC_DISPLAY_PRIMARY, 1, "SecondaryDisplay", "/dev/dri/card0", ""} 131 }}; 132 133 } // namespace gs101 134 135 const exynos_mpp_t AVAILABLE_M2M_MPP_UNITS[] = { 136 #ifndef DISABLE_M2M_MPPS 137 {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_PRI", 0, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 0, 0}, 138 {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_PRI", 0, 1, HWC_RESERVE_DISPLAY_MAIN_BIT, 0, 0}, 139 {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_EXT", 0, 2, HWC_RESERVE_DISPLAY_MINOR_BIT, 0, 0}, 140 {MPP_G2D, MPP_LOGICAL_G2D_RGB, "G2D0-RGB_PRI", 0, 3, HWC_RESERVE_DISPLAY_MAIN_BIT, 0, 0}, 141 {MPP_G2D, MPP_LOGICAL_G2D_RGB, "G2D0-RGB_EXT", 0, 4, HWC_RESERVE_DISPLAY_MINOR_BIT, 0, 0}, 142 {MPP_G2D, MPP_LOGICAL_G2D_COMBO, "G2D0-COMBO_VIR", 0, 5, HWC_RESERVE_DISPLAY_MINOR_BIT, 0, 0} 143 #endif 144 }; 145 146 #endif 147