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Searched defs:imm12 (Results 1 – 8 of 8) sorted by relevance

/art/dex2oat/linker/riscv64/
Drelative_patcher_riscv64.cc86 uint32_t imm12 = disp & 0xfffu; // The instruction shall sign-extend this immediate. in PatchPcRelativeReference() local
Drelative_patcher_riscv64_test.cc88 uint32_t imm12 = offset & 0xfffu; in GenNopsAndAuipcAndUse() local
/art/disassembler/
Ddisassembler_arm.cc81 uint32_t imm12 = reinterpret_cast<const uint16_t*>(address)[1] & 0xfffu; in operator <<() local
Ddisassembler_riscv64.cc96 uint32_t imm12 = (insn32 >> 20); in Decode32Imm12() local
413 int32_t imm12 = Decode32Imm12(insn32); in Print32Jalr() local
/art/dex2oat/linker/arm64/
Drelative_patcher_arm64.cc306 uint32_t imm12 = (disp & 0xfffu) >> shift; in PatchPcRelativeReference() local
/art/compiler/utils/riscv64/
Dassembler_riscv64.h2332 void EmitI(int32_t imm12, Reg1 rs1, uint32_t funct3, Reg2 rd, uint32_t opcode) { in EmitI()
2396 void EmitS(int32_t imm12, Reg1 rs2, Reg2 rs1, uint32_t funct3, uint32_t opcode) { in EmitS()
2448 uint32_t imm12 = (static_cast<uint32_t>(offset) >> 1) & 0xfffu; in EmitB() local
Dassembler_riscv64.cc305 void Riscv64Assembler::Addi(XRegister rd, XRegister rs1, int32_t imm12) { in Addi()
339 void Riscv64Assembler::Slti(XRegister rd, XRegister rs1, int32_t imm12) { in Slti()
343 void Riscv64Assembler::Sltiu(XRegister rd, XRegister rs1, int32_t imm12) { in Sltiu()
347 void Riscv64Assembler::Xori(XRegister rd, XRegister rs1, int32_t imm12) { in Xori()
358 void Riscv64Assembler::Ori(XRegister rd, XRegister rs1, int32_t imm12) { in Ori()
362 void Riscv64Assembler::Andi(XRegister rd, XRegister rs1, int32_t imm12) { in Andi()
533 void Riscv64Assembler::Addiw(XRegister rd, XRegister rs1, int32_t imm12) { in Addiw()
/art/compiler/optimizing/
Dcode_generator_riscv64.cc153 int32_t imm12 = dchecked_integral_cast<int32_t>(bits0_11) - in SplitJitAddress() local
268 CompileOptimizedSlowPathRISCV64(HSuspendCheck* suspend_check, XRegister base, int32_t imm12) in CompileOptimizedSlowPathRISCV64()