1 /*
2 * Copyright (C) 2023 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 // x86_64 machine IR interface.
18
19 #ifndef BERBERIS_BACKEND_X86_64_MACHINE_IR_H_
20 #define BERBERIS_BACKEND_X86_64_MACHINE_IR_H_
21
22 #include <cstdint>
23 #include <string>
24
25 #include "berberis/assembler/x86_64.h"
26 #include "berberis/backend/code_emitter.h"
27 #include "berberis/backend/common/machine_ir.h"
28 #include "berberis/base/arena_alloc.h"
29 #include "berberis/guest_state/guest_state_arch.h"
30
31 namespace berberis {
32
33 enum MachineOpcode : int {
34 kMachineOpUndefined = 0,
35 kMachineOpCallImm,
36 kMachineOpCallImmArg,
37 kMachineOpPseudoBranch,
38 kMachineOpPseudoCondBranch,
39 kMachineOpPseudoCopy,
40 kMachineOpPseudoDefReg,
41 kMachineOpPseudoDefXReg,
42 kMachineOpPseudoIndirectJump,
43 kMachineOpPseudoJump,
44 kMachineOpPseudoReadFlags,
45 kMachineOpPseudoWriteFlags,
46 #include "berberis/backend/x86_64/machine_opcode_guest-inl.h"
47 #include "machine_opcode_x86_64-inl.h" // NOLINT generated file!
48 };
49
50 namespace x86_64 {
51
52 constexpr const MachineReg kMachineRegR8{1};
53 constexpr const MachineReg kMachineRegR9{2};
54 constexpr const MachineReg kMachineRegR10{3};
55 constexpr const MachineReg kMachineRegR11{4};
56 constexpr const MachineReg kMachineRegRSI{5};
57 constexpr const MachineReg kMachineRegRDI{6};
58 constexpr const MachineReg kMachineRegRAX{7};
59 constexpr const MachineReg kMachineRegRBX{8};
60 constexpr const MachineReg kMachineRegRCX{9};
61 constexpr const MachineReg kMachineRegRDX{10};
62 constexpr const MachineReg kMachineRegRBP{11};
63 constexpr const MachineReg kMachineRegRSP{12};
64 constexpr const MachineReg kMachineRegR12{13};
65 constexpr const MachineReg kMachineRegR13{14};
66 constexpr const MachineReg kMachineRegR14{15};
67 constexpr const MachineReg kMachineRegR15{16};
68 constexpr const MachineReg kMachineRegFLAGS{19};
69 constexpr const MachineReg kMachineRegXMM0{20};
70 constexpr const MachineReg kMachineRegXMM1{21};
71 constexpr const MachineReg kMachineRegXMM2{22};
72 constexpr const MachineReg kMachineRegXMM3{23};
73 constexpr const MachineReg kMachineRegXMM4{24};
74 constexpr const MachineReg kMachineRegXMM5{25};
75 constexpr const MachineReg kMachineRegXMM6{26};
76 constexpr const MachineReg kMachineRegXMM7{27};
77 constexpr const MachineReg kMachineRegXMM8{28};
78 constexpr const MachineReg kMachineRegXMM9{29};
79 constexpr const MachineReg kMachineRegXMM10{30};
80 constexpr const MachineReg kMachineRegXMM11{31};
81 constexpr const MachineReg kMachineRegXMM12{32};
82 constexpr const MachineReg kMachineRegXMM13{33};
83 constexpr const MachineReg kMachineRegXMM14{34};
84 constexpr const MachineReg kMachineRegXMM15{35};
85
IsGReg(MachineReg r)86 inline bool IsGReg(MachineReg r) {
87 return r.reg() >= kMachineRegR8.reg() && r.reg() <= kMachineRegR15.reg();
88 }
89
IsXReg(MachineReg r)90 inline bool IsXReg(MachineReg r) {
91 return r.reg() >= kMachineRegXMM0.reg() && r.reg() <= kMachineRegXMM15.reg();
92 }
93
94 // rax, rdi, rsi, rdx, rcx, r8-r11, xmm0-xmm15, flags
95 const int kMaxMachineRegOperands = 26;
96
97 // Context loads and stores use rbp as base.
98 const MachineReg kCPUStatePointer = kMachineRegRBP;
99
100 struct MachineInsnInfo {
101 MachineOpcode opcode;
102 int num_reg_operands;
103 MachineRegKind reg_kinds[kMaxMachineRegOperands];
104 MachineInsnKind kind;
105 };
106
107 enum class MachineMemOperandScale {
108 kOne,
109 kTwo,
110 kFour,
111 kEight,
112 };
113
114 #include "machine_reg_class_x86_64-inl.h" // NOLINT generated file!
115
116 class MachineInsnX86_64 : public MachineInsn {
117 public:
118 static constexpr const auto kEAX = x86_64::kEAX;
119 static constexpr const auto kRAX = x86_64::kRAX;
120 static constexpr const auto kCL = x86_64::kCL;
121 static constexpr const auto kECX = x86_64::kECX;
122 static constexpr const auto kRCX = x86_64::kRCX;
123 static constexpr const auto kEDX = x86_64::kEDX;
124 static constexpr const auto kRDX = x86_64::kRDX;
125 static constexpr const auto kGeneralReg8 = x86_64::kGeneralReg8;
126 static constexpr const auto kGeneralReg16 = x86_64::kGeneralReg16;
127 static constexpr const auto kGeneralReg32 = x86_64::kGeneralReg32;
128 static constexpr const auto kGeneralReg64 = x86_64::kGeneralReg64;
129 static constexpr const auto kFpReg32 = x86_64::kFpReg32;
130 static constexpr const auto kFpReg64 = x86_64::kFpReg64;
131 static constexpr const auto kVecReg128 = x86_64::kVecReg128;
132 static constexpr const auto kXmmReg = x86_64::kXmmReg;
133 static constexpr const auto kFLAGS = x86_64::kFLAGS;
134
~MachineInsnX86_64()135 ~MachineInsnX86_64() override {
136 // No code here - will never be called!
137 }
138
scale()139 MachineMemOperandScale scale() const { return scale_; }
140
disp()141 uint32_t disp() const { return disp_; }
142
cond()143 Assembler::Condition cond() const { return cond_; }
144
imm()145 uint64_t imm() const { return imm_; }
146
IsCPUStateGet()147 bool IsCPUStateGet() {
148 if (opcode() != kMachineOpMovqRegMemBaseDisp && opcode() != kMachineOpMovdqaXRegMemBaseDisp &&
149 opcode() != kMachineOpMovwRegMemBaseDisp && opcode() != kMachineOpMovsdXRegMemBaseDisp) {
150 return false;
151 }
152
153 // Check that it is not for ThreadState fields outside of CPUState.
154 if (disp() >= sizeof(CPUState)) {
155 return false;
156 }
157
158 // reservation_value is loaded in HeavyOptimizerFrontend::AtomicLoad and written
159 // in HeavyOptimizerFrontend::AtomicStore partially (for performance
160 // reasons), which is not supported by our context optimizer.
161 auto reservation_value_offset = offsetof(ThreadState, cpu.reservation_value);
162 if (disp() >= reservation_value_offset &&
163 disp() < reservation_value_offset + sizeof(Reservation)) {
164 return false;
165 }
166
167 return RegAt(1) == kCPUStatePointer;
168 }
169
IsCPUStatePut()170 bool IsCPUStatePut() {
171 if (opcode() != kMachineOpMovqMemBaseDispReg && opcode() != kMachineOpMovdqaMemBaseDispXReg &&
172 opcode() != kMachineOpMovwMemBaseDispReg && opcode() != kMachineOpMovsdMemBaseDispXReg) {
173 return false;
174 }
175
176 // Check that it is not for ThreadState fields outside of CPUState.
177 if (disp() >= sizeof(CPUState)) {
178 return false;
179 }
180
181 // reservation_value is loaded in HeavyOptimizerFrontend::AtomicLoad and written
182 // in HeavyOptimizerFrontend::AtomicStore partially (for performance
183 // reasons), which is not supported by our context optimizer.
184 auto reservation_value_offset = offsetof(ThreadState, cpu.reservation_value);
185 if (disp() >= reservation_value_offset &&
186 disp() < reservation_value_offset + sizeof(Reservation)) {
187 return false;
188 }
189
190 return RegAt(0) == kCPUStatePointer;
191 }
192
193 protected:
MachineInsnX86_64(const MachineInsnInfo * info)194 explicit MachineInsnX86_64(const MachineInsnInfo* info)
195 : MachineInsn(info->opcode, info->num_reg_operands, info->reg_kinds, regs_, info->kind),
196 scale_(MachineMemOperandScale::kOne) {}
197
set_scale(MachineMemOperandScale scale)198 void set_scale(MachineMemOperandScale scale) { scale_ = scale; }
199
set_disp(uint32_t disp)200 void set_disp(uint32_t disp) { disp_ = disp; }
201
set_cond(Assembler::Condition cond)202 void set_cond(Assembler::Condition cond) { cond_ = cond; }
203
set_imm(uint64_t imm)204 void set_imm(uint64_t imm) { imm_ = imm; }
205
206 private:
207 MachineReg regs_[kMaxMachineRegOperands];
208 MachineMemOperandScale scale_;
209 uint32_t disp_;
210 uint64_t imm_;
211 Assembler::Condition cond_;
212 };
213
214 // Syntax sugar.
AsMachineInsnX86_64(const MachineInsn * insn)215 inline const MachineInsnX86_64* AsMachineInsnX86_64(const MachineInsn* insn) {
216 return static_cast<const MachineInsnX86_64*>(insn);
217 }
218
AsMachineInsnX86_64(MachineInsn * insn)219 inline MachineInsnX86_64* AsMachineInsnX86_64(MachineInsn* insn) {
220 return static_cast<MachineInsnX86_64*>(insn);
221 }
222
223 // Clobbered registers are described as DEF'ed.
224 // TODO(b/232598137): implement simpler support for clobbered registers?
225 class CallImm : public MachineInsnX86_64 {
226 public:
227 enum class RegType {
228 kIntType,
229 kXmmType,
230 };
231
232 static constexpr RegType kIntRegType = RegType::kIntType;
233 static constexpr RegType kXmmRegType = RegType::kXmmType;
234
235 struct Arg {
236 MachineReg reg;
237 RegType reg_type;
238 };
239
240 public:
241 explicit CallImm(uint64_t imm);
242
243 [[nodiscard]] static int GetIntArgIndex(int i);
244 [[nodiscard]] static int GetXmmArgIndex(int i);
245 [[nodiscard]] static int GetFlagsArgIndex();
246
247 [[nodiscard]] MachineReg IntResultAt(int i) const;
248 [[nodiscard]] MachineReg XmmResultAt(int i) const;
249
250 [[nodiscard]] std::string GetDebugString() const override;
251 void Emit(CodeEmitter* as) const override;
252 };
253
254 // An auxiliary instruction to express data-flow for CallImm arguments. It uses the same vreg as
255 // the corresponding operand in CallImm. The specific hard register assigned is defined by the
256 // register class of CallImm operand. MachineIRBuilder adds an extra PseudoCopy before this insn in
257 // case the same vreg holds values for several arguments (with non-intersecting register classes).
258 class CallImmArg : public MachineInsnX86_64 {
259 public:
260 explicit CallImmArg(MachineReg arg, CallImm::RegType reg_type);
261
262 std::string GetDebugString() const override;
Emit(CodeEmitter *)263 void Emit(CodeEmitter*) const override{
264 // It's an auxiliary instruction. Do not emit.
265 };
266 };
267
268 // This template is syntax sugar to group memory instructions with
269 // different addressing modes.
270 template <typename Absolute_, typename BaseDisp_, typename IndexDisp_, typename BaseIndexDisp_>
271 class MemInsns {
272 public:
273 using Absolute = Absolute_;
274 using BaseDisp = BaseDisp_;
275 using IndexDisp = IndexDisp_;
276 using BaseIndexDisp = BaseIndexDisp_;
277 };
278
279 using MachineInsnForArch = MachineInsnX86_64;
280
281 #include "gen_machine_ir_x86_64-inl.h" // NOLINT generated file!
282
283 class MachineInfo {
284 public:
285 #include "machine_info_x86_64-inl.h" // NOLINT generated file!
286 };
287
288 class MachineIR : public berberis::MachineIR {
289 public:
290 enum class BasicBlockOrder {
291 kUnordered,
292 kReversePostOrder,
293 };
294
295 explicit MachineIR(Arena* arena, int num_vreg = 0)
296 : berberis::MachineIR(arena, num_vreg, 0), bb_order_(BasicBlockOrder::kUnordered) {}
297
AddEdge(MachineBasicBlock * src,MachineBasicBlock * dst)298 void AddEdge(MachineBasicBlock* src, MachineBasicBlock* dst) {
299 MachineEdge* edge = NewInArena<MachineEdge>(arena(), arena(), src, dst);
300 src->out_edges().push_back(edge);
301 dst->in_edges().push_back(edge);
302 bb_order_ = BasicBlockOrder::kUnordered;
303 }
304
NewBasicBlock()305 [[nodiscard]] MachineBasicBlock* NewBasicBlock() {
306 return NewInArena<MachineBasicBlock>(arena(), arena(), ReserveBasicBlockId());
307 }
308
309 // Instruction iterators are preserved after splitting basic block and moving
310 // instructions to the new basic block.
SplitBasicBlock(MachineBasicBlock * bb,MachineInsnList::iterator insn_it)311 [[nodiscard]] MachineBasicBlock* SplitBasicBlock(MachineBasicBlock* bb,
312 MachineInsnList::iterator insn_it) {
313 MachineBasicBlock* new_bb = NewBasicBlock();
314
315 new_bb->insn_list().splice(
316 new_bb->insn_list().begin(), bb->insn_list(), insn_it, bb->insn_list().end());
317 bb->insn_list().push_back(NewInsn<PseudoBranch>(new_bb));
318
319 // Relink out edges from bb.
320 for (auto out_edge : bb->out_edges()) {
321 out_edge->set_src(new_bb);
322 }
323 new_bb->out_edges().swap(bb->out_edges());
324
325 AddEdge(bb, new_bb);
326 bb_list().push_back(new_bb);
327 return new_bb;
328 }
329
IsControlTransfer(MachineInsn * insn)330 [[nodiscard]] static bool IsControlTransfer(MachineInsn* insn) {
331 return insn->opcode() == kMachineOpPseudoBranch ||
332 insn->opcode() == kMachineOpPseudoCondBranch ||
333 insn->opcode() == kMachineOpPseudoIndirectJump || insn->opcode() == kMachineOpPseudoJump;
334 }
335
bb_order()336 [[nodiscard]] BasicBlockOrder bb_order() const { return bb_order_; }
337
set_bb_order(BasicBlockOrder order)338 void set_bb_order(BasicBlockOrder order) { bb_order_ = order; }
339
340 private:
341 BasicBlockOrder bb_order_;
342 };
343
344 } // namespace x86_64
345
346 } // namespace berberis
347
348 #endif // BERBERIS_BACKEND_X86_64_MACHINE_IR_H_
349