1 /* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * Project HWC 2.0 Design 19 */ 20 21 #ifndef _EXYNOSMPP_H 22 #define _EXYNOSMPP_H 23 24 #include <utils/Thread.h> 25 #include <utils/Mutex.h> 26 #include <utils/Condition.h> 27 #include <utils/String8.h> 28 #include <utils/StrongPointer.h> 29 #include <utils/List.h> 30 #include <utils/Vector.h> 31 #include <map> 32 #include <hardware/exynos/acryl.h> 33 #include <map> 34 #include "ExynosHWCModule.h" 35 #include "ExynosHWCHelper.h" 36 #include "ExynosMPPType.h" 37 38 class ExynosDisplay; 39 class ExynosMPP; 40 class ExynosResourceManager; 41 42 #ifndef NUM_MPP_DST_BUFS 43 #define NUM_MPP_DST_BUFS_DEFAULT 3 44 /* 45 * Buffer number can be different according to type 46 * #define NUM_MPP_DST_BUFS(type) ((type == MPP_LOGICAL_G2D_RGB) ? 3:2) 47 */ 48 #define NUM_MPP_DST_BUFS(type) (3) 49 #endif 50 51 #ifndef G2D_MAX_SRC_NUM 52 #define G2D_MAX_SRC_NUM 15 53 #endif 54 55 #define G2D_JUSTIFIED_DST_ALIGN 16 56 57 #define NUM_MPP_SRC_BUFS G2D_MAX_SRC_NUM 58 59 #ifndef G2D_RESTRICTIVE_SRC_NUM 60 #define G2D_RESTRICTIVE_SRC_NUM 5 61 #endif 62 63 #ifndef G2D_BASE_PPC 64 #define G2D_BASE_PPC 2.8 65 #endif 66 #ifndef G2D_DST_BASE_PPC 67 #define G2D_DST_BASE_PPC 3.5 68 #endif 69 #ifndef G2D_DST_BASE_PPC_YUV420 70 #define G2D_DST_BASE_PPC_YUV420 2.8 71 #endif 72 #ifndef G2D_DST_BASE_PPC_ROT 73 #define G2D_DST_BASE_PPC_ROT 2.4 74 #endif 75 #ifndef G2D_BASE_PPC_COLORFILL 76 #define G2D_BASE_PPC_COLORFILL 3.8 77 #endif 78 79 #ifndef G2D_CLOCK 80 #define G2D_CLOCK 711000 81 #endif 82 83 #ifndef MSC_CLOCK 84 #define MSC_CLOCK 534000 85 #endif 86 87 #ifndef VPP_CLOCK 88 #define VPP_CLOCK 664000 89 #endif 90 #ifndef VPP_MIC_FACTOR 91 #define VPP_MIC_FACTOR 2 92 #endif 93 94 #ifndef VPP_TE_PERIOD 95 #define VPP_TE_PERIOD 63 96 #endif 97 #ifndef VPP_MARGIN 98 #define VPP_MARGIN 1.1 99 #endif 100 #ifndef VPP_BUBBLE 101 #define VPP_BUBBLE 0.06 102 #endif 103 104 #define VPP_RESOL_CLOCK_FACTOR (VPP_TE_PERIOD * VPP_MARGIN) 105 #define VPP_RESOL_MARGIN (VPP_MARGIN + VPP_BUBBLE) 106 #ifndef VPP_DISP_FACTOR 107 #define VPP_DISP_FACTOR 1.0 108 #endif 109 #ifndef VPP_PIXEL_PER_CLOCK 110 #define VPP_PIXEL_PER_CLOCK 2 111 #endif 112 113 #ifndef MPP_G2D_CAPACITY 114 #define MPP_G2D_CAPACITY 8 115 #endif 116 // G2D or MSC additional margin capacity when HDR layer is passed. 117 #ifndef MPP_HDR_MARGIN 118 #define MPP_HDR_MARGIN 1.2 119 #endif 120 121 #ifndef MPP_MSC_CAPACITY 122 #define MPP_MSC_CAPACITY 8 123 #endif 124 125 /* Currently allowed capacity percentage is over 10% */ 126 #define MPP_CAPA_OVER_THRESHOLD 1.1 127 128 #ifndef MPP_G2D_SRC_SCALED_WEIGHT 129 #define MPP_G2D_SRC_SCALED_WEIGHT 1.125 130 #endif 131 132 #ifndef MPP_G2D_DST_ROT_WEIGHT 133 #define MPP_G2D_DST_ROT_WEIGHT 2.0 134 #endif 135 136 #define MPP_DUMP_PATH "/data/vendor/log/hwc/output.dat" 137 138 using namespace android; 139 140 enum { 141 eMPPSaveCapability = 1ULL << 0, 142 eMPPStrideCrop = 1ULL << 1, 143 eMPPUnsupportedRotation = 1ULL << 2, 144 eMPPHWBusy = 1ULL << 3, 145 eMPPExeedSrcCropMax = 1ULL << 4, 146 eMPPUnsupportedColorTransform = 1ULL << 5, 147 eMPPUnsupportedBlending = 1ULL << 6, 148 eMPPUnsupportedFormat = 1ULL << 7, 149 eMPPNotAlignedDstSize = 1ULL << 8, 150 eMPPNotAlignedSrcCropPosition = 1ULL << 9, 151 eMPPNotAlignedHStride = 1ULL << 10, 152 eMPPNotAlignedVStride = 1ULL << 11, 153 eMPPExceedHStrideMaximum = 1ULL << 12, 154 eMPPExceedVStrideMaximum = 1ULL << 13, 155 eMPPExeedMaxDownScale = 1ULL << 14, 156 eMPPExeedMaxDstWidth = 1ULL << 15, 157 eMPPExeedMaxDstHeight = 1ULL << 16, 158 eMPPExeedMinSrcWidth = 1ULL << 17, 159 eMPPExeedMinSrcHeight = 1ULL << 18, 160 eMPPExeedMaxUpScale = 1ULL << 19, 161 eMPPExeedSrcWCropMax = 1ULL << 20, 162 eMPPExeedSrcHCropMax = 1ULL << 21, 163 eMPPExeedSrcWCropMin = 1ULL << 22, 164 eMPPExeedSrcHCropMin = 1ULL << 23, 165 eMPPNotAlignedCrop = 1ULL << 24, 166 eMPPNotAlignedOffset = 1ULL << 25, 167 eMPPExeedMinDstWidth = 1ULL << 26, 168 eMPPExeedMinDstHeight = 1ULL << 27, 169 eMPPUnsupportedCompression = 1ULL << 28, 170 eMPPUnsupportedCSC = 1ULL << 29, 171 eMPPUnsupportedDIMLayer = 1ULL << 30, 172 eMPPUnsupportedDRM = 1ULL << 31, 173 eMPPUnsupportedDynamicMeta = 1ULL << 32, 174 eMPPSatisfiedRestriction = 1ULL << 33, 175 eMPPExeedHWResource = 1ULL << 34, 176 }; 177 178 enum { 179 MPP_TYPE_NONE, 180 MPP_TYPE_OTF, 181 MPP_TYPE_M2M 182 }; 183 184 enum { 185 MPP_ASSIGN_STATE_FREE = 0x00000000, 186 MPP_ASSIGN_STATE_RESERVED = 0x00000001, 187 MPP_ASSIGN_STATE_ASSIGNED = 0x00000002, 188 }; 189 190 enum { 191 MPP_HW_STATE_IDLE, 192 MPP_HW_STATE_RUNNING 193 }; 194 195 enum { 196 MPP_BUFFER_NORMAL = 0, 197 MPP_BUFFER_NORMAL_DRM, 198 MPP_BUFFER_SECURE_DRM, 199 MPP_BUFFER_DUMP, 200 }; 201 202 enum { 203 MPP_MEM_MMAP = 1, 204 MPP_MEM_USERPTR, 205 MPP_MEM_OVERLAY, 206 MPP_MEM_DMABUF, 207 }; 208 209 enum { 210 MPP_SOURCE_COMPOSITION_TARGET, 211 MPP_SOURCE_LAYER, 212 MPP_SOURCE_MAX 213 }; 214 215 /* Based on multi-resolution feature */ 216 typedef enum { 217 DST_SIZE_HD = 0, 218 DST_SIZE_HD_PLUS, 219 DST_SIZE_FHD, 220 DST_SIZE_FHD_PLUS, 221 DST_SIZE_WQHD, 222 DST_SIZE_WQHD_PLUS, 223 DST_SIZE_UNKNOWN, 224 } dst_alloc_buf_size_t; 225 226 #ifndef DEFAULT_MPP_DST_FORMAT 227 #define DEFAULT_MPP_DST_FORMAT HAL_PIXEL_FORMAT_RGBA_8888 228 #endif 229 #ifndef DEFAULT_MPP_DST_YUV_FORMAT 230 #define DEFAULT_MPP_DST_YUV_FORMAT HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_SPN 231 #endif 232 #ifndef DEFAULT_MPP_DST_UNCOMP_YUV_FORMAT 233 #define DEFAULT_MPP_DST_UNCOMP_YUV_FORMAT HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_SPN 234 #endif 235 236 typedef struct exynos_mpp_img_info { 237 buffer_handle_t bufferHandle; 238 uint32_t bufferType; 239 uint32_t format; 240 android_dataspace_t dataspace; 241 AcrylicLayer *mppLayer; 242 int acrylicAcquireFenceFd; 243 int acrylicReleaseFenceFd; 244 ExynosDisplay *assignedDisplay; 245 } exynos_mpp_img_info_t; 246 247 typedef enum { 248 PPC_SCALE_NO = 0, /* no scale */ 249 PPC_SCALE_DOWN_1_4, /* x1/1.xx ~ x1/4 */ 250 PPC_SCALE_DOWN_4_9, /* x1/4 ~ x1/9 */ 251 PPC_SCALE_DOWN_9_16, /* x1/9 ~ x1/16 */ 252 PPC_SCALE_DOWN_16_, /* x1/16 ~ */ 253 PPC_SCALE_UP_1_4, /* x1.xx ~ x4 */ 254 PPC_SCALE_UP_4_, /* x4 ~ */ 255 PPC_SCALE_MAX 256 } scaling_index_t; 257 258 typedef enum { 259 PPC_FORMAT_YUV420 = 0, 260 PPC_FORMAT_YUV422, 261 PPC_FORMAT_RGB32, 262 PPC_FORMAT_SBWC, 263 PPC_FORMAT_P010, 264 PPC_FORMAT_AFBC_RGB, 265 PPC_FORMAT_AFBC_YUV, 266 PPC_FORMAT_FORMAT_MAX 267 } format_index_t; 268 269 typedef enum { 270 PPC_ROT_NO = 0, 271 PPC_ROT, 272 PPC_ROT_MAX 273 } rot_index_t; 274 275 typedef struct ppc_list_for_scaling { 276 float ppcList[PPC_SCALE_MAX]; 277 } ppc_list_for_scaling_t; 278 279 typedef std::map<uint32_t, ppc_list_for_scaling> ppc_table; 280 281 typedef struct dstMetaInfo { 282 uint16_t minLuminance = 0; 283 uint16_t maxLuminance = 0; 284 } dstMetaInfo_t; 285 286 enum 287 { 288 NODE_NONE, 289 NODE_SRC, 290 NODE_DST 291 }; /* nodeType */ 292 293 enum 294 { 295 HAL_TRANSFORM_NONE = 0 296 }; 297 298 enum 299 { 300 HAL_PIXEL_FORMAT_NONE = 0 301 }; 302 303 #define YUV_CHROMA_H_SUBSAMPLE static_cast<uint32_t>(2) // Horizontal 304 #define YUV_CHROMA_V_SUBSAMPLE static_cast<uint32_t>(2) // Vertical 305 #define RESTRICTION_CNT_MAX 1024 306 307 typedef enum restriction_classification { 308 RESTRICTION_RGB = 0, 309 RESTRICTION_YUV, 310 RESTRICTION_MAX 311 } restriction_classification_t; 312 313 typedef struct restriction_key 314 { 315 mpp_phycal_type_t hwType; /* MPP_DPP_VG, MPP_DPP_VGFS, ... */ 316 uint32_t nodeType; /* src or dst */ 317 uint32_t format; /* HAL format */ 318 uint32_t reserved; 319 } restriction_key_t; 320 321 typedef struct restriction_size 322 { 323 static constexpr size_t kNumofRestriction = 16; 324 union { 325 std::array<uint32_t, kNumofRestriction> mData; 326 struct { 327 uint32_t maxDownScale; 328 uint32_t maxUpScale; 329 uint32_t maxFullWidth; 330 uint32_t maxFullHeight; 331 uint32_t minFullWidth; 332 uint32_t minFullHeight; 333 uint32_t fullWidthAlign; 334 uint32_t fullHeightAlign; 335 uint32_t maxCropWidth; 336 uint32_t maxCropHeight; 337 uint32_t minCropWidth; 338 uint32_t minCropHeight; 339 uint32_t cropXAlign; 340 uint32_t cropYAlign; 341 uint32_t cropWidthAlign; 342 uint32_t cropHeightAlign; 343 }; 344 }; 345 restriction_sizerestriction_size346 restriction_size() { mData.fill(0); } restriction_sizerestriction_size347 restriction_size(std::array<uint32_t, kNumofRestriction> &&rdata) : mData(rdata){}; 348 349 bool operator==(const restriction_size &rhs) const { return rhs.mData == mData; } 350 } restriction_size_t; 351 352 typedef struct restriction_size_element 353 { 354 restriction_key_t key; 355 restriction_size_t sizeRestriction; 356 } restriction_size_element_t; 357 358 typedef struct restriction_table_element 359 { 360 uint32_t classfication_type; 361 const restriction_size_element *table; 362 uint32_t table_element_size; 363 } restriction_table_element_t; 364 /* */ 365 366 #define FORMAT_SHIFT 10 367 #define ROT_SHIFT 20 368 #define PPC_IDX(x,y,z) (x|(y<<FORMAT_SHIFT)|(z<<ROT_SHIFT)) 369 370 const std::map<uint32_t, int32_t> dataspace_standard_map = 371 { 372 {HAL_DATASPACE_STANDARD_UNSPECIFIED, 373 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 374 375 {HAL_DATASPACE_STANDARD_BT709, 376 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 377 378 {HAL_DATASPACE_STANDARD_BT601_625, 379 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 380 381 {HAL_DATASPACE_STANDARD_BT601_625_UNADJUSTED, 382 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 383 384 {HAL_DATASPACE_STANDARD_BT601_525, 385 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 386 387 {HAL_DATASPACE_STANDARD_BT601_525_UNADJUSTED, 388 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 389 390 {HAL_DATASPACE_STANDARD_BT2020, 391 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 392 393 {HAL_DATASPACE_STANDARD_BT2020_CONSTANT_LUMINANCE, 394 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 395 396 {HAL_DATASPACE_STANDARD_BT470M, 397 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 398 399 {HAL_DATASPACE_STANDARD_FILM, 400 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 401 402 {HAL_DATASPACE_STANDARD_DCI_P3, 403 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 404 405 {HAL_DATASPACE_STANDARD_ADOBE_RGB, 406 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS} 407 }; 408 409 const std::map<uint32_t, int32_t> dataspace_transfer_map = 410 { 411 {HAL_DATASPACE_TRANSFER_UNSPECIFIED, 412 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 413 414 {HAL_DATASPACE_TRANSFER_LINEAR, 415 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 416 417 {HAL_DATASPACE_TRANSFER_SRGB, 418 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 419 420 {HAL_DATASPACE_TRANSFER_SMPTE_170M, 421 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 422 423 {HAL_DATASPACE_TRANSFER_GAMMA2_2, 424 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 425 426 {HAL_DATASPACE_TRANSFER_GAMMA2_6, 427 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 428 429 {HAL_DATASPACE_TRANSFER_GAMMA2_8, 430 MPP_ATTR_WCG | MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 431 432 {HAL_DATASPACE_TRANSFER_ST2084, 433 MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS}, 434 435 {HAL_DATASPACE_TRANSFER_HLG, 436 MPP_ATTR_HDR10 | MPP_ATTR_HDR10PLUS} 437 }; 438 439 void dumpExynosMPPImgInfo(uint32_t type, exynos_mpp_img_info &imgInfo); 440 441 struct ExynosMPPFrameInfo 442 { 443 uint32_t srcNum; 444 exynos_image srcInfo[NUM_MPP_SRC_BUFS]; 445 exynos_image dstInfo[NUM_MPP_SRC_BUFS]; 446 }; 447 448 class ExynosMPPSource { 449 public: 450 ExynosMPPSource(); 451 ExynosMPPSource(uint32_t sourceType, void *source); ~ExynosMPPSource()452 ~ExynosMPPSource(){}; 453 void setExynosImage(const exynos_image& src_img, const exynos_image& dst_img); 454 void setExynosMidImage(const exynos_image& mid_img); 455 456 uint32_t mSourceType; 457 void *mSource; 458 exynos_image mSrcImg; 459 exynos_image mDstImg; 460 exynos_image mMidImg; 461 462 ExynosMPP *mOtfMPP; 463 ExynosMPP *mM2mMPP; 464 465 /** 466 * SRAM/HW resource info 467 */ 468 std::unordered_map<tdm_attr_t, int32_t> mHWResourceAmount; getHWResourceAmount(tdm_attr_t attr)469 uint32_t getHWResourceAmount(tdm_attr_t attr) { return mHWResourceAmount[attr]; } 470 setHWResourceAmount(tdm_attr_t attr,uint32_t amount)471 uint32_t setHWResourceAmount(tdm_attr_t attr, uint32_t amount) { 472 mHWResourceAmount[attr] = amount; 473 return 0; 474 } 475 476 bool mNeedPreblending = false; 477 }; 478 479 bool exynosMPPSourceComp(const ExynosMPPSource* l, const ExynosMPPSource* r); 480 void dump(const restriction_size_t &restrictionSize, String8 &result); 481 482 class ExynosMPP { 483 private: 484 class ResourceManageThread: public Thread { 485 private: 486 ExynosMPP *mExynosMPP; 487 Condition mCondition; 488 List<exynos_mpp_img_info > mFreedBuffers; 489 List<int> mStateFences; 490 491 void freeBuffers(); 492 bool checkStateFences(); 493 public: 494 bool mRunning; 495 Mutex mMutex; 496 ResourceManageThread(ExynosMPP *exynosMPP); 497 ~ResourceManageThread(); 498 virtual bool threadLoop(); 499 void addFreedBuffer(exynos_mpp_img_info freedBuffer); 500 void addStateFence(int fence); 501 }; 502 503 public: 504 ExynosResourceManager *mResourceManager; 505 /** 506 * Resource type 507 * Ex: MPP_DPP_VGFS, MPP_DPP_VG, MPP_MSC, MPP_G2D 508 */ 509 uint32_t mMPPType; 510 uint32_t mPhysicalType; 511 uint32_t mLogicalType; 512 String8 mName; 513 uint32_t mPhysicalIndex; 514 uint32_t mLogicalIndex; 515 uint32_t mPreAssignDisplayInfo; 516 uint32_t mPreAssignDisplayList[DISPLAY_MODE_NUM]; 517 static int mainDisplayWidth; 518 static int mainDisplayHeight; 519 520 uint32_t mHWState; 521 int mLastStateFenceFd; 522 uint32_t mAssignedState; 523 bool mEnable; 524 525 ExynosDisplay *mAssignedDisplay; 526 527 /* Some resource can support blending feature 528 * then source can be multiple layers */ 529 Vector <ExynosMPPSource* > mAssignedSources; 530 uint32_t mMaxSrcLayerNum; 531 532 uint32_t mPrevAssignedState; 533 int32_t mPrevAssignedDisplayType; 534 int32_t mReservedDisplay; 535 536 android::sp<ResourceManageThread> mResourceManageThread; 537 float mCapacity; 538 float mUsedCapacity; 539 540 union { 541 struct { 542 float mUsedBaseCycles; 543 uint32_t mRotatedSrcCropBW; 544 uint32_t mNoRotatedSrcCropBW; 545 }; 546 }; 547 548 bool mAllocOutBufFlag; 549 bool mFreeOutBufFlag; 550 bool mHWBusyFlag; 551 /* For reuse previous frame */ 552 ExynosMPPFrameInfo mPrevFrameInfo; 553 struct exynos_mpp_img_info mSrcImgs[NUM_MPP_SRC_BUFS]; 554 struct exynos_mpp_img_info mDstImgs[NUM_MPP_DST_BUFS_DEFAULT]; 555 int32_t mCurrentDstBuf; 556 int32_t mPrivDstBuf; 557 bool mNeedCompressedTarget; 558 struct restriction_size mSrcSizeRestrictions[RESTRICTION_MAX]; 559 struct restriction_size mDstSizeRestrictions[RESTRICTION_MAX]; 560 561 // Force Dst buffer reallocation 562 dst_alloc_buf_size_t mDstAllocatedSize; 563 564 /* For libacryl */ 565 Acrylic *mAcrylicHandle; 566 567 bool mUseM2MSrcFence; 568 /* MPP's attribute bit (supported feature bit) */ 569 uint64_t mAttr; 570 571 uint32_t mAssignOrder; 572 uint32_t mAXIPortId; 573 uint32_t mHWBlockId; 574 575 bool mNeedSolidColorLayer; 576 577 ExynosMPP(ExynosResourceManager* resourceManager, 578 uint32_t physicalType, uint32_t logicalType, const char *name, 579 uint32_t physicalIndex, uint32_t logicalIndex, uint32_t preAssignInfo); 580 virtual ~ExynosMPP(); 581 582 int32_t allocOutBuf(uint32_t w, uint32_t h, uint32_t format, uint64_t usage, uint32_t index); 583 int32_t setOutBuf(buffer_handle_t outbuf, int32_t fence); 584 int32_t freeOutBuf(exynos_mpp_img_info dst); 585 int32_t doPostProcessing(struct exynos_image& dst); 586 int32_t setupRestriction(); 587 int32_t getSrcReleaseFence(uint32_t srcIndex); 588 int32_t resetSrcReleaseFence(); 589 int32_t getDstImageInfo(exynos_image *img); 590 int32_t setDstAcquireFence(int releaseFence); 591 int32_t resetDstReleaseFence(); 592 int32_t requestHWStateChange(uint32_t state); 593 int32_t setHWStateFence(int32_t fence); 594 virtual int64_t isSupported(ExynosDisplay &display, struct exynos_image &src, struct exynos_image &dst); 595 596 bool isDataspaceSupportedByMPP(struct exynos_image &src, struct exynos_image &dst); 597 bool isSupportedHDR(struct exynos_image &src, struct exynos_image &dst); 598 bool isSupportedBlend(struct exynos_image &src); 599 virtual bool isSupportedTransform(struct exynos_image &src); 600 bool isSupportedCapability(ExynosDisplay &display, struct exynos_image &src); 601 bool isSupportedDRM(struct exynos_image &src); 602 virtual bool isSupportedHStrideCrop(struct exynos_image &src); 603 bool checkDownscaleCap(const float resolution, const float displayRatio_V) const; checkSpecificRestriction(const uint32_t __unused refreshRate,const struct exynos_image __unused & src,const struct exynos_image __unused & dst)604 virtual bool checkSpecificRestriction(const uint32_t __unused refreshRate, 605 const struct exynos_image __unused &src, 606 const struct exynos_image __unused &dst) { 607 return false; 608 } 609 virtual uint32_t getDownscaleRestriction(const struct exynos_image &src, 610 const struct exynos_image &dst) const; 611 virtual uint32_t getMaxDownscale(const ExynosDisplay &display, const struct exynos_image &src, 612 const struct exynos_image &dst) const; 613 virtual uint32_t getMaxUpscale(const struct exynos_image &src, 614 const struct exynos_image &dst) const; 615 uint32_t getSrcMaxWidth(struct exynos_image &src); 616 uint32_t getSrcMaxHeight(struct exynos_image &src); 617 uint32_t getSrcMinWidth(struct exynos_image &src); 618 uint32_t getSrcMinWidth(uint32_t idx); 619 uint32_t getSrcMinHeight(struct exynos_image &src); 620 uint32_t getSrcMinHeight(uint32_t idx); 621 uint32_t getSrcWidthAlign(struct exynos_image &src); 622 uint32_t getSrcHeightAlign(struct exynos_image &src); 623 uint32_t getSrcMaxCropWidth(struct exynos_image &src); 624 uint32_t getSrcMaxCropHeight(struct exynos_image &src); 625 virtual uint32_t getSrcMaxCropSize(struct exynos_image &src); 626 uint32_t getSrcMinCropWidth(struct exynos_image &src); 627 uint32_t getSrcMinCropHeight(struct exynos_image &src); 628 virtual uint32_t getSrcXOffsetAlign(struct exynos_image &src); 629 uint32_t getSrcXOffsetAlign(uint32_t idx); 630 uint32_t getSrcYOffsetAlign(struct exynos_image &src); 631 uint32_t getSrcYOffsetAlign(uint32_t idx); 632 uint32_t getSrcCropWidthAlign(const struct exynos_image &src) const; 633 uint32_t getSrcCropWidthAlign(uint32_t idx) const; 634 uint32_t getSrcCropHeightAlign(const struct exynos_image &src) const; 635 uint32_t getSrcCropHeightAlign(uint32_t idx) const; 636 virtual bool isSrcFormatSupported(struct exynos_image &src); 637 virtual bool isDimLayerSupported(); 638 int32_t isSupportThis(uint32_t mSupportAttr); 639 640 uint32_t getDstMaxWidth(struct exynos_image &dst); 641 uint32_t getDstMaxHeight(struct exynos_image &dst); 642 uint32_t getDstMinWidth(struct exynos_image &dst); 643 uint32_t getDstMinHeight(struct exynos_image &dst); 644 virtual uint32_t getDstWidthAlign(const struct exynos_image &dst) const; 645 uint32_t getDstHeightAlign(const struct exynos_image &dst) const; 646 uint32_t getDstXOffsetAlign(struct exynos_image &dst); 647 uint32_t getDstYOffsetAlign(struct exynos_image &dst); 648 uint32_t getOutBufAlign(); 649 virtual bool isDstFormatSupported(struct exynos_image &dst); 650 int32_t isSupportLayerColorTransform( 651 struct exynos_image &src, struct exynos_image &dst); 652 uint32_t getSrcMaxBlendingNum(struct exynos_image &src, struct exynos_image &dst); 653 uint32_t getAssignedSourceNum(); 654 655 /* Based on multi-resolution support */ 656 void setDstAllocSize(uint32_t width, uint32_t height); 657 dst_alloc_buf_size_t getDstAllocSize(); 658 virtual bool needPreAllocation(); 659 660 int32_t resetMPP(); 661 int32_t resetAssignedState(); 662 int32_t resetAssignedState(ExynosMPPSource *mppSource); 663 int32_t reserveMPP(int32_t displayType = -1); 664 665 bool isAssignableState(ExynosDisplay *display, struct exynos_image &src, struct exynos_image &dst); 666 bool isAssignable(ExynosDisplay *display, struct exynos_image &src, struct exynos_image &dst, 667 float totalUsedCapacity); 668 int32_t assignMPP(ExynosDisplay *display, ExynosMPPSource* mppSource); 669 670 bool hasEnoughCapa(ExynosDisplay *display, struct exynos_image &src, struct exynos_image &dst, 671 float totalUsedCapa); 672 float getRequiredCapacity(ExynosDisplay *display, struct exynos_image &src, struct exynos_image &dst); 673 int32_t updateUsedCapacity(); 674 void resetUsedCapacity(); 675 int prioritize(int priority); 676 getMPPClockKhz()677 uint32_t getMPPClockKhz() { return mClockKhz; }; 678 679 void dump(String8& result); 680 uint32_t increaseDstBuffIndex(); 681 bool canSkipProcessing(); 682 683 virtual bool isSupportedCompression(struct exynos_image &src); 684 685 void closeFences(); 686 687 void reloadResourceForHWFC(); 688 void setTargetDisplayLuminance(uint16_t min, uint16_t max); 689 void setTargetDisplayDevice(int device); 690 691 virtual bool checkRotationCondition(struct exynos_image &src); 692 void updateAttr(); 693 void updatePreassignedDisplay(uint32_t fromDisplayBit, uint32_t toDisplayBit); 694 dstMetaInfo getDstMetaInfo(android_dataspace_t dstDataspace); 695 float getAssignedCapacity(); 696 setPPC(float ppc)697 void setPPC(float ppc) { mPPC = ppc; }; setClockKhz(uint32_t clock)698 void setClockKhz(uint32_t clock) { mClockKhz = clock; }; 699 initTDMInfo(uint32_t hwBlockIndex,uint32_t axiPortIndex)700 virtual void initTDMInfo(uint32_t hwBlockIndex, uint32_t axiPortIndex) { 701 mHWBlockId = hwBlockIndex; 702 mAXIPortId = axiPortIndex; 703 } getHWBlockId()704 virtual uint32_t getHWBlockId() { return mHWBlockId; } getAXIPortId()705 virtual uint32_t getAXIPortId() { return mAXIPortId; } 706 707 protected: 708 uint32_t getBufferType(uint64_t usage); 709 uint32_t getBufferType(const buffer_handle_t handle); 710 uint64_t getBufferUsage(uint64_t usage); 711 bool needCompressDstBuf() const; 712 uint32_t getAlignedDstFullWidth(struct exynos_image& dst); 713 bool needDstBufRealloc(struct exynos_image &dst, uint32_t index); 714 bool canUsePrevFrame(); 715 uint32_t getDstStrideAlignment(int format); 716 int32_t setupDst(exynos_mpp_img_info *dstImgInfo); 717 virtual int32_t doPostProcessingInternal(); 718 virtual int32_t setupLayer(exynos_mpp_img_info *srcImgInfo, 719 struct exynos_image &src, struct exynos_image &dst); setColorConversionInfo()720 virtual int32_t setColorConversionInfo() { return NO_ERROR; }; 721 722 uint32_t getRestrictionClassification(const struct exynos_image &img) const; 723 724 /* 725 * getPPC for src, dst referencing mppSources in mAssignedSources and 726 * assignCheckSrc, assignCheckDst that are likely to be added to the mAssignedSources 727 */ 728 float getPPC(const struct exynos_image &src, const struct exynos_image &dst, 729 const struct exynos_image &criteria, 730 const struct exynos_image *assignCheckSrc = NULL, 731 const struct exynos_image *assignCheckDst = NULL); getPPC()732 float getPPC() { return mPPC; }; 733 734 /* format and rotation index are defined by indexImage */ 735 void getPPCIndex(const struct exynos_image &indexImage, 736 const struct exynos_image &refImage, 737 uint32_t &formatIndex, uint32_t &rotIndex, uint32_t &scaleIndex, 738 const struct exynos_image &criteria); 739 740 float getRequiredBaseCycles(struct exynos_image &src, struct exynos_image &dst); 741 bool addCapacity(ExynosMPPSource* mppSource); 742 bool removeCapacity(ExynosMPPSource* mppSource); 743 /* 744 * This should be called by isCSCSupportedByMPP() 745 * This function checks additional restriction for color space conversion 746 */ 747 virtual bool checkCSCRestriction(struct exynos_image &src, struct exynos_image &dst); 748 749 /* 750 * Check additional conditions those have a capacity exception. 751 */ 752 virtual bool isCapacityExceptionCondition(float totalUsedCapacity, float requiredCapacity, 753 struct exynos_image &src); 754 755 uint32_t mClockKhz = 0; 756 float mPPC = 0; 757 }; 758 759 #endif //_EXYNOSMPP_H 760