1 /**********************************************************
2 * Copyright 2009-2023 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26 /**
27 * @file
28 * Common definitions for the VMware SVGA winsys.
29 *
30 * @author Jose Fonseca <jfonseca@vmware.com>
31 */
32
33
34 #ifndef VMW_SCREEN_H_
35 #define VMW_SCREEN_H_
36
37
38 #include "util/compiler.h"
39 #include "pipe/p_state.h"
40
41 #include "svga_winsys.h"
42 #include "pipebuffer/pb_buffer_fenced.h"
43 #include "util/u_thread.h"
44 #include <sys/types.h>
45
46 #define VMW_GMR_POOL_SIZE (16*1024*1024)
47 #define VMW_QUERY_POOL_SIZE (8192)
48 #define VMW_DEBUG_FLUSH_STACK 10
49
50 /*
51 * Something big, but arbitrary. The kernel reports an error if it can't
52 * handle this, and the svga driver will resort to multiple partial
53 * uploads.
54 */
55 #define VMW_MAX_BUFFER_SIZE (512*1024*1024)
56
57 struct pb_manager;
58 struct vmw_region;
59
60 struct vmw_cap_3d {
61 bool has_cap;
62 SVGA3dDevCapResult result;
63 };
64
65 struct vmw_winsys_screen
66 {
67 struct svga_winsys_screen base;
68
69 struct {
70 int drm_fd;
71 uint32_t hwversion;
72 uint32_t num_cap_3d;
73 struct vmw_cap_3d *cap_3d;
74 uint64_t max_mob_memory;
75 uint64_t max_surface_memory;
76 uint64_t max_texture_size;
77 bool have_drm_2_6;
78 bool have_drm_2_9;
79 uint32_t drm_execbuf_version;
80 bool have_drm_2_15;
81 bool have_drm_2_16;
82 bool have_drm_2_17;
83 bool have_drm_2_18;
84 bool have_drm_2_19;
85 bool have_drm_2_20;
86 } ioctl;
87
88 struct {
89 struct pb_manager *dma_base;
90 struct pb_manager *dma_mm;
91 struct pb_manager *query_mm;
92 struct pb_manager *query_fenced;
93 struct pb_manager *dma_fenced;
94 struct pb_manager *dma_cache;
95 struct pb_manager *dma_slab;
96 struct pb_manager *dma_slab_fenced;
97 } pools;
98
99 struct pb_fence_ops *fence_ops;
100
101 #ifdef VMX86_STATS
102 /*
103 * mksGuestStats TLS array; length must be power of two
104 */
105 struct {
106 void * stat_pages;
107 uint64_t stat_id;
108 uint32_t pid;
109 } mksstat_tls[64];
110
111 #endif
112 /*
113 * Screen instances
114 */
115 dev_t device;
116 int open_count;
117
118 cnd_t cs_cond;
119 mtx_t cs_mutex;
120
121 bool force_coherent;
122 bool cache_maps;
123 };
124
125
126 static inline struct vmw_winsys_screen *
vmw_winsys_screen(struct svga_winsys_screen * base)127 vmw_winsys_screen(struct svga_winsys_screen *base)
128 {
129 return (struct vmw_winsys_screen *)base;
130 }
131
132 /* */
133 uint32_t
134 vmw_region_size(struct vmw_region *region);
135
136 uint32
137 vmw_ioctl_context_create(struct vmw_winsys_screen *vws);
138
139 uint32
140 vmw_ioctl_extended_context_create(struct vmw_winsys_screen *vws,
141 bool vgpu10);
142
143 void
144 vmw_ioctl_context_destroy(struct vmw_winsys_screen *vws,
145 uint32 cid);
146
147 uint32
148 vmw_ioctl_surface_create(struct vmw_winsys_screen *vws,
149 SVGA3dSurface1Flags flags,
150 SVGA3dSurfaceFormat format,
151 unsigned usage,
152 SVGA3dSize size,
153 uint32 numFaces,
154 uint32 numMipLevels,
155 unsigned sampleCount);
156 uint32
157 vmw_ioctl_gb_surface_create(struct vmw_winsys_screen *vws,
158 SVGA3dSurfaceAllFlags flags,
159 SVGA3dSurfaceFormat format,
160 unsigned usage,
161 SVGA3dSize size,
162 uint32 numFaces,
163 uint32 numMipLevels,
164 unsigned sampleCount,
165 uint32 buffer_handle,
166 SVGA3dMSPattern multisamplePattern,
167 SVGA3dMSQualityLevel qualityLevel,
168 struct vmw_region **p_region);
169
170 int
171 vmw_ioctl_gb_surface_ref(struct vmw_winsys_screen *vws,
172 const struct winsys_handle *whandle,
173 SVGA3dSurfaceAllFlags *flags,
174 SVGA3dSurfaceFormat *format,
175 uint32_t *numMipLevels,
176 uint32_t *handle,
177 struct vmw_region **p_region);
178
179 void
180 vmw_ioctl_surface_destroy(struct vmw_winsys_screen *vws,
181 uint32 sid);
182
183 void
184 vmw_ioctl_command(struct vmw_winsys_screen *vws,
185 int32_t cid,
186 uint32_t throttle_us,
187 void *commands,
188 uint32_t size,
189 struct pipe_fence_handle **fence,
190 int32_t imported_fence_fd,
191 uint32_t flags);
192
193 struct vmw_region *
194 vmw_ioctl_region_create(struct vmw_winsys_screen *vws, uint32_t size);
195
196 void
197 vmw_ioctl_region_destroy(struct vmw_region *region);
198
199 struct SVGAGuestPtr
200 vmw_ioctl_region_ptr(struct vmw_region *region);
201
202 void *
203 vmw_ioctl_region_map(struct vmw_region *region);
204 void
205 vmw_ioctl_region_unmap(struct vmw_region *region);
206
207
208 int
209 vmw_ioctl_fence_finish(struct vmw_winsys_screen *vws,
210 uint32_t handle, uint32_t flags);
211
212 int
213 vmw_ioctl_fence_signalled(struct vmw_winsys_screen *vws,
214 uint32_t handle, uint32_t flags);
215
216 void
217 vmw_ioctl_fence_unref(struct vmw_winsys_screen *vws,
218 uint32_t handle);
219
220 uint32
221 vmw_ioctl_shader_create(struct vmw_winsys_screen *vws,
222 SVGA3dShaderType type,
223 uint32 code_len);
224 void
225 vmw_ioctl_shader_destroy(struct vmw_winsys_screen *vws, uint32 shid);
226
227 int
228 vmw_ioctl_syncforcpu(struct vmw_region *region,
229 bool dont_block,
230 bool readonly,
231 bool allow_cs);
232 void
233 vmw_ioctl_releasefromcpu(struct vmw_region *region,
234 bool readonly,
235 bool allow_cs);
236 /* Initialize parts of vmw_winsys_screen at startup:
237 */
238 bool vmw_ioctl_init(struct vmw_winsys_screen *vws);
239 bool vmw_pools_init(struct vmw_winsys_screen *vws);
240 bool vmw_query_pools_init(struct vmw_winsys_screen *vws);
241 bool vmw_winsys_screen_init_svga(struct vmw_winsys_screen *vws);
242
243 void vmw_ioctl_cleanup(struct vmw_winsys_screen *vws);
244 void vmw_pools_cleanup(struct vmw_winsys_screen *vws);
245
246 struct vmw_winsys_screen *vmw_winsys_create(int fd);
247 void vmw_winsys_destroy(struct vmw_winsys_screen *sws);
248 void vmw_winsys_screen_set_throttling(struct pipe_screen *screen,
249 uint32_t throttle_us);
250
251 struct pb_manager *
252 simple_fenced_bufmgr_create(struct pb_manager *provider,
253 struct pb_fence_ops *ops);
254 void
255 vmw_fences_signal(struct pb_fence_ops *fence_ops,
256 uint32_t signaled,
257 uint32_t emitted,
258 bool has_emitted);
259
260 struct svga_winsys_gb_shader *
261 vmw_svga_winsys_shader_create(struct svga_winsys_screen *sws,
262 SVGA3dShaderType type,
263 const uint32 *bytecode,
264 uint32 bytecodeLen);
265 void
266 vmw_svga_winsys_shader_destroy(struct svga_winsys_screen *sws,
267 struct svga_winsys_gb_shader *shader);
268
269 size_t
270 vmw_svga_winsys_stats_len(void);
271
272 #endif /* VMW_SCREEN_H_ */
273