1 /************************************************************************** 2 * 3 * Copyright 2017 Advanced Micro Devices, Inc. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 **************************************************************************/ 8 9 #ifndef _RADEON_VCN_ENC_H 10 #define _RADEON_VCN_ENC_H 11 12 #include "radeon_vcn.h" 13 #include "util/macros.h" 14 15 #include "ac_vcn_enc.h" 16 17 #define PIPE_ALIGN_IN_BLOCK_SIZE(value, alignment) DIV_ROUND_UP(value, alignment) 18 19 #define RADEON_ENC_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value)) 20 #define RADEON_ENC_BEGIN(cmd) \ 21 { \ 22 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \ 23 RADEON_ENC_CS(cmd) 24 #define RADEON_ENC_READ(buf, domain, off) \ 25 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off)) 26 #define RADEON_ENC_WRITE(buf, domain, off) \ 27 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off)) 28 #define RADEON_ENC_READWRITE(buf, domain, off) \ 29 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off)) 30 #define RADEON_ENC_END() \ 31 *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; \ 32 enc->total_task_size += *begin; \ 33 } 34 #define RADEON_ENC_ADDR_SWAP() \ 35 do { \ 36 unsigned int *low = &enc->cs.current.buf[enc->cs.current.cdw - 2]; \ 37 unsigned int *high = &enc->cs.current.buf[enc->cs.current.cdw - 1]; \ 38 unsigned int temp = *low; \ 39 *low = *high; \ 40 *high = temp; \ 41 } while(0) 42 43 #define RADEON_ENC_DESTROY_VIDEO_BUFFER(buf) \ 44 do { \ 45 if (buf) { \ 46 si_vid_destroy_buffer(buf); \ 47 FREE(buf); \ 48 (buf) = NULL; \ 49 } \ 50 } while(0) 51 52 typedef void (*radeon_enc_get_buffer)(struct pipe_resource *resource, struct pb_buffer_lean **handle, 53 struct radeon_surf **surface); 54 55 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context, 56 const struct pipe_video_codec *templat, 57 struct radeon_winsys *ws, 58 radeon_enc_get_buffer get_buffer); 59 60 struct radeon_enc_pic { 61 union { 62 enum pipe_h2645_enc_picture_type picture_type; 63 enum pipe_av1_enc_frame_type frame_type; 64 }; 65 66 unsigned frame_num; 67 unsigned pic_order_cnt; 68 unsigned pic_order_cnt_type; 69 unsigned ref_idx_l0; 70 bool ref_idx_l0_is_ltr; 71 unsigned ref_idx_l1; 72 bool ref_idx_l1_is_ltr; 73 unsigned crop_left; 74 unsigned crop_right; 75 unsigned crop_top; 76 unsigned crop_bottom; 77 unsigned general_tier_flag; 78 unsigned general_profile_idc; 79 unsigned general_level_idc; 80 unsigned max_poc; 81 unsigned log2_max_poc; 82 unsigned chroma_format_idc; 83 unsigned pic_width_in_luma_samples; 84 unsigned pic_height_in_luma_samples; 85 unsigned log2_diff_max_min_luma_coding_block_size; 86 unsigned log2_min_transform_block_size_minus2; 87 unsigned log2_diff_max_min_transform_block_size; 88 unsigned max_transform_hierarchy_depth_inter; 89 unsigned max_transform_hierarchy_depth_intra; 90 unsigned log2_parallel_merge_level_minus2; 91 unsigned bit_depth_luma_minus8; 92 unsigned bit_depth_chroma_minus8; 93 unsigned nal_unit_type; 94 unsigned max_num_merge_cand; 95 unsigned temporal_id; 96 unsigned num_temporal_layers; 97 unsigned temporal_layer_pattern_index; 98 rvcn_enc_quality_modes_t quality_modes; 99 rvcn_enc_vui_info vui_info; 100 101 bool not_referenced; 102 bool is_ltr; 103 unsigned ltr_idx; 104 bool is_idr; 105 bool need_sequence_header; 106 bool is_even_frame; 107 bool sample_adaptive_offset_enabled_flag; 108 bool pcm_enabled_flag; 109 bool sps_temporal_mvp_enabled_flag; 110 111 struct { 112 struct { 113 struct { 114 uint32_t enable_tile_obu:1; 115 uint32_t enable_render_size:1; 116 uint32_t enable_error_resilient_mode:1; 117 uint32_t enable_order_hint:1; 118 uint32_t enable_color_description:1; 119 uint32_t timing_info_present:1; 120 uint32_t timing_info_equal_picture_interval:1; 121 uint32_t frame_id_numbers_present:1; 122 uint32_t force_integer_mv:1; 123 uint32_t disable_screen_content_tools:1; 124 uint32_t is_obu_frame:1; 125 uint32_t stream_obu_frame:1; /* all frames have the same number of tiles */ 126 uint32_t need_av1_seq:1; 127 uint32_t av1_mark_long_term_reference:1; 128 }; 129 uint32_t render_width; 130 uint32_t render_height; 131 uint32_t frame_to_show_map_index; 132 enum pipe_av1_enc_frame_type last_frame_type; 133 uint32_t display_frame_id; 134 uint32_t frame_id; 135 uint32_t temporal_seq_num; 136 uint32_t order_hint; 137 uint32_t order_hint_bits; 138 uint32_t refresh_frame_flags; 139 uint32_t reference_delta_frame_id; 140 uint32_t reference_frame_index; 141 uint32_t reference_order_hint[RENCDOE_AV1_NUM_REF_FRAMES]; 142 uint32_t *copy_start; 143 }; 144 rvcn_enc_av1_spec_misc_t av1_spec_misc; 145 rvcn_enc_av1_cdf_default_table_t av1_cdf_default_table; 146 rvcn_enc_av1_timing_info_t av1_timing_info; 147 rvcn_enc_av1_color_description_t av1_color_description; 148 uint32_t count_last_layer; 149 rvcn_enc_av1_ref_frame_t frames[RENCDOE_AV1_NUM_REF_FRAMES]; 150 rvcn_enc_av1_recon_slot_t recon_slots[RENCDOE_AV1_NUM_REF_FRAMES + 1]; 151 uint8_t av1_ref_frame_idx[RENCDOE_AV1_REFS_PER_FRAME]; 152 void *av1_ref_list[RENCDOE_AV1_NUM_REF_FRAMES]; 153 void *av1_recon_frame; 154 uint32_t av1_ref_frame_ctrl_l0; 155 uint32_t av1_ref_frame_ctrl_l1; 156 uint32_t av1_ltr_seq; 157 }; 158 159 rvcn_enc_session_info_t session_info; 160 rvcn_enc_task_info_t task_info; 161 rvcn_enc_session_init_t session_init; 162 rvcn_enc_layer_control_t layer_ctrl; 163 rvcn_enc_layer_select_t layer_sel; 164 rvcn_enc_h264_slice_control_t slice_ctrl; 165 rvcn_enc_hevc_slice_control_t hevc_slice_ctrl; 166 rvcn_enc_h264_spec_misc_t spec_misc; 167 rvcn_enc_hevc_spec_misc_t hevc_spec_misc; 168 rvcn_enc_rate_ctl_session_init_t rc_session_init; 169 rvcn_enc_rate_ctl_layer_init_t rc_layer_init[RENCODE_MAX_NUM_TEMPORAL_LAYERS]; 170 rvcn_enc_h264_encode_params_t h264_enc_params; 171 rvcn_enc_h264_deblocking_filter_t h264_deblock; 172 rvcn_enc_hevc_deblocking_filter_t hevc_deblock; 173 rvcn_enc_rate_ctl_per_picture_t rc_per_pic; 174 rvcn_enc_quality_params_t quality_params; 175 rvcn_enc_encode_context_buffer_t ctx_buf; 176 rvcn_enc_video_bitstream_buffer_t bit_buf; 177 rvcn_enc_feedback_buffer_t fb_buf; 178 rvcn_enc_intra_refresh_t intra_refresh; 179 rvcn_enc_encode_params_t enc_params; 180 rvcn_enc_stats_t enc_statistics; 181 rvcn_enc_input_format_t enc_input_format; 182 rvcn_enc_output_format_t enc_output_format; 183 rvcn_enc_qp_map_t enc_qp_map; 184 }; 185 186 struct radeon_encoder { 187 struct pipe_video_codec base; 188 189 void (*begin)(struct radeon_encoder *enc); 190 void (*before_encode)(struct radeon_encoder *enc); 191 void (*encode)(struct radeon_encoder *enc); 192 void (*destroy)(struct radeon_encoder *enc); 193 void (*session_info)(struct radeon_encoder *enc); 194 void (*task_info)(struct radeon_encoder *enc, bool need_feedback); 195 void (*session_init)(struct radeon_encoder *enc); 196 void (*layer_control)(struct radeon_encoder *enc); 197 void (*layer_select)(struct radeon_encoder *enc); 198 void (*slice_control)(struct radeon_encoder *enc); 199 void (*spec_misc)(struct radeon_encoder *enc); 200 void (*rc_session_init)(struct radeon_encoder *enc); 201 void (*rc_layer_init)(struct radeon_encoder *enc); 202 void (*deblocking_filter)(struct radeon_encoder *enc); 203 void (*quality_params)(struct radeon_encoder *enc); 204 void (*nalu_sps)(struct radeon_encoder *enc); 205 void (*nalu_pps)(struct radeon_encoder *enc); 206 void (*nalu_vps)(struct radeon_encoder *enc); 207 void (*nalu_aud)(struct radeon_encoder *enc); 208 void (*nalu_sei)(struct radeon_encoder *enc); 209 void (*nalu_prefix)(struct radeon_encoder *enc); 210 void (*slice_header)(struct radeon_encoder *enc); 211 void (*ctx)(struct radeon_encoder *enc); 212 void (*bitstream)(struct radeon_encoder *enc); 213 void (*feedback)(struct radeon_encoder *enc); 214 void (*intra_refresh)(struct radeon_encoder *enc); 215 void (*rc_per_pic)(struct radeon_encoder *enc); 216 void (*encode_params)(struct radeon_encoder *enc); 217 void (*encode_params_codec_spec)(struct radeon_encoder *enc); 218 void (*qp_map)(struct radeon_encoder *enc); 219 void (*op_init)(struct radeon_encoder *enc); 220 void (*op_close)(struct radeon_encoder *enc); 221 void (*op_enc)(struct radeon_encoder *enc); 222 void (*op_init_rc)(struct radeon_encoder *enc); 223 void (*op_init_rc_vbv)(struct radeon_encoder *enc); 224 void (*op_preset)(struct radeon_encoder *enc); 225 void (*encode_headers)(struct radeon_encoder *enc); 226 void (*input_format)(struct radeon_encoder *enc); 227 void (*output_format)(struct radeon_encoder *enc); 228 void (*encode_statistics)(struct radeon_encoder *enc); 229 void (*obu_instructions)(struct radeon_encoder *enc); 230 void (*cdf_default_table)(struct radeon_encoder *enc); 231 /* mq is used for preversing multiple queue ibs */ 232 void (*mq_begin)(struct radeon_encoder *enc); 233 void (*mq_encode)(struct radeon_encoder *enc); 234 void (*mq_destroy)(struct radeon_encoder *enc); 235 236 unsigned stream_handle; 237 238 struct pipe_screen *screen; 239 struct radeon_winsys *ws; 240 struct radeon_cmdbuf cs; 241 242 radeon_enc_get_buffer get_buffer; 243 244 struct pb_buffer_lean *handle; 245 struct radeon_surf *luma; 246 struct radeon_surf *chroma; 247 248 struct pb_buffer_lean *bs_handle; 249 unsigned bs_size; 250 251 struct rvid_buffer *si; 252 struct rvid_buffer *fb; 253 struct rvid_buffer *dpb; 254 struct rvid_buffer *cdf; 255 struct rvid_buffer *roi; 256 struct radeon_enc_pic enc_pic; 257 struct pb_buffer_lean *stats; 258 rvcn_enc_cmd_t cmd; 259 260 unsigned alignment; 261 unsigned shifter; 262 unsigned bits_in_shifter; 263 unsigned num_zeros; 264 unsigned byte_index; 265 unsigned bits_output; 266 unsigned bits_size; 267 uint32_t total_task_size; 268 uint32_t *p_task_size; 269 struct rvcn_sq_var sq; 270 271 bool emulation_prevention; 272 bool need_feedback; 273 bool need_rate_control; 274 unsigned dpb_size; 275 unsigned roi_size; 276 rvcn_enc_picture_info_t dpb_info[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES]; 277 unsigned max_ltr_idx; 278 279 struct pipe_context *ectx; 280 }; 281 282 void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer_lean *buf, 283 unsigned usage, enum radeon_bo_domain domain, signed offset); 284 285 void radeon_enc_dummy(struct radeon_encoder *enc); 286 287 void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set); 288 289 void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte); 290 291 void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte); 292 293 void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value, 294 unsigned int num_bits); 295 296 void radeon_enc_reset(struct radeon_encoder *enc); 297 298 void radeon_enc_byte_align(struct radeon_encoder *enc); 299 300 void radeon_enc_flush_headers(struct radeon_encoder *enc); 301 302 void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value); 303 304 void radeon_enc_code_se(struct radeon_encoder *enc, int value); 305 306 void radeon_enc_code_uvlc(struct radeon_encoder *enc, unsigned int value); 307 308 void radeon_enc_code_leb128(unsigned char *buf, unsigned int value, 309 unsigned int num_bytes); 310 311 void radeon_enc_1_2_init(struct radeon_encoder *enc); 312 313 void radeon_enc_2_0_init(struct radeon_encoder *enc); 314 315 void radeon_enc_3_0_init(struct radeon_encoder *enc); 316 317 void radeon_enc_4_0_init(struct radeon_encoder *enc); 318 319 void radeon_enc_av1_bs_instruction_type(struct radeon_encoder *enc, 320 unsigned int inst, unsigned int obu_type); 321 322 unsigned char *radeon_enc_av1_header_size_offset(struct radeon_encoder *enc); 323 324 unsigned int radeon_enc_value_bits(unsigned int value); 325 326 #endif // _RADEON_VCN_ENC_H 327