1 /*
2 * Copyright © 2014-2017 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file v3dx_simulator.c
26 *
27 * Implements the actual HW interaction betweeh the GL driver's V3D simulator and the simulator.
28 *
29 * The register headers between V3D versions will have conflicting defines, so
30 * all register interactions appear in this file and are compiled per V3D version
31 * we support.
32 */
33
34 #ifdef USE_V3D_SIMULATOR
35
36 #include <assert.h>
37 #include <stdbool.h>
38 #include <stdio.h>
39
40 #include "v3d_simulator.h"
41 #include "v3d_simulator_wrapper.h"
42
43 #include "common/v3d_performance_counters.h"
44
45 #include "util/macros.h"
46 #include "util/bitscan.h"
47 #include "drm-uapi/v3d_drm.h"
48
49 #define HW_REGISTER_RO(x) (x)
50 #define HW_REGISTER_RW(x) (x)
51 #if V3D_VERSION == 71
52 #include "libs/core/v3d/registers/7.1.6.0/v3d.h"
53 #else
54 #if V3D_VERSION == 42
55 #include "libs/core/v3d/registers/4.2.14.0/v3d.h"
56 #endif
57 #endif
58
59 #define V3D_WRITE(reg, val) v3d_hw_write_reg(v3d, reg, val)
60 #define V3D_READ(reg) v3d_hw_read_reg(v3d, reg)
61
62 /* Invalidates the L2C cache. This is a read-only cache for uniforms and instructions. */
63 static void
v3d_invalidate_l2c(struct v3d_hw * v3d)64 v3d_invalidate_l2c(struct v3d_hw *v3d)
65 {
66 if (V3D_VERSION >= 33)
67 return;
68
69 V3D_WRITE(V3D_CTL_0_L2CACTL,
70 V3D_CTL_0_L2CACTL_L2CCLR_SET |
71 V3D_CTL_0_L2CACTL_L2CENA_SET);
72 }
73
74 enum v3d_l2t_cache_flush_mode {
75 V3D_CACHE_FLUSH_MODE_FLUSH,
76 V3D_CACHE_FLUSH_MODE_CLEAR,
77 V3D_CACHE_FLUSH_MODE_CLEAN,
78 };
79
80 /* Invalidates texture L2 cachelines */
81 static void
v3d_invalidate_l2t(struct v3d_hw * v3d)82 v3d_invalidate_l2t(struct v3d_hw *v3d)
83 {
84 V3D_WRITE(V3D_CTL_0_L2TFLSTA, 0);
85 V3D_WRITE(V3D_CTL_0_L2TFLEND, ~0);
86 V3D_WRITE(V3D_CTL_0_L2TCACTL,
87 V3D_CTL_0_L2TCACTL_L2TFLS_SET |
88 (V3D_CACHE_FLUSH_MODE_FLUSH << V3D_CTL_0_L2TCACTL_L2TFLM_LSB));
89 }
90
91 /*
92 * Wait for l2tcactl, used for flushes.
93 *
94 * FIXME: for a multicore scenario we should pass here the core. All wrapper
95 * assumes just one core, so would be better to handle that on that case.
96 */
v3d_core_wait_l2tcactl(struct v3d_hw * v3d,uint32_t ctrl)97 static UNUSED void v3d_core_wait_l2tcactl(struct v3d_hw *v3d,
98 uint32_t ctrl)
99 {
100 assert(!(ctrl & ~(V3D_CTL_0_L2TCACTL_TMUWCF_SET | V3D_CTL_0_L2TCACTL_L2TFLS_SET)));
101
102 while (V3D_READ(V3D_CTL_0_L2TCACTL) & ctrl) {
103 v3d_hw_tick(v3d);
104 }
105 }
106
107 /* Flushes dirty texture cachelines from the L1 write combiner */
108 static void
v3d_flush_l1td(struct v3d_hw * v3d)109 v3d_flush_l1td(struct v3d_hw *v3d)
110 {
111 V3D_WRITE(V3D_CTL_0_L2TCACTL,
112 V3D_CTL_0_L2TCACTL_TMUWCF_SET);
113
114 /* Note: here the kernel (and previous versions of the simulator
115 * wrapper) is using V3D_CTL_0_L2TCACTL_L2TFLS_SET, as with l2t. We
116 * understand that it makes more sense to do like this. We need to
117 * confirm which one is doing it correctly. So far things work fine on
118 * the simulator this way.
119 */
120 v3d_core_wait_l2tcactl(v3d, V3D_CTL_0_L2TCACTL_TMUWCF_SET);
121 }
122
123 /* Flushes dirty texture L2 cachelines */
124 static void
v3d_flush_l2t(struct v3d_hw * v3d)125 v3d_flush_l2t(struct v3d_hw *v3d)
126 {
127 V3D_WRITE(V3D_CTL_0_L2TFLSTA, 0);
128 V3D_WRITE(V3D_CTL_0_L2TFLEND, ~0);
129 V3D_WRITE(V3D_CTL_0_L2TCACTL,
130 V3D_CTL_0_L2TCACTL_L2TFLS_SET |
131 (V3D_CACHE_FLUSH_MODE_CLEAN << V3D_CTL_0_L2TCACTL_L2TFLM_LSB));
132
133 v3d_core_wait_l2tcactl(v3d, V3D_CTL_0_L2TCACTL_L2TFLS_SET);
134 }
135
136 /* Invalidates the slice caches. These are read-only caches. */
137 static void
v3d_invalidate_slices(struct v3d_hw * v3d)138 v3d_invalidate_slices(struct v3d_hw *v3d)
139 {
140 V3D_WRITE(V3D_CTL_0_SLCACTL, ~0);
141 }
142
143 static void
v3d_invalidate_caches(struct v3d_hw * v3d)144 v3d_invalidate_caches(struct v3d_hw *v3d)
145 {
146 v3d_invalidate_l2c(v3d);
147 v3d_invalidate_l2t(v3d);
148 v3d_invalidate_slices(v3d);
149 }
150
151 static uint32_t g_gmp_ofs;
152 static void
v3d_reload_gmp(struct v3d_hw * v3d)153 v3d_reload_gmp(struct v3d_hw *v3d)
154 {
155 /* Completely reset the GMP. */
156 V3D_WRITE(V3D_GMP_CFG,
157 V3D_GMP_CFG_PROTENABLE_SET);
158 V3D_WRITE(V3D_GMP_TABLE_ADDR, g_gmp_ofs);
159 V3D_WRITE(V3D_GMP_CLEAR_LOAD, ~0);
160 while (V3D_READ(V3D_GMP_STATUS) &
161 V3D_GMP_STATUS_CFG_BUSY_SET) {
162 ;
163 }
164 }
165
166 static UNUSED void
v3d_flush_caches(struct v3d_hw * v3d)167 v3d_flush_caches(struct v3d_hw *v3d)
168 {
169 v3d_flush_l1td(v3d);
170 v3d_flush_l2t(v3d);
171 }
172
173 #if V3D_VERSION < 71
174 #define TFU_REG(NAME) V3D_TFU_ ## NAME
175 #else
176 #define TFU_REG(NAME) V3D_IFC_ ## NAME
177 #endif
178
179
180 int
v3dX(simulator_submit_tfu_ioctl)181 v3dX(simulator_submit_tfu_ioctl)(struct v3d_hw *v3d,
182 struct drm_v3d_submit_tfu *args)
183 {
184 int last_vtct = V3D_READ(TFU_REG(CS)) & V3D_TFU_CS_CVTCT_SET;
185
186 V3D_WRITE(TFU_REG(IIA), args->iia);
187 V3D_WRITE(TFU_REG(IIS), args->iis);
188 V3D_WRITE(TFU_REG(ICA), args->ica);
189 V3D_WRITE(TFU_REG(IUA), args->iua);
190 V3D_WRITE(TFU_REG(IOA), args->ioa);
191 #if V3D_VERSION >= 71
192 V3D_WRITE(TFU_REG(IOC), args->v71.ioc);
193 #endif
194 V3D_WRITE(TFU_REG(IOS), args->ios);
195 V3D_WRITE(TFU_REG(COEF0), args->coef[0]);
196 V3D_WRITE(TFU_REG(COEF1), args->coef[1]);
197 V3D_WRITE(TFU_REG(COEF2), args->coef[2]);
198 V3D_WRITE(TFU_REG(COEF3), args->coef[3]);
199
200 V3D_WRITE(TFU_REG(ICFG), args->icfg);
201
202 while ((V3D_READ(TFU_REG(CS)) & V3D_TFU_CS_CVTCT_SET) == last_vtct) {
203 v3d_hw_tick(v3d);
204 }
205
206 return 0;
207 }
208
209 int
v3dX(simulator_submit_csd_ioctl)210 v3dX(simulator_submit_csd_ioctl)(struct v3d_hw *v3d,
211 struct drm_v3d_submit_csd *args,
212 uint32_t gmp_ofs)
213 {
214 #if V3D_VERSION >= 42
215 int last_completed_jobs = (V3D_READ(V3D_CSD_0_STATUS) &
216 V3D_CSD_0_STATUS_NUM_COMPLETED_JOBS_SET);
217 g_gmp_ofs = gmp_ofs;
218 v3d_reload_gmp(v3d);
219
220 v3d_invalidate_caches(v3d);
221
222 V3D_WRITE(V3D_CSD_0_QUEUED_CFG1, args->cfg[1]);
223 V3D_WRITE(V3D_CSD_0_QUEUED_CFG2, args->cfg[2]);
224 V3D_WRITE(V3D_CSD_0_QUEUED_CFG3, args->cfg[3]);
225 V3D_WRITE(V3D_CSD_0_QUEUED_CFG4, args->cfg[4]);
226 V3D_WRITE(V3D_CSD_0_QUEUED_CFG5, args->cfg[5]);
227 V3D_WRITE(V3D_CSD_0_QUEUED_CFG6, args->cfg[6]);
228 #if V3D_VERSION >= 71
229 V3D_WRITE(V3D_CSD_0_QUEUED_CFG7, 0);
230 #endif
231 /* CFG0 kicks off the job */
232 V3D_WRITE(V3D_CSD_0_QUEUED_CFG0, args->cfg[0]);
233
234 /* Now we wait for the dispatch to finish. The safest way is to check
235 * if NUM_COMPLETED_JOBS has increased. Note that in spite of that
236 * name that register field is about the number of completed
237 * dispatches.
238 */
239 while ((V3D_READ(V3D_CSD_0_STATUS) &
240 V3D_CSD_0_STATUS_NUM_COMPLETED_JOBS_SET) == last_completed_jobs) {
241 v3d_hw_tick(v3d);
242 }
243
244 v3d_flush_caches(v3d);
245
246 return 0;
247 #else
248 return -1;
249 #endif
250 }
251
252 int
v3dX(simulator_get_param_ioctl)253 v3dX(simulator_get_param_ioctl)(struct v3d_hw *v3d,
254 struct drm_v3d_get_param *args)
255 {
256 static const uint32_t reg_map[] = {
257 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_CTL_UIFCFG,
258 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_CTL_IDENT1,
259 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_CTL_IDENT2,
260 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_CTL_IDENT3,
261 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_0_IDENT0,
262 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_0_IDENT1,
263 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_0_IDENT2,
264 };
265
266 switch (args->param) {
267 case DRM_V3D_PARAM_SUPPORTS_TFU:
268 args->value = 1;
269 return 0;
270 case DRM_V3D_PARAM_SUPPORTS_CSD:
271 args->value = V3D_VERSION >= 42;
272 return 0;
273 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
274 args->value = 1;
275 return 0;
276 case DRM_V3D_PARAM_SUPPORTS_PERFMON:
277 args->value = V3D_VERSION >= 42;
278 return 0;
279 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT:
280 args->value = 1;
281 return 0;
282 case DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE:
283 args->value = 1;
284 return 0;
285 }
286
287 if (args->param < ARRAY_SIZE(reg_map) && reg_map[args->param]) {
288 args->value = V3D_READ(reg_map[args->param]);
289 return 0;
290 }
291
292 fprintf(stderr, "Unknown DRM_IOCTL_V3D_GET_PARAM(%lld)\n",
293 (long long)args->value);
294 abort();
295 }
296
297 static struct v3d_hw *v3d_isr_hw;
298
299
300 static void
v3d_isr_core(struct v3d_hw * v3d,unsigned core)301 v3d_isr_core(struct v3d_hw *v3d,
302 unsigned core)
303 {
304 /* FIXME: so far we are assuming just one core, and using only the _0_
305 * registers. If we add multiple-core on the simulator, we would need
306 * to pass core as a parameter, and chose the proper registers.
307 */
308 assert(core == 0);
309 uint32_t core_status = V3D_READ(V3D_CTL_0_INT_STS);
310 V3D_WRITE(V3D_CTL_0_INT_CLR, core_status);
311
312 if (core_status & V3D_CTL_0_INT_STS_INT_OUTOMEM_SET) {
313 uint32_t size = 256 * 1024;
314 uint32_t offset = v3d_simulator_get_spill(size);
315
316 v3d_reload_gmp(v3d);
317
318 V3D_WRITE(V3D_PTB_0_BPOA, offset);
319 V3D_WRITE(V3D_PTB_0_BPOS, size);
320 return;
321 }
322
323 #if V3D_VERSION <= 42
324 if (core_status & V3D_CTL_0_INT_STS_INT_GMPV_SET) {
325 fprintf(stderr, "GMP violation at 0x%08x\n",
326 V3D_READ(V3D_GMP_VIO_ADDR));
327 } else {
328 fprintf(stderr,
329 "Unexpected ISR with core status 0x%08x\n",
330 core_status);
331 }
332 abort();
333 #endif
334 }
335
336 static void
handle_mmu_interruptions(struct v3d_hw * v3d,uint32_t hub_status)337 handle_mmu_interruptions(struct v3d_hw *v3d,
338 uint32_t hub_status)
339 {
340 bool wrv = hub_status & V3D_HUB_CTL_INT_STS_INT_MMU_WRV_SET;
341 bool pti = hub_status & V3D_HUB_CTL_INT_STS_INT_MMU_PTI_SET;
342 bool cap = hub_status & V3D_HUB_CTL_INT_STS_INT_MMU_CAP_SET;
343
344 if (!(pti || cap || wrv))
345 return;
346
347 const char *client = "?";
348 uint32_t axi_id = V3D_READ(V3D_MMU_VIO_ID);
349 uint32_t va_width = 30;
350
351 static const char *const v3d42_axi_ids[] = {
352 "L2T",
353 "PTB",
354 "PSE",
355 "TLB",
356 "CLE",
357 "TFU",
358 "MMU",
359 "GMP",
360 };
361
362 axi_id = axi_id >> 5;
363 if (axi_id < ARRAY_SIZE(v3d42_axi_ids))
364 client = v3d42_axi_ids[axi_id];
365
366 uint32_t mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
367
368 va_width += ((mmu_debug & V3D_MMU_DEBUG_INFO_VA_WIDTH_SET)
369 >> V3D_MMU_DEBUG_INFO_VA_WIDTH_LSB);
370
371 /* Only the top bits (final number depends on the gen) of the virtual
372 * address are reported in the MMU VIO_ADDR register.
373 */
374 uint64_t vio_addr = ((uint64_t)V3D_READ(V3D_MMU_VIO_ADDR) <<
375 (va_width - 32));
376
377 /* Difference with the kernel: here were are going to abort after
378 * logging, so we don't bother with some stuff that the kernel does,
379 * like restoring the MMU ctrl bits
380 */
381
382 fprintf(stderr, "MMU error from client %s (%d) at 0x%llx%s%s%s\n",
383 client, axi_id, (long long) vio_addr,
384 wrv ? ", write violation" : "",
385 pti ? ", pte invalid" : "",
386 cap ? ", cap exceeded" : "");
387
388 abort();
389 }
390
391 static void
v3d_isr_hub(struct v3d_hw * v3d)392 v3d_isr_hub(struct v3d_hw *v3d)
393 {
394 uint32_t hub_status = V3D_READ(V3D_HUB_CTL_INT_STS);
395
396 /* Acknowledge the interrupts we're handling here */
397 V3D_WRITE(V3D_HUB_CTL_INT_CLR, hub_status);
398
399 if (hub_status & V3D_HUB_CTL_INT_STS_INT_TFUC_SET) {
400 /* FIXME: we were not able to raise this exception. We let the
401 * unreachable here, so we could get one if it is raised on
402 * the future. In any case, note that for this case we would
403 * only be doing debugging log.
404 */
405 unreachable("TFU Conversion Complete interrupt not handled");
406 }
407
408 handle_mmu_interruptions(v3d, hub_status);
409
410 #if V3D_VERSION == 71
411 if (hub_status & V3D_HUB_CTL_INT_STS_INT_GMPV_SET) {
412 fprintf(stderr, "GMP violation at 0x%08x\n",
413 V3D_READ(V3D_GMP_VIO_ADDR));
414 } else {
415 fprintf(stderr,
416 "Unexpected ISR with status 0x%08x\n",
417 hub_status);
418 }
419 abort();
420 #endif
421 }
422
423 static void
v3d_isr(uint32_t hub_status)424 v3d_isr(uint32_t hub_status)
425 {
426 struct v3d_hw *v3d = v3d_isr_hw;
427 uint32_t mask = hub_status;
428
429 /* Check the hub_status bits */
430 while (mask) {
431 unsigned core = u_bit_scan(&mask);
432
433 if (core == v3d_hw_get_hub_core())
434 v3d_isr_hub(v3d);
435 else
436 v3d_isr_core(v3d, core);
437 }
438
439 return;
440 }
441
442 void
v3dX(simulator_init_regs)443 v3dX(simulator_init_regs)(struct v3d_hw *v3d)
444 {
445 /* FIXME: the kernel captures some additional core interrupts here,
446 * for tracing. Perhaps we should evaluate to do the same here and add
447 * some debug options.
448 */
449 uint32_t core_interrupts = V3D_CTL_0_INT_STS_INT_OUTOMEM_SET;
450 #if V3D_VERSION <= 42
451 core_interrupts |= V3D_CTL_0_INT_STS_INT_GMPV_SET;
452 #endif
453
454 V3D_WRITE(V3D_CTL_0_INT_MSK_SET, ~core_interrupts);
455 V3D_WRITE(V3D_CTL_0_INT_MSK_CLR, core_interrupts);
456
457 uint32_t hub_interrupts =
458 (V3D_HUB_CTL_INT_STS_INT_MMU_WRV_SET | /* write violation */
459 V3D_HUB_CTL_INT_STS_INT_MMU_PTI_SET | /* page table invalid */
460 V3D_HUB_CTL_INT_STS_INT_MMU_CAP_SET | /* CAP exceeded */
461 V3D_HUB_CTL_INT_STS_INT_TFUC_SET); /* TFU conversion */
462
463 #if V3D_VERSION == 71
464 hub_interrupts |= V3D_HUB_CTL_INT_STS_INT_GMPV_SET;
465 #endif
466 V3D_WRITE(V3D_HUB_CTL_INT_MSK_SET, ~hub_interrupts);
467 V3D_WRITE(V3D_HUB_CTL_INT_MSK_CLR, hub_interrupts);
468
469 v3d_isr_hw = v3d;
470 v3d_hw_set_isr(v3d, v3d_isr);
471 }
472
473 void
v3dX(simulator_submit_cl_ioctl)474 v3dX(simulator_submit_cl_ioctl)(struct v3d_hw *v3d,
475 struct drm_v3d_submit_cl *submit,
476 uint32_t gmp_ofs)
477 {
478 int last_bfc = (V3D_READ(V3D_CLE_0_BFC) &
479 V3D_CLE_0_BFC_BMFCT_SET);
480
481 int last_rfc = (V3D_READ(V3D_CLE_0_RFC) &
482 V3D_CLE_0_RFC_RMFCT_SET);
483
484 g_gmp_ofs = gmp_ofs;
485 v3d_reload_gmp(v3d);
486
487 v3d_invalidate_caches(v3d);
488
489 if (submit->qma) {
490 V3D_WRITE(V3D_CLE_0_CT0QMA, submit->qma);
491 V3D_WRITE(V3D_CLE_0_CT0QMS, submit->qms);
492 }
493 if (submit->qts) {
494 V3D_WRITE(V3D_CLE_0_CT0QTS,
495 V3D_CLE_0_CT0QTS_CTQTSEN_SET |
496 submit->qts);
497 }
498 V3D_WRITE(V3D_CLE_0_CT0QBA, submit->bcl_start);
499 V3D_WRITE(V3D_CLE_0_CT0QEA, submit->bcl_end);
500
501 /* Wait for bin to complete before firing render. The kernel's
502 * scheduler implements this using the GPU scheduler blocking on the
503 * bin fence completing. (We don't use HW semaphores).
504 */
505 while ((V3D_READ(V3D_CLE_0_BFC) &
506 V3D_CLE_0_BFC_BMFCT_SET) == last_bfc) {
507 v3d_hw_tick(v3d);
508 }
509
510 v3d_invalidate_caches(v3d);
511
512 V3D_WRITE(V3D_CLE_0_CT1QBA, submit->rcl_start);
513 V3D_WRITE(V3D_CLE_0_CT1QEA, submit->rcl_end);
514
515 while ((V3D_READ(V3D_CLE_0_RFC) &
516 V3D_CLE_0_RFC_RMFCT_SET) == last_rfc) {
517 v3d_hw_tick(v3d);
518 }
519 }
520
521 #define V3D_PCTR_0_PCTR_N(x) (V3D_PCTR_0_PCTR0 + 4 * (x))
522 #define V3D_PCTR_0_SRC_N(x) (V3D_PCTR_0_SRC_0_3 + 4 * (x))
523 #define V3D_PCTR_0_SRC_N_SHIFT(x) ((x) * 8)
524 #define V3D_PCTR_0_SRC_N_MASK(x) (BITFIELD_RANGE(V3D_PCTR_0_SRC_N_SHIFT(x), \
525 V3D_PCTR_0_SRC_N_SHIFT(x) + \
526 V3D_PCTR_0_SRC_0_3_PCTRS0_MSB))
527
528 void
v3dX(simulator_perfmon_start)529 v3dX(simulator_perfmon_start)(struct v3d_hw *v3d,
530 uint32_t ncounters,
531 uint8_t *events)
532 {
533 int i, j;
534 uint32_t source;
535 uint32_t mask = BITFIELD_RANGE(0, ncounters);
536
537 for (i = 0; i < ncounters; i+=4) {
538 source = i / 4;
539 uint32_t channels = 0;
540 for (j = 0; j < 4 && (i + j) < ncounters; j++)
541 channels |= events[i + j] << V3D_PCTR_0_SRC_N_SHIFT(j);
542 V3D_WRITE(V3D_PCTR_0_SRC_N(source), channels);
543 }
544 V3D_WRITE(V3D_PCTR_0_CLR, mask);
545 V3D_WRITE(V3D_PCTR_0_OVERFLOW, mask);
546 V3D_WRITE(V3D_PCTR_0_EN, mask);
547 }
548
v3dX(simulator_perfmon_stop)549 void v3dX(simulator_perfmon_stop)(struct v3d_hw *v3d,
550 uint32_t ncounters,
551 uint64_t *values)
552 {
553 int i;
554
555 for (i = 0; i < ncounters; i++)
556 values[i] += V3D_READ(V3D_PCTR_0_PCTR_N(i));
557
558 V3D_WRITE(V3D_PCTR_0_EN, 0);
559 }
560
v3dX(simulator_get_perfcnt_total)561 void v3dX(simulator_get_perfcnt_total)(uint32_t *count)
562 {
563 *count = ARRAY_SIZE(v3d_performance_counters);
564 }
565
566 #endif /* USE_V3D_SIMULATOR */
567