Searched defs:vs2 (Results 1 – 3 of 3) sorted by relevance
| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64.cc | 1892 void Riscv64Assembler::VLoxei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxei8()
1899 void Riscv64Assembler::VLoxei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxei16()
1906 void Riscv64Assembler::VLoxei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxei32()
1913 void Riscv64Assembler::VLoxei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLoxei64()
1920 void Riscv64Assembler::VLuxei8(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxei8()
1927 void Riscv64Assembler::VLuxei16(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxei16()
1934 void Riscv64Assembler::VLuxei32(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxei32()
1941 void Riscv64Assembler::VLuxei64(VRegister vd, XRegister rs1, VRegister vs2, VM vm) { in VLuxei64()
1948 void Riscv64Assembler::VSoxei8(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxei8()
1954 void Riscv64Assembler::VSoxei16(VRegister vs3, XRegister rs1, VRegister vs2, VM vm) { in VSoxei16()
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| D | assembler_riscv64_test.cc | 1948 return [](VRegister vd, VRegister vs2, Reg3, Riscv64Assembler::VM vm) { in VXVVmSkipV0VmAndNoR1R2Overlap()
1954 return [](VRegister vd, VRegister vs2, VRegister vs1, Riscv64Assembler::VM vm) { in VXVVmSkipV0VmAndNoR1R2R3Overlap()
1960 return [](VRegister vd, VRegister vs2, Riscv64Assembler::VM vm) { in VVVmSkipV0VmAndNoR1R2Overlap()
1985 return [](VRegister vd, VRegister vs2, VRegister vs1) { return vd != vs1 && vd != vs2; }; in VVVNoR1R2R3Overlap()
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| /art/test/123-compiler-regressions-mt/src/ |
| D | Main.java | 72 int[] vs2 = values; in thread2() local
112 int[] vs2 = values; in thread2() local
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