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/external/eigen/blas/testing/
Ddblat1.f6 * http://www.netlib.org/lapack/explore-html/
40 * -- Reference BLAS test routine (version 3.4.1) --
41 * -- Reference BLAS is a software package provided by Univ. of Tennessee, --
42 * -- Univ. of California Berkeley, Univ. of Colorado Denver and NAG Ltd..--
61 DATA SFAC/9.765625D-4/
87 * -- Print
93 99998 FORMAT (' ----- PASS -----')
146 DATA DA1/0.3D0, 0.4D0, -0.3D0, -0.4D0, -0.3D0, 0.0D0,
147 + 0.0D0, 1.0D0/
148 DATA DB1/0.4D0, 0.3D0, 0.4D0, 0.3D0, -0.4D0, 0.0D0,
[all …]
Dzblat1.f6 * http://www.netlib.org/lapack/explore-html/
40 * -- Reference BLAS test routine (version 3.4.1) --
41 * -- Reference BLAS is a software package provided by Univ. of Tennessee, --
42 * -- Univ. of California Berkeley, Univ. of Colorado Denver and NAG Ltd..--
61 DATA SFAC/9.765625D-4/
82 * -- Print
88 99998 FORMAT (' ----- PASS -----')
147 DATA SA, CA/0.3D0, (0.4D0,-0.7D0)/
148 DATA ((CV(I,J,1),I=1,8),J=1,5)/(0.1D0,0.1D0),
149 + (1.0D0,2.0D0), (1.0D0,2.0D0), (1.0D0,2.0D0),
[all …]
/external/cblas/testing/
Dc_zblat1.f19 DATA SFAC/9.765625D-4/
40 * -- Print
46 99998 FORMAT (' ----- PASS -----')
105 DATA SA, CA/0.3D0, (0.4D0,-0.7D0)/
106 DATA ((CV(I,J,1),I=1,8),J=1,5)/(0.1D0,0.1D0),
107 + (1.0D0,2.0D0), (1.0D0,2.0D0), (1.0D0,2.0D0),
108 + (1.0D0,2.0D0), (1.0D0,2.0D0), (1.0D0,2.0D0),
109 + (1.0D0,2.0D0), (0.3D0,-0.4D0), (3.0D0,4.0D0),
110 + (3.0D0,4.0D0), (3.0D0,4.0D0), (3.0D0,4.0D0),
111 + (3.0D0,4.0D0), (3.0D0,4.0D0), (3.0D0,4.0D0),
[all …]
Dc_dblat1.f19 DATA SFAC/9.765625D-4/
46 * -- Print
52 99998 FORMAT (' ----- PASS -----')
102 DATA DA1/0.3D0, 0.4D0, -0.3D0, -0.4D0, -0.3D0, 0.0D0,
103 + 0.0D0, 1.0D0/
104 DATA DB1/0.4D0, 0.3D0, 0.4D0, 0.3D0, -0.4D0, 0.0D0,
105 + 1.0D0, 0.0D0/
106 DATA DC1/0.6D0, 0.8D0, -0.6D0, 0.8D0, 0.6D0, 1.0D0,
107 + 0.0D0, 1.0D0/
108 DATA DS1/0.8D0, 0.6D0, 0.8D0, -0.6D0, 0.8D0, 0.0D0,
[all …]
/external/llvm/test/MC/ARM/
Dneon-vld-vst-align.s1 @ RUN: not llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s > %t 2> %t.err
3 @ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t.err %s
5 vld1.8 {d0}, [r4]
6 vld1.8 {d0}, [r4:16]
7 vld1.8 {d0}, [r4:32]
8 vld1.8 {d0}, [r4:64]
9 vld1.8 {d0}, [r4:128]
10 vld1.8 {d0}, [r4:256]
12 @ CHECK: vld1.8 {d0}, [r4] @ encoding: [0x24,0xf9,0x0f,0x07]
13 @ CHECK-ERRORS: error: alignment must be 64 or omitted
[all …]
Ddirective-arch_extension-fp.s1 @ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \
2 @ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK
3 @ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \
4 @ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK
5 @ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \
6 @ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK
7 @ RUN: not llvm-mc -triple thumbv8-eabi -filetype asm -o /dev/null 2>&1 %s \
8 @ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK
13 @ CHECK-V7: error: architectural extension 'fp' is not allowed for the current base architecture
14 @ CHECK-V7-NEXT: .arch_extension fp
[all …]
Ddirective-arch_extension-simd.s1 @ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \
2 @ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK
3 @ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \
4 @ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK
5 @ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \
6 @ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK
7 @ RUN: not llvm-mc -triple thumbv8-eabi -filetype asm -o /dev/null 2>&1 %s \
8 @ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK
13 @ CHECK-V7: error: architectural extension 'simd' is not allowed for the current base architecture
14 @ CHECK-V7-NEXT: .arch_extension simd
[all …]
Dvfp-aliases.s1 @ RUN: llvm-mc -triple armv7-eabi -filetype asm -o - %s | FileCheck %s
8 fstmfdd sp!, {d0}
9 fstmead sp!, {d0}
10 fstmdbd sp!, {d0}
11 fstmiad sp!, {d0}
21 fldmiad sp!, {d0}
22 fldmdbd sp!, {d0}
23 fldmead sp!, {d0}
24 fldmfdd sp!, {d0}
26 fstmeax sp!, {d0}
[all …]
Dfullfp16-neon-neg.s1 @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16,+neon -show-encoding < %s 2>&1 | FileC…
2 @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,-neon -show-encoding < %s 2>&1 | FileC…
3 @ RUN: not llvm-mc -triple thumbv8a-none-eabi -mattr=-fullfp16,+neon -show-encoding < %s 2>&1 | Fil…
4 @ RUN: not llvm-mc -triple thumbv8a-none-eabi -mattr=+fullfp16,-neon -show-encoding < %s 2>&1 | Fil…
6 vadd.f16 d0, d1, d2
11 vsub.f16 d0, d1, d2
16 vmul.f16 d0, d1, d2
26 vmla.f16 d0, d1, d2
36 vmls.f16 d0, d1, d2
46 vfma.f16 d0, d1, d2
[all …]
Dfullfp16-neon.s1 @ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,+neon -show-encoding < %s | FileCheck %s -…
2 @ RUN: llvm-mc -triple thumbv8a-none-eabi -mattr=+fullfp16,+neon -show-encoding < %s | FileCheck %s…
4 vadd.f16 d0, d1, d2
6 @ ARM: vadd.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x11,0xf2]
8 @ THUMB: vadd.f16 d0, d1, d2 @ encoding: [0x11,0xef,0x02,0x0d]
11 vsub.f16 d0, d1, d2
13 @ ARM: vsub.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x31,0xf2]
15 @ THUMB: vsub.f16 d0, d1, d2 @ encoding: [0x31,0xef,0x02,0x0d]
18 vmul.f16 d0, d1, d2
20 @ ARM: vmul.f16 d0, d1, d2 @ encoding: [0x12,0x0d,0x11,0xf3]
[all …]
/external/neon_2_sse/
DNEON_2_SSE.h3 //*** Copyright (C) 2012-2018 Intel Corporation. All rights reserved.
32 // This file is intended to simplify ARM->IA32 porting
36 //performance overhead and the necessity to use the EMMS instruction (_mm_empty())for mmx-x87 float…
40 //!!!!!!!!!!!!!! but please pay attention at #define USE_SSE4 below - you might need to define it …
47 …tions use SSE4 instructions instead of earlier SSE versions, when undefined - SIMD up to SSSE3 are…
48 //For older devices without SSE4 support it should be undefined, for newer devices - defined, prob…
175 # define SINT_MIN (-2147483647 - 1) /* min signed int value */
208 //Unfortunately we are unable to merge two 64-bits in on 128 bit register because user should be ab…
444 //Vector add: vadd -> Vr[i]:=Va[i]+Vb[i], Vr, Va, Vb have equal lane sizes.
445 _NEON2SSESTORAGE int8x8_t vadd_s8(int8x8_t a, int8x8_t b); // VADD.I8 d0,d0,d0
[all …]
/external/libdav1d/src/arm/32/
Dipred.S51 .word 640f - L(ipred_dc_128_tbl) + CONFIG_THUMB
52 .word 320f - L(ipred_dc_128_tbl) + CONFIG_THUMB
53 .word 16f - L(ipred_dc_128_tbl) + CONFIG_THUMB
54 .word 8f - L(ipred_dc_128_tbl) + CONFIG_THUMB
55 .word 4f - L(ipred_dc_128_tbl) + CONFIG_THUMB
57 vst1.32 {d0[0]}, [r0, :32], r1
58 vst1.32 {d0[0]}, [r12, :32], r1
60 vst1.32 {d0[0]}, [r0, :32], r1
61 vst1.32 {d0[0]}, [r12, :32], r1
65 vst1.8 {d0}, [r0, :64], r1
[all …]
Dipred16.S54 .word 640f - L(ipred_dc_128_tbl) + CONFIG_THUMB
55 .word 320f - L(ipred_dc_128_tbl) + CONFIG_THUMB
56 .word 160f - L(ipred_dc_128_tbl) + CONFIG_THUMB
57 .word 8f - L(ipred_dc_128_tbl) + CONFIG_THUMB
58 .word 4f - L(ipred_dc_128_tbl) + CONFIG_THUMB
60 vst1.16 {d0}, [r0, :64], r1
61 vst1.16 {d0}, [r12, :64], r1
63 vst1.16 {d0}, [r0, :64], r1
64 vst1.16 {d0}, [r12, :64], r1
68 vst1.16 {d0, d1}, [r0, :128], r1
[all …]
/external/libaom/av1/common/x86/
Dintra_edge_sse4.c34 // Extend the first and last samples to simplify the loop for the 5-tap case in av1_filter_intra_edge_sse4_1()
35 p[-1] = p[0]; in av1_filter_intra_edge_sse4_1()
36 __m128i last = _mm_set1_epi8((char)p[sz - 1]); in av1_filter_intra_edge_sse4_1()
40 uint8_t *in = (strength == 3) ? p - 1 : p; in av1_filter_intra_edge_sse4_1()
44 int len = sz - 1; in av1_filter_intra_edge_sse4_1()
49 __m128i coef0 = _mm_lddqu_si128((__m128i const *)kern[strength - 1]); in av1_filter_intra_edge_sse4_1()
56 __m128i d0 = _mm_shuffle_epi8(in0, shuf0); in av1_filter_intra_edge_sse4_1() local
58 d0 = _mm_maddubs_epi16(d0, coef0); in av1_filter_intra_edge_sse4_1()
60 d0 = _mm_hadd_epi16(d0, d1); in av1_filter_intra_edge_sse4_1()
62 d0 = _mm_add_epi16(d0, eight); in av1_filter_intra_edge_sse4_1()
[all …]
/external/libavc/common/arm/
Dih264_inter_pred_luma_horz_hpel_vert_qpel_a9q.s9 @ * http://www.apache.org/licenses/LICENSE-2.0
33 @* - ih264_inter_pred_luma_horz_hpel_vert_qpel_a9q()
122 stmfd sp!, {r4-r12, r14} @ store register values to stack
123 vstmdb sp!, {d8-d15} @push neon registers to stack
125 sub r0, r0, r2, lsl #1 @ pu1_src-2*src_strd
126 sub r0, r0, #2 @ pu1_src-2
151 vld1.32 {q0}, [r0], r2 @ row -2 load for horizontal filter
152 vext.8 d5, d0, d1, #5
153 vaddl.u8 q3, d0, d5
155 vext.8 d2, d0, d1, #2
[all …]
/external/renderscript-intrinsics-replacement-toolkit/renderscript-toolkit/src/main/cpp/
DColorMatrix_neon.S8 * http://www.apache.org/licenses/LICENSE-2.0
23 .word x##_end-x
27 vpush {q4-q7}
43 vpush {q4-q7}
70 #vmul.f32 q0,q0,d0[0]
71 #vmla.f32 q0,q0,d0[0]
75 vpop {q4-q7}
81 vld4.8 {d0[0],d1[0],d2[0],d3[0]}, [r1]!
82 vld4.8 {d0[1],d1[1],d2[1],d3[1]}, [r1]!
83 vld4.8 {d0[2],d1[2],d2[2],d3[2]}, [r1]!
[all …]
/external/sdv/vsomeip/third_party/boost/proto/test/
Ddeduce_domain.cpp8 // Avoid a compile-time check inside the deduce_domain code.
19 struct D0 : proto::domain<> struct
23 struct D1 : proto::domain<proto::default_generator, _, D0>
27 struct D2 : proto::domain<proto::default_generator, _, D0>
60 BOOST_MPL_ASSERT((is_same<proto::detail::common_domain3<D0, D0, D0>::type, D0>)); in test1()
61 …OOST_MPL_ASSERT((is_same<proto::detail::common_domain3<proto::default_domain, D0, D0>::type, D0>)); in test1()
62 …BOOST_MPL_ASSERT((is_same<proto::detail::common_domain3<D0, proto::default_domain, D0>::type, D0>)… in test1()
63 …BOOST_MPL_ASSERT((is_same<proto::detail::common_domain3<D0, D0, proto::default_domain>::type, D0>)… in test1()
64 …_ASSERT((is_same<proto::detail::common_domain3<D0, proto::default_domain, proto::default_domain>::… in test1()
65 …_same<proto::detail::common_domain3<proto::default_domain, D0, proto::default_domain>::type, D0>)); in test1()
[all …]
/external/libvpx/vpx_dsp/arm/
Dhighbd_intrapred_neon.c4 * Use of this source code is governed by a BSD-style license
18 //------------------------------------------------------------------------------
68 const uint16x4_t dc = vdup_n_u16(1 << (bd - 1)); in vpx_highbd_dc_128_predictor_4x4_neon()
74 //------------------------------------------------------------------------------
125 const uint16x8_t dc = vdupq_n_u16(1 << (bd - 1)); in vpx_highbd_dc_128_predictor_8x8_neon()
131 //------------------------------------------------------------------------------
189 const uint16x8_t dc = vdupq_n_u16(1 << (bd - 1)); in vpx_highbd_dc_128_predictor_16x16_neon()
195 //------------------------------------------------------------------------------
268 const uint16x8_t dc = vdupq_n_u16(1 << (bd - 1)); in vpx_highbd_dc_128_predictor_32x32_neon()
274 // -----------------------------------------------------------------------------
[all …]
/external/XNNPACK/src/qc8-gemm/gen/
D1x8-minmax-fp32-aarch32-neonv8-mlal-lane-cortex-a35.S1 // Auto-generated file. Do not edit!
2 // Template: src/qs8-gemm/1x8-aarch32-neon-mlal-lane-cortex-a7.S.in
7 // This source code is licensed under the BSD-style license found in the
18 // size_t kc, (r2) -> r5
20 // size_t a_stride, sp + 96 -> (unused)
21 // const void*restrict w, sp + 100 -> r9
22 // int8_t*restrict c, sp + 104 -> r11
23 // size_t cm_stride, sp + 108 -> (unused)
24 // size_t cn_stride, sp + 112 -> r7
25 // xnn_qs8_minmax_params params) sp + 116 -> (r5)
[all …]
D1x8-minmax-fp32-aarch32-neon-mlal-lane-prfm-cortex-a7.S1 // Auto-generated file. Do not edit!
2 // Template: src/qs8-gemm/1x8-aarch32-neon-mlal-lane-cortex-a7.S.in
7 // This source code is licensed under the BSD-style license found in the
18 // size_t kc, (r2) -> r5
20 // size_t a_stride, sp + 96 -> (unused)
21 // const void*restrict w, sp + 100 -> r9
22 // int8_t*restrict c, sp + 104 -> r11
23 // size_t cm_stride, sp + 108 -> (unused)
24 // size_t cn_stride, sp + 112 -> r7
25 // xnn_qs8_minmax_params params) sp + 116 -> (r5)
[all …]
D1x8-minmax-fp32-aarch32-neonv8-mlal-lane-prfm-cortex-a35.S1 // Auto-generated file. Do not edit!
2 // Template: src/qs8-gemm/1x8-aarch32-neon-mlal-lane-cortex-a7.S.in
7 // This source code is licensed under the BSD-style license found in the
18 // size_t kc, (r2) -> r5
20 // size_t a_stride, sp + 96 -> (unused)
21 // const void*restrict w, sp + 100 -> r9
22 // int8_t*restrict c, sp + 104 -> r11
23 // size_t cm_stride, sp + 108 -> (unused)
24 // size_t cn_stride, sp + 112 -> r7
25 // xnn_qs8_minmax_params params) sp + 116 -> (r5)
[all …]
D1x8-minmax-fp32-aarch32-neon-mlal-lane-cortex-a7.S1 // Auto-generated file. Do not edit!
2 // Template: src/qs8-gemm/1x8-aarch32-neon-mlal-lane-cortex-a7.S.in
7 // This source code is licensed under the BSD-style license found in the
18 // size_t kc, (r2) -> r5
20 // size_t a_stride, sp + 96 -> (unused)
21 // const void*restrict w, sp + 100 -> r9
22 // int8_t*restrict c, sp + 104 -> r11
23 // size_t cm_stride, sp + 108 -> (unused)
24 // size_t cn_stride, sp + 112 -> r7
25 // xnn_qs8_minmax_params params) sp + 116 -> (r5)
[all …]
/external/XNNPACK/src/qu8-gemm/gen/
D1x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a7.S1 // Auto-generated file. Do not edit!
2 // Template: src/qs8-gemm/1x8-aarch32-neon-mlal-lane-cortex-a7.S.in
7 // This source code is licensed under the BSD-style license found in the
18 // size_t kc, (r2) -> r5
20 // size_t a_stride, sp + 96 -> (unused)
21 // const void*restrict w, sp + 100 -> r9
22 // uint8_t*restrict c, sp + 104 -> r11
23 // size_t cm_stride, sp + 108 -> (unused)
24 // size_t cn_stride, sp + 112 -> r7
25 // xnn_qs8_conv_minmax_params params) sp + 116 -> (r5)
[all …]
/external/XNNPACK/src/qs8-gemm/gen/
D1x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a7.S1 // Auto-generated file. Do not edit!
2 // Template: src/qs8-gemm/1x8-aarch32-neon-mlal-lane-cortex-a7.S.in
7 // This source code is licensed under the BSD-style license found in the
18 // size_t kc, (r2) -> r5
20 // size_t a_stride, sp + 96 -> (unused)
21 // const void*restrict w, sp + 100 -> r9
22 // int8_t*restrict c, sp + 104 -> r11
23 // size_t cm_stride, sp + 108 -> (unused)
24 // size_t cn_stride, sp + 112 -> r7
25 // xnn_qs8_conv_minmax_params params) sp + 116 -> (r5)
[all …]
D1x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a7.S1 // Auto-generated file. Do not edit!
2 // Template: src/qs8-gemm/1x8-aarch32-neon-mlal-lane-cortex-a7.S.in
7 // This source code is licensed under the BSD-style license found in the
18 // size_t kc, (r2) -> r5
20 // size_t a_stride, sp + 96 -> (unused)
21 // const void*restrict w, sp + 100 -> r9
22 // int8_t*restrict c, sp + 104 -> r11
23 // size_t cm_stride, sp + 108 -> (unused)
24 // size_t cn_stride, sp + 112 -> r7
25 // xnn_qs8_conv_minmax_params params) sp + 116 -> (r5)
[all …]

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