Home
last modified time | relevance | path

Searched +full:64 +full:- +full:bit (Results 1 – 25 of 1238) sorted by relevance

12345678910>>...50

/external/clang/lib/Headers/
Dmmintrin.h1 /*===---- mmintrin.h - MMX intrinsics --------------------------------------===
21 *===-----------------------------------------------------------------------===
50 /// \brief Constructs a 64-bit integer vector, setting the lower 32 bits to the
51 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
58 /// A 32-bit integer value.
59 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
67 /// \brief Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
75 /// A 64-bit integer vector.
76 /// \returns A 32-bit signed integer value containing the lower 32 bits of the
84 /// \brief Casts a 64-bit signed integer value into a 64-bit integer vector.
[all …]
Dtmmintrin.h1 /*===---- tmmintrin.h - SSSE3 intrinsics -----------------------------------===
21 *===-----------------------------------------------------------------------===
32 /// \brief Computes the absolute value of each of the packed 8-bit signed
33 /// integers in the source operand and stores the 8-bit unsigned integer
41 /// A 64-bit vector of [8 x i8].
42 /// \returns A 64-bit integer vector containing the absolute values of the
50 /// \brief Computes the absolute value of each of the packed 8-bit signed
51 /// integers in the source operand and stores the 8-bit unsigned integer
59 /// A 128-bit vector of [16 x i8].
60 /// \returns A 128-bit integer vector containing the absolute values of the
[all …]
Dbmiintrin.h1 /*===---- bmiintrin.h - BMI intrinsics -------------------------------------===
21 *===-----------------------------------------------------------------------===
42 /// An unsigned 16-bit integer whose trailing zeros are to be counted.
43 /// \returns An unsigned 16-bit integer containing the number of trailing zero
67 /// \brief Clears all bits in the source except for the least significant bit
84 /// \brief Creates a mask whose bits are set to 1, using bit 0 up to and
85 /// including the least siginificant bit that is set to 1 in the source
101 /// \brief Clears the least siginificant bit that is set to 1 in the source
129 /// An unsigned 32-bit integer whose trailing zeros are to be counted.
130 /// \returns An unsigned 32-bit integer containing the number of trailing zero
[all …]
Dxmmintrin.h1 /*===---- xmmintrin.h - SSE intrinsics -------------------------------------===
21 *===-----------------------------------------------------------------------===
45 /// \brief Adds the 32-bit float values in the low-order bits of the operands.
52 /// A 128-bit vector of [4 x float] containing one of the source operands.
55 /// A 128-bit vector of [4 x float] containing one of the source operands.
57 /// \returns A 128-bit vector of [4 x float] whose lower 32 bits contain the sum
67 /// \brief Adds two 128-bit vectors of [4 x float], and returns the results of
75 /// A 128-bit vector of [4 x float] containing one of the source operands.
77 /// A 128-bit vector of [4 x float] containing one of the source operands.
78 /// \returns A 128-bit vector of [4 x float] containing the sums of both
[all …]
/external/swiftshader/tests/regres/testlists/vk-default/
Dmesh-shader.txt1 dEQP-VK.mesh_shader.nv.smoke.mesh_shader_triangle
2 dEQP-VK.mesh_shader.nv.smoke.mesh_task_shader_triangle
3 dEQP-VK.mesh_shader.nv.smoke.task_only_shader_triangle
4 dEQP-VK.mesh_shader.nv.smoke.fullscreen_gradient
5 dEQP-VK.mesh_shader.nv.smoke.fullscreen_gradient_fs2x2
6 dEQP-VK.mesh_shader.nv.smoke.fullscreen_gradient_fs2x1
7 dEQP-VK.mesh_shader.nv.api.draw.draw_count_0.no_indirect_args.no_count_limit.no_count_offset.no_tas…
8 dEQP-VK.mesh_shader.nv.api.draw.draw_count_0.no_indirect_args.no_count_limit.no_count_offset.no_tas…
9 dEQP-VK.mesh_shader.nv.api.draw.draw_count_0.no_indirect_args.no_count_limit.no_count_offset.with_t…
10 dEQP-VK.mesh_shader.nv.api.draw.draw_count_0.no_indirect_args.no_count_limit.no_count_offset.with_t…
[all …]
/external/deqp/external/vulkancts/mustpass/main/vk-default/
Dmesh-shader.txt1 dEQP-VK.mesh_shader.ext.api.draw.draw_count_0.no_indirect_args.no_count_limit.no_count_offset.no_ta…
2 dEQP-VK.mesh_shader.ext.api.draw.draw_count_0.no_indirect_args.no_count_limit.no_count_offset.no_ta…
3 dEQP-VK.mesh_shader.ext.api.draw.draw_count_0.no_indirect_args.no_count_limit.no_count_offset.with_…
4 dEQP-VK.mesh_shader.ext.api.draw.draw_count_0.no_indirect_args.no_count_limit.no_count_offset.with_…
5 dEQP-VK.mesh_shader.ext.api.draw.draw_count_1.no_indirect_args.no_count_limit.no_count_offset.no_ta…
6 dEQP-VK.mesh_shader.ext.api.draw.draw_count_1.no_indirect_args.no_count_limit.no_count_offset.no_ta…
7 dEQP-VK.mesh_shader.ext.api.draw.draw_count_1.no_indirect_args.no_count_limit.no_count_offset.with_…
8 dEQP-VK.mesh_shader.ext.api.draw.draw_count_1.no_indirect_args.no_count_limit.no_count_offset.with_…
9 dEQP-VK.mesh_shader.ext.api.draw.draw_count_2.no_indirect_args.no_count_limit.no_count_offset.no_ta…
10 dEQP-VK.mesh_shader.ext.api.draw.draw_count_2.no_indirect_args.no_count_limit.no_count_offset.no_ta…
[all …]
/external/deqp/android/cts/main/vk-main-2023-03-01/
Dmesh-shader.txt1 dEQP-VK.mesh_shader.ext.api.draw.draw_count_0.no_indirect_args.no_count_limit.no_count_offset.no_ta…
2 dEQP-VK.mesh_shader.ext.api.draw.draw_count_0.no_indirect_args.no_count_limit.no_count_offset.no_ta…
3 dEQP-VK.mesh_shader.ext.api.draw.draw_count_0.no_indirect_args.no_count_limit.no_count_offset.with_…
4 dEQP-VK.mesh_shader.ext.api.draw.draw_count_0.no_indirect_args.no_count_limit.no_count_offset.with_…
5 dEQP-VK.mesh_shader.ext.api.draw.draw_count_1.no_indirect_args.no_count_limit.no_count_offset.no_ta…
6 dEQP-VK.mesh_shader.ext.api.draw.draw_count_1.no_indirect_args.no_count_limit.no_count_offset.no_ta…
7 dEQP-VK.mesh_shader.ext.api.draw.draw_count_1.no_indirect_args.no_count_limit.no_count_offset.with_…
8 dEQP-VK.mesh_shader.ext.api.draw.draw_count_1.no_indirect_args.no_count_limit.no_count_offset.with_…
9 dEQP-VK.mesh_shader.ext.api.draw.draw_count_2.no_indirect_args.no_count_limit.no_count_offset.no_ta…
10 dEQP-VK.mesh_shader.ext.api.draw.draw_count_2.no_indirect_args.no_count_limit.no_count_offset.no_ta…
[all …]
/external/mbedtls/tests/suites/
Dtest_suite_alignment.data1 Aligned 16-bit access
4 Aligned 32-bit access
7 Aligned 64-bit access
8 mbedtls_unaligned_access:64:0
10 Unaligned 16-bit access offset=1
13 Unaligned 32-bit access offset=1
16 Unaligned 64-bit access offset=1
17 mbedtls_unaligned_access:64:1
19 Unaligned 16-bit access offset=4
22 Unaligned 32-bit access offset=4
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVSchedule.td1 //===-- RISCVSchedule.td - RISCV Scheduling Definitions -------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShift32 : SchedWrite; // 32-bit shift operations on RV64Ix
13 def WriteShift : SchedWrite; // 32 or 64-bit shift operations
14 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
15 def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
16 def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
[all …]
/external/virglrenderer/.gitlab-ci/expectations/host/
Dvirgl-gles-skips.txt11 spec@ext_texture_integer@fbo-integer
14 spec@arb_direct_state_access@gettextureimage-formats
16 spec@nv_primitive_restart@primitive-restart-draw-mode-polygon
17 spec@nv_primitive_restart@primitive-restart-draw-mode-quad_strip
18 spec@nv_primitive_restart@primitive-restart-draw-mode-quads
19 spec@ext_framebuffer_multisample@clip-and-scissor-blit.*
22 spec@glsl-4.*@*dmat*
23 spec@glsl-4.*@*dvec*
24 spec@glsl-4.*@*double*
25 spec@arb_enhanced_layouts@execution@component-layout@vs-gs-fs-double
[all …]
/external/virglrenderer/.gitlab-ci/expectations/virt/
Dvirgl-gles-skips.txt11 spec@ext_texture_integer@fbo-integer
14 spec@arb_direct_state_access@gettextureimage-formats
16 spec@nv_primitive_restart@primitive-restart-draw-mode-polygon
17 spec@nv_primitive_restart@primitive-restart-draw-mode-quad_strip
18 spec@nv_primitive_restart@primitive-restart-draw-mode-quads
19 spec@ext_framebuffer_multisample@clip-and-scissor-blit.*
22 spec@arb_shader_image_load_store@max-size
23 spec@glsl-1.50@execution@interface-blocks-api-access-members
25 # Skip slow tests on crosvm/virglrenderer (90-250 s)
26 spec@glsl-1.30@execution@interpolation@interpolation-noperspective-gl_backsecondarycolor-flat-dista…
[all …]
/external/llvm/test/CodeGen/X86/
D3addr-16bit.ll1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -asm-verbose=false | FileCheck %s -check-prefix=64BIT
4 ; In 32-bit the partial register stall would degrade performance.
8 ; 32BIT-LABEL: t1:
9 ; 32BIT: movw 20(%esp), %ax
10 ; 32BIT-NOT: movw %ax, %cx
11 ; 32BIT: leal 1(%eax), %ecx
13 ; 64BIT-LABEL: t1:
14 ; 64BIT-NOT: movw %si, %ax
15 ; 64BIT: movl %esi, %eax
30 ; 32BIT-LABEL: t2:
[all …]
/external/llvm/test/MC/Mips/
Dmips-expansions-bad.s1 # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
2 # RUN: FileCheck %s < %t1 --check-prefix=32-BIT
3 # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
4 # RUN: FileCheck %s --check-prefixes=64-BIT,N32-ONLY
5 # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
6 # RUN: FileCheck %s --check-prefixes=64-BIT,N64-ONLY
10 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
12 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
14 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
17 # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
[all …]
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/
DRISCVSchedule.td1 //===-- RISCVSchedule.td - RISCV Scheduling Definitions ----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
13 def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
14 def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
15 def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
16 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
[all …]
/external/oboe/samples/RhythmGame/third_party/glm/gtc/
Dtype_precision.hpp11 /// @brief Defines specific C++-based precision types.
14 /// extension defines types based on explicitly-sized C++ data types.
48 /// Low precision 8 bit signed integer type.
52 /// Low precision 16 bit signed integer type.
56 /// Low precision 32 bit signed integer type.
60 /// Low precision 64 bit signed integer type.
64 /// Low precision 8 bit signed integer type.
68 /// Low precision 16 bit signed integer type.
72 /// Low precision 32 bit signed integer type.
76 /// Low precision 64 bit signed integer type.
[all …]
/external/capstone/
DMathExtras.h1 //===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===//
8 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
15 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
36 /// Hi_32 - This function returns the high 32 bits of a 64 bit value.
41 /// Lo_32 - This function returns the low 32 bits of a 64 bit value.
46 /// isUIntN - Checks if an unsigned integer fits into the given (dynamic)
47 /// bit width.
49 return x == (x & (~0ULL >> (64 - N))); in isUIntN()
52 /// isIntN - Checks if an signed integer fits into the given (dynamic)
[all …]
/external/aws-sdk-java-v2/test/sdk-benchmarks/src/main/resources/software/amazon/awssdk/benchmark/
Dbaseline.json3 "id": "apicall.httpclient.async.NettyClientH1NonTlsBenchmark.concurrentApiCall-Throughput",
7 "jvmName": "OpenJDK 64-Bit Server VM",
8 "jvmVersion": "25.222-b10",
10 "date": "2020-03-18T20:11:42.308-07:00[America/Los_Angeles]"
23 "id": "apicall.httpclient.async.NettyClientH1NonTlsBenchmark.sequentialApiCall-Throughput",
27 "jvmName": "OpenJDK 64-Bit Server VM",
28 "jvmVersion": "25.222-b10",
30 "date": "2020-03-18T20:11:42.314-07:00[America/Los_Angeles]"
43 …all.httpclient.async.NettyHttpClientH1Benchmark.concurrentApiCall-Throughput-sslProviderValue-jdk",
47 "jvmName": "OpenJDK 64-Bit Server VM",
[all …]
/external/arm-trusted-firmware/drivers/arm/gic/v3/
Dgic600ae_fmu_helpers.c4 * SPDX-License-Identifier: BSD-3-Clause
18 /* Macro to write 32-bit FMU registers */
30 /* Macro to write 64-bit FMU registers */
39 * APB bus is 32-bit wide; so split the 64-bit write into \
40 * two 32-bit writes \
42 mmio_write_32((base) + reg##_LO + (n * 64), (val)); \
43 mmio_write_32((base) + reg##_HI + (n * 64), (val)); \
54 status = (gic_fmu_read_status(base) & BIT(0)); in wait_until_fmu_is_idle()
56 if (timeout_count-- == 0U) { in wait_until_fmu_is_idle()
97 * APB bus is 32-bit wide; so split the 64-bit read into in gic_fmu_read_errfr()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64GenRegisterBankInfo.def1 //===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
21 {0, 64, AArch64::FPRRegBank},
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
[all …]
/external/oboe/samples/RhythmGame/third_party/glm/gtx/
Dtype_aligned.hpp33 /// Low precision 8 bit signed integer aligned scalar type.
37 /// Low precision 16 bit signed integer aligned scalar type.
41 /// Low precision 32 bit signed integer aligned scalar type.
45 /// Low precision 64 bit signed integer aligned scalar type.
50 /// Low precision 8 bit signed integer aligned scalar type.
54 /// Low precision 16 bit signed integer aligned scalar type.
58 /// Low precision 32 bit signed integer aligned scalar type.
62 /// Low precision 64 bit signed integer aligned scalar type.
67 /// Low precision 8 bit signed integer aligned scalar type.
71 /// Low precision 16 bit signed integer aligned scalar type.
[all …]
/external/oboe/samples/RhythmGame/third_party/glm/
Dfwd.hpp17 /// Quaternion of low single-precision floating-point numbers.
22 /// Quaternion of medium single-precision floating-point numbers.
27 /// Quaternion of high single-precision floating-point numbers.
39 /// Quaternion of default single-precision floating-point numbers.
43 /// Quaternion of low single-precision floating-point numbers.
48 /// Quaternion of medium single-precision floating-point numbers.
53 /// Quaternion of high single-precision floating-point numbers.
58 /// Quaternion of default single-precision floating-point numbers.
64 /// Quaternion of low double-precision floating-point numbers.
69 /// Quaternion of medium double-precision floating-point numbers.
[all …]
/external/pdfium/third_party/libtiff/
Dtiffconf.h62 /* Signed 8-bit type */
65 /* Unsigned 8-bit type */
68 /* Signed 16-bit type */
71 /* Unsigned 16-bit type */
74 /* Signed 32-bit type */
77 /* Unsigned 32-bit type */
80 /* Signed 32-bit type formatter */
83 /* Unsigned 32-bit type formatter */
88 /* Signed 64-bit type formatter */
91 /* Unsigned 64-bit type formatter */
[all …]
/external/llvm/test/MC/X86/
Dx86_errors.s1 // RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t.err
2 // RUN: FileCheck --check-prefix=64 < %t.err %s
4 // RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t.err
5 // RUN: FileCheck --check-prefix=32 < %t.err %s
8 // 64: error: ambiguous instructions require an explicit suffix (could be 'cmpb', 'cmpw', 'cmpl', o…
11 // 32: error: register %rax is only available in 64-bit mode
14 // 32: error: register %xmm16 is only available in 64-bit mode
15 // 64: error: register %xmm16 is only available with AVX512
25 // 32: error: instruction requires: 64-bit mode
29 // 64: error: expected scale expression
[all …]
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
DAArch64GenRegisterBankInfo.def1 //===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
21 {0, 64, AArch64::FPRRegBank},
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
[all …]
/external/libvpx/vp9/encoder/x86/
Dvp9_error_avx2.c4 * Use of this source code is governed by a BSD-style license
34 // dqcoeff - coeff in vp9_block_error_avx2()
36 // madd (dqcoeff - coeff) in vp9_block_error_avx2()
40 // Save the higher 64 bit of each 128 bit lane. in vp9_block_error_avx2()
43 // Add the higher 64 bit to the low 64 bit. in vp9_block_error_avx2()
46 // Expand each double word in the lower 64 bits to quad word. in vp9_block_error_avx2()
62 // dqcoeff - coeff in vp9_block_error_avx2()
65 // madd (dqcoeff - coeff) in vp9_block_error_avx2()
71 // Add the first madd (dqcoeff - coeff) with the second. in vp9_block_error_avx2()
75 // Expand each double word of madd (dqcoeff - coeff) to quad word. in vp9_block_error_avx2()
[all …]

12345678910>>...50