Searched full:bit (Results 1 – 25 of 17894) sorted by relevance
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27 #define CCM_CCGR_SETTING0_DOM_CLK_RUN BIT(0)28 #define CCM_CCGR_SETTING0_DOM_CLK_RUN_WAIT BIT(1)29 #define CCM_CCGR_SETTING0_DOM_CLK_ALWAYS (BIT(1) | BIT(0))31 #define CCM_CCGR_SETTING1_DOM_CLK_RUN BIT(4)32 #define CCM_CCGR_SETTING1_DOM_CLK_RUN_WAIT BIT(5)33 #define CCM_CCGR_SETTING1_DOM_CLK_ALWAYS (BIT(5) | BIT(4))35 #define CCM_CCGR_SETTING2_DOM_CLK_RUN BIT(8)36 #define CCM_CCGR_SETTING2_DOM_CLK_RUN_WAIT BIT(9)37 #define CCM_CCGR_SETTING2_DOM_CLK_ALWAYS (BIT(9) | BIT(8))39 #define CCM_CCGR_SETTING3_DOM_CLK_RUN BIT(12)[all …]
238 #define RCC_TZCR_TZEN BIT(0)239 #define RCC_TZCR_MCKPROT BIT(1)242 #define RCC_OCENSETR_HSION BIT(0)243 #define RCC_OCENSETR_HSIKERON BIT(1)244 #define RCC_OCENSETR_CSION BIT(4)245 #define RCC_OCENSETR_CSIKERON BIT(5)246 #define RCC_OCENSETR_DIGBYP BIT(7)247 #define RCC_OCENSETR_HSEON BIT(8)248 #define RCC_OCENSETR_HSEKERON BIT(9)249 #define RCC_OCENSETR_HSEBYP BIT(10)[all …]
26 #define USART_CR1_UE BIT(0)27 #define USART_CR1_UESM BIT(1)28 #define USART_CR1_RE BIT(2)29 #define USART_CR1_TE BIT(3)30 #define USART_CR1_IDLEIE BIT(4)31 #define USART_CR1_RXNEIE BIT(5)32 #define USART_CR1_TCIE BIT(6)33 #define USART_CR1_TXEIE BIT(7)34 #define USART_CR1_PEIE BIT(8)35 #define USART_CR1_PS BIT(9)[all …]
215 #define RCC_SECCFGR_HSISEC BIT(0)216 #define RCC_SECCFGR_CSISEC BIT(1)217 #define RCC_SECCFGR_HSESEC BIT(2)218 #define RCC_SECCFGR_LSISEC BIT(3)219 #define RCC_SECCFGR_LSESEC BIT(4)220 #define RCC_SECCFGR_PLL12SEC BIT(8)221 #define RCC_SECCFGR_PLL3SEC BIT(9)222 #define RCC_SECCFGR_PLL4SEC BIT(10)223 #define RCC_SECCFGR_MPUSEC BIT(11)224 #define RCC_SECCFGR_AXISEC BIT(12)[all …]
731 #define RCC_R0CIDCFGR_CFEN BIT(0)732 #define RCC_R0CIDCFGR_SEM_EN BIT(1)739 #define RCC_R0SEMCR_SEM_MUTEX BIT(0)744 #define RCC_R1CIDCFGR_CFEN BIT(0)745 #define RCC_R1CIDCFGR_SEM_EN BIT(1)752 #define RCC_R1SEMCR_SEM_MUTEX BIT(0)757 #define RCC_R2CIDCFGR_CFEN BIT(0)758 #define RCC_R2CIDCFGR_SEM_EN BIT(1)765 #define RCC_R2SEMCR_SEM_MUTEX BIT(0)770 #define RCC_R3CIDCFGR_CFEN BIT(0)[all …]
15 /* Pin function bit */16 #define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)17 #define GPSR0_DU_EXVSYNC_DU_VSYNC BIT(20)18 #define GPSR0_DU_EXHSYNC_DU_HSYNC BIT(19)19 #define GPSR0_DU_DOTCLKOUT BIT(18)20 #define GPSR0_DU_DB7 BIT(17)21 #define GPSR0_DU_DB6 BIT(16)22 #define GPSR0_DU_DB5 BIT(15)23 #define GPSR0_DU_DB4 BIT(14)24 #define GPSR0_DU_DB3 BIT(13)[all …]
15 /* Pin functon bit */16 #define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)17 #define GPSR0_DU_EXVSYNC_DU_VSYNC BIT(20)18 #define GPSR0_DU_EXHSYNC_DU_HSYNC BIT(19)19 #define GPSR0_DU_DOTCLKOUT BIT(18)20 #define GPSR0_DU_DB7 BIT(17)21 #define GPSR0_DU_DB6 BIT(16)22 #define GPSR0_DU_DB5 BIT(15)23 #define GPSR0_DU_DB4 BIT(14)24 #define GPSR0_DU_DB3 BIT(13)[all …]
12 #define IMX_UART_RXD_CHARRDY BIT(15)13 #define IMX_UART_RXD_ERR BIT(14)14 #define IMX_UART_RXD_OVERRUN BIT(13)15 #define IMX_UART_RXD_FRMERR BIT(12)16 #define IMX_UART_RXD_BRK BIT(11)17 #define IMX_UART_RXD_PRERR BIT(10)22 #define IMX_UART_CR1_ADEN BIT(15)23 #define IMX_UART_CR1_ADBR BIT(14)24 #define IMX_UART_CR1_TRDYEN BIT(13)25 #define IMX_UART_CR1_IDEN BIT(12)[all …]
11 # Aruba - bit 20114 # Antigua and Barbuda - bit 21417 # United Arab Emirates - bit 20820 # Afghanistan - bit 20223 # Algeria - bit 26326 # Azerbaijan - bit 21729 # Albania - bit 20532 # Armenia - bit 21035 # Andorra - bit 20638 # Angola - bit 203[all …]
17 # Aruba - bit 20120 # Antigua and Barbuda - bit 21423 # United Arab Emirates - bit 20826 # Afghanistan - bit 20229 # Algeria - bit 26332 # Azerbaijan - bit 21735 # Albania - bit 20538 # Armenia - bit 21041 # Andorra - bit 20644 # Angola - bit 203[all …]
39 #define MASK_DSM_TRIGGER_A53 BIT(31)40 #define IRQ_SRC_A53_WUP BIT(30)42 #define IRQ_SRC_C1 BIT(29)43 #define IRQ_SRC_C0 BIT(28)44 #define IRQ_SRC_C3 BIT(23)45 #define IRQ_SRC_C2 BIT(22)46 #define CPU_CLOCK_ON_LPM BIT(14)47 #define A53_CLK_ON_LPM BIT(14)48 #define MASTER0_LPM_HSK BIT(6)49 #define MASTER1_LPM_HSK BIT(7)[all …]
1 dEQP-VK.memory_model.shared.16bit.arrays_of_arrays.02 dEQP-VK.memory_model.shared.16bit.arrays_of_arrays.13 dEQP-VK.memory_model.shared.16bit.arrays_of_arrays.24 dEQP-VK.memory_model.shared.16bit.arrays_of_arrays.35 dEQP-VK.memory_model.shared.16bit.arrays_of_arrays.46 dEQP-VK.memory_model.shared.16bit.arrays_of_arrays.57 dEQP-VK.memory_model.shared.16bit.arrays_of_arrays.68 dEQP-VK.memory_model.shared.16bit.arrays_of_arrays.79 dEQP-VK.memory_model.shared.16bit.arrays_of_arrays.810 dEQP-VK.memory_model.shared.16bit.arrays_of_arrays.9[all …]
3 PSA import AES 128-bit not supported7 PSA generate AES 128-bit not supported11 PSA import AES 192-bit not supported15 PSA generate AES 192-bit not supported19 PSA import AES 256-bit not supported23 PSA generate AES 256-bit not supported27 PSA import ARC4 8-bit not supported31 PSA generate ARC4 8-bit not supported35 PSA import ARC4 128-bit not supported39 PSA generate ARC4 128-bit not supported[all …]
37 #define MASK_DSM_TRIGGER_A53 BIT(31)38 #define IRQ_SRC_A53_WUP BIT(30)40 #define IRQ_SRC_C1 BIT(29)41 #define IRQ_SRC_C0 BIT(28)42 #define IRQ_SRC_C3 BIT(23)43 #define IRQ_SRC_C2 BIT(22)44 #define CPU_CLOCK_ON_LPM BIT(14)45 #define A53_CLK_ON_LPM BIT(14)46 #define MASTER0_LPM_HSK BIT(6)47 #define MASTER1_LPM_HSK BIT(7)[all …]
3 PSA AES 128-bit7 PSA AES 192-bit11 PSA AES 256-bit15 PSA ARIA 128-bit19 PSA ARIA 192-bit23 PSA ARIA 256-bit27 PSA CAMELLIA 128-bit31 PSA CAMELLIA 192-bit35 PSA CAMELLIA 256-bit39 PSA CHACHA20 256-bit[all …]
3 PSA import AES 128-bit not supported7 PSA generate AES 128-bit not supported11 PSA import AES 192-bit not supported15 PSA generate AES 192-bit not supported19 PSA import AES 256-bit not supported23 PSA generate AES 256-bit not supported27 PSA import ARIA 128-bit not supported31 PSA generate ARIA 128-bit not supported35 PSA import ARIA 192-bit not supported39 PSA generate ARIA 192-bit not supported[all …]
1 dEQP-VK.ubo.random.16bit.descriptor_indexing.02 dEQP-VK.ubo.random.16bit.descriptor_indexing.13 dEQP-VK.ubo.random.16bit.descriptor_indexing.104 dEQP-VK.ubo.random.16bit.descriptor_indexing.115 dEQP-VK.ubo.random.16bit.descriptor_indexing.126 dEQP-VK.ubo.random.16bit.descriptor_indexing.137 dEQP-VK.ubo.random.16bit.descriptor_indexing.148 dEQP-VK.ubo.random.16bit.descriptor_indexing.159 dEQP-VK.ubo.random.16bit.descriptor_indexing.1610 dEQP-VK.ubo.random.16bit.descriptor_indexing.17[all …]
23 #define DRDU2_U2PLL_LOCK BIT(6U)24 #define DRDU2_U2PLL_RESETB BIT(5U)27 #define DRDU2_U2PLL_SUSPEND_EN BIT(0U)30 #define DRDU2_U2IDDQ BIT(30U)31 #define DRDU2_U2SOFT_RST_N BIT(29U)32 #define DRDU2_U2PHY_ON_FLAG BIT(22U)35 #define DRDU2_U2PHY_RESETB BIT(5U)36 #define DRDU2_U2PHY_ISO BIT(4U)37 #define DRDU2_U2AFE_BG_PWRDWNB BIT(3U)38 #define DRDU2_U2AFE_PLL_PWRDWNB BIT(2U)[all …]