| /external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/ExecutionEngine/JITLink/ |
| D | x86_64.h | 1 //===-- x86_64.h - Generic JITLink x86-64 edge kinds, utilities -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Generic utilities for graphs representing x86-64 objects.
11 //===----------------------------------------------------------------------===//
25 /// Represents x86-64 fixups and other x86-64-specific edge kinds.
28 /// A plain 64-bit pointer value relocation.
30 /// Fixup expression:
31 /// Fixup <- Target + Addend : uint64
35 /// A plain 32-bit pointer value relocation.
[all …]
|
| D | aarch64.h | 1 //=== aarch64.h - Generic JITLink aarch64 edge kinds, utilities -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
24 /// Represents aarch64 fixups and other aarch64-specific edge kinds.
27 /// A plain 64-bit pointer value relocation.
29 /// Fixup expression:
30 /// Fixup <- Target + Addend : uint64
34 /// A plain 32-bit pointer value relocation.
36 /// Fixup expression:
[all …]
|
| D | loongarch.h | 1 //= loongarch.h - Generic JITLink loongarch edge kinds, utilities -*- C++ -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
26 /// A plain 64-bit pointer value relocation.
28 /// Fixup expression:
29 /// Fixup <- Target + Addend : uint64
33 /// A plain 32-bit pointer value relocation.
35 /// Fixup expression:
36 /// Fixup <- Target + Addend : uint32
[all …]
|
| D | i386.h | 1 //=== i386.h - Generic JITLink i386 edge kinds, utilities -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
26 /// A plain 32-bit pointer value relocation.
28 /// Fixup expression:
29 /// Fixup <- Target + Addend : uint32
32 /// - The target must reside in the low 32-bits of the address space,
33 /// otherwise an out-of-range error will be returned.
37 /// A 32-bit PC-relative relocation.
[all …]
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| /external/clang/lib/CodeGen/ |
| D | CGCleanup.cpp | 1 //===--- CGCleanup.cpp - Bookkeeping and code emission for cleanups -------===//
8 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
46 CGF.CreateDefaultAlignTempAlloca(V->getType(), "saved-rvalue"); in save()
54 llvm::StructType::get(V.first->getType(), V.second->getType(), in save()
56 Address addr = CGF.CreateDefaultAlignTempAlloca(ComplexTy, "saved-complex"); in save()
60 CGF.CGM.getDataLayout().getTypeAllocSize(V.first->getType())); in save()
73 CGF.CreateTempAlloca(V.getType(), CGF.getPointerAlign(), "saved-rvalue"); in save()
79 /// Given a saved r-value produced by SaveRValue, perform the code
84 auto alignment = cast<llvm::AllocaInst>(value)->getAlignment(); in restore()
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| D | EHScopeStack.h | 1 //===-- EHScopeStack.h - Stack for cleanup IR generation --------*- C++ -*-===//
8 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
31 /// A branch fixup. These are required when emitting a goto to a
33 /// emitted as a branch to the basic block for the label, and (if it
34 /// occurs in a scope with non-trivial cleanups) a fixup is added to
38 /// The block containing the terminator which needs to be modified
39 /// into a switch if this fixup is resolved into the current scope.
45 /// This can be set to null to indicate that this fixup was
52 /// The initial branch of the fixup.
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| /external/rust/crates/config/.github/workflows/ |
| D | fixupmerge.yml | 6 block-fixup:
7 runs-on: ubuntu-latest
10 - uses: actions/checkout@v3
11 - name: Block Fixup Commit Merge
12 uses: 13rac1/block-fixup-merge-action@v2.0.0
|
| /external/python/cpython2/Lib/ |
| D | sre_compile.py | 1 # -*- coding: utf-8 -*-
7 # Copyright (c) 1997-2001 by Secret Labs AB. All rights reserved.
91 code[skip] = _len(code) - skip
101 def fixup(literal, flags=flags): function
105 fixup = None
107 _compile_charset(av, flags, code, fixup, fixes)
108 code[skip] = _len(code) - skip
123 code[skip] = _len(code) - skip
134 code[skip] = _len(code) - skip
141 code[skip] = _len(code) - skip
[all …]
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| D | ARMFixCortexA57AES1742098Pass.cpp | 1 //===-- ARMFixCortexA57AES1742098Pass.cpp ---------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // - Cortex-A57 Erratum 1742098
10 // - Cortex-A72 Erratum 1655431
21 // - an input vector register to the AES instruction is defined outside the
24 // - an input vector register to the AES instruction is updated along multiple
25 // different control-flow paths, where we have to ensure all the register
33 //===----------------------------------------------------------------------===//
66 #define DEBUG_TYPE "arm-fix-cortex-a57-aes-1742098"
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/ExecutionEngine/JITLink/ |
| D | JITLinkGeneric.h | 1 //===------ JITLinkGeneric.h - Generic JIT linker utilities -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Generic JITLinker utilities. E.g. graph pruning, eh-frame parsing.
11 //===----------------------------------------------------------------------===//
35 assert(this->Ctx && "Ctx can not be null"); in JITLinkerBase()
36 assert(this->G && "G can not be null"); in JITLinkerBase()
49 // a GOT start symbol prior to fixup).
53 // 1.1: Run pre-prune passes
55 // 1.3: Run post-prune passes
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFixupHwLoops.cpp | 1 //===---- HexagonFixupHwLoops.cpp - Fixup HW loops too far from LOOPn. ----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
12 //===----------------------------------------------------------------------===//
28 "hexagon-loop-range", cl::Hidden, cl::init(200),
53 return "Hexagon Hardware Loop Fixup"; in getPassName()
63 /// the loop basic block to determine if we can use the LOOP instruction
77 "Hexagon Hardware Loops Fixup", false, false)
103 /// pass computes the offset of the basic block from the start.
109 // Map for each basic block to it's first instruction. in fixupLoopInstrs()
115 // First pass - compute the offset of each basic block. in fixupLoopInstrs()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFixupHwLoops.cpp | 1 //===---- HexagonFixupHwLoops.cpp - Fixup HW loops too far from LOOPn. ----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
12 //===----------------------------------------------------------------------===//
28 "hexagon-loop-range", cl::Hidden, cl::init(200),
53 return "Hexagon Hardware Loop Fixup"; in getPassName()
63 /// the loop basic block to determine if we can use the LOOP instruction
77 "Hexagon Hardware Loops Fixup", false, false)
103 /// pass computes the offset of the basic block from the start.
109 // Map for each basic block to it's first instruction. in fixupLoopInstrs()
115 // First pass - compute the offset of each basic block. in fixupLoopInstrs()
[all …]
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFixupHwLoops.cpp | 1 //===---- HexagonFixupHwLoops.cpp - Fixup HW loops too far from LOOPn. ----===//
13 //===----------------------------------------------------------------------===//
29 "hexagon-loop-range", cl::Hidden, cl::init(200),
54 return "Hexagon Hardware Loop Fixup"; in getPassName()
64 /// the loop basic block to determine if we can use the LOOP instruction
78 "Hexagon Hardware Loops Fixup", false, false)
104 /// pass computes the offset of the basic block from the start.
110 // Map for each basic block to it's first instruction. in fixupLoopInstrs()
116 // First pass - compute the offset of each basic block. in fixupLoopInstrs()
121 // aligned basic block according to the alignment value. in fixupLoopInstrs()
[all …]
|
| /external/python/cpython3/Lib/re/ |
| D | _compiler.py | 6 # Copyright (c) 1997-2001 by Secret Labs AB. All rights reserved.
84 code[skip] = _len(code) - skip
97 code[skip] = _len(code) - skip
113 code[skip] = _len(code) - skip
120 code[skip] = _len(code) - skip
126 emit((group-1)*2)
131 emit((group-1)*2+1)
142 code[skip] = _len(code) - skip
153 raise error("look-behind requires fixed-width pattern")
157 code[skip] = _len(code) - skip
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMachObjectWriter.cpp | 1 //===-- PPCMachObjectWriter.cpp - PPC Mach-O Writer -----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
30 const MCFixup &Fixup, MCValue Target,
35 const MCFragment *Fragment, const MCFixup &Fixup,
44 const MCFixup &Fixup, MCValue Target, in recordRelocation() argument
46 if (Writer->is64Bit()) { in recordRelocation()
49 RecordPPCRelocation(Writer, Asm, Layout, Fragment, Fixup, Target, in recordRelocation()
60 report_fatal_error("log2size(FixupKind): Unhandled fixup kind!"); in getFixupKindLog2Size()
80 /// Translates generic PPC fixup kind to Mach-O/PPC relocation type enum.
[all …]
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMachObjectWriter.cpp | 1 //===-- PPCMachObjectWriter.cpp - PPC Mach-O Writer -----------------------===//
8 //===----------------------------------------------------------------------===//
31 const MCFixup &Fixup, MCValue Target,
36 const MCFragment *Fragment, const MCFixup &Fixup,
45 const MCFixup &Fixup, MCValue Target, in recordRelocation() argument
47 if (Writer->is64Bit()) { in recordRelocation()
50 RecordPPCRelocation(Writer, Asm, Layout, Fragment, Fixup, Target, in recordRelocation()
61 report_fatal_error("log2size(FixupKind): Unhandled fixup kind!"); in getFixupKindLog2Size()
81 /// Translates generic PPC fixup kind to Mach-O/PPC relocation type enum.
85 // Fixup.getKind() in getRelocType()
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| D | FixupStatepointCallerSaved.cpp | 1 //===-- FixupStatepointCallerSaved.cpp - Fixup caller saved registers ----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
15 /// The need to fixup (i.e this pass) is specifically handling the fact that
21 //===----------------------------------------------------------------------===//
35 #define DEBUG_TYPE "fixup-statepoint-caller-saved"
41 "fixup-scs-extend-slot-size", cl::Hidden, cl::init(false),
46 "fixup-allow-gcptr-in-csr", cl::Hidden, cl::init(false),
50 "fixup-scs-enable-copy-propagation", cl::Hidden, cl::init(true),
56 "fixup-max-csr-statepoints", cl::Hidden,
[all …]
|
| D | CFIFixup.cpp | 1 //===------ CFIFixup.cpp - Insert CFI remember/restore instructions -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 // of the call-frame information caused by final machine basic block layout.
14 // * there is a single basic block, containing the function prologue
15 // * possibly multiple epilogue blocks, where each epilogue block is
16 // complete and self-contained, i.e. CSR restore instructions (and the
19 // Thus, during execution, at the beginning and at the end of each basic block
21 // - "has a call frame", if the function has executed the prologue, and
23 // - "does not have a call frame", if the function has not executed the
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MachObjectWriter.cpp | 1 //===-- X86MachObjectWriter.cpp - X86 Mach-O Writer -----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
31 const MCFixup &Fixup,
39 const MCFixup &Fixup,
47 const MCFixup &Fixup,
52 const MCFragment *Fragment, const MCFixup &Fixup,
61 const MCFixup &Fixup, MCValue Target, in recordRelocation() argument
63 if (Writer->is64Bit()) in recordRelocation()
64 RecordX86_64Relocation(Writer, Asm, Layout, Fragment, Fixup, Target, in recordRelocation()
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MachObjectWriter.cpp | 1 //===-- X86MachObjectWriter.cpp - X86 Mach-O Writer -----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
31 const MCFixup &Fixup,
39 const MCFixup &Fixup,
47 const MCFixup &Fixup,
52 const MCFragment *Fragment, const MCFixup &Fixup,
61 const MCFixup &Fixup, MCValue Target, in recordRelocation() argument
63 if (Writer->is64Bit()) in recordRelocation()
64 RecordX86_64Relocation(Writer, Asm, Layout, Fragment, Fixup, Target, in recordRelocation()
[all …]
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MachObjectWriter.cpp | 1 //===-- X86MachObjectWriter.cpp - X86 Mach-O Writer -----------------------===//
8 //===----------------------------------------------------------------------===//
32 const MCFixup &Fixup,
40 const MCFixup &Fixup,
48 const MCFixup &Fixup,
53 const MCFragment *Fragment, const MCFixup &Fixup,
62 const MCFixup &Fixup, MCValue Target, in recordRelocation() argument
64 if (Writer->is64Bit()) in recordRelocation()
65 RecordX86_64Relocation(Writer, Asm, Layout, Fragment, Fixup, Target, in recordRelocation()
68 RecordX86Relocation(Writer, Asm, Layout, Fragment, Fixup, Target, in recordRelocation()
[all …]
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssembler.h | 1 //===- subzero/src/IceAssembler.h - Integrated assembler --------*- C++ -*-===//
4 // BSD-style license that can be found in the LICENSE file.
8 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
20 /// Instructions are assembled by architecture-specific assemblers that derive
24 //===----------------------------------------------------------------------===//
41 /// - Unused.
42 /// - Linked, unplaced and tracking the position of branches to the label.
43 /// - Bound, placed and tracking its position.
64 return -Position - kWordSize; in getPosition()
[all …]
|
| /external/flac/test/ |
| D | test_flac.sh | 1 #!/bin/sh -e
3 # FLAC - Free Lossless Audio Codec
4 # Copyright (C) 2001-2009 Josh Coalson
5 # Copyright (C) 2011-2023 Xiph.Org Foundation
9 # are distributed under Xiph.Org's BSD-like license (see the file
23 # we use '.' as decimal separator in --skip/--until tests
33 flac${EXE} --help 1>/dev/null 2>/dev/null || die "ERROR can't find flac executable"
38 …echo "valgrind --leak-check=yes --show-reachable=yes --num-callers=50 flac $*" >>test_flac.valgrin…
39 …valgrind --leak-check=yes --show-reachable=yes --num-callers=50 --log-fd=4 flac${EXE} $TOTALLY_SIL…
41 flac${EXE} $TOTALLY_SILENT --no-error-on-compression-fail $*
[all …]
|
| /external/arm-trusted-firmware/lib/aarch64/ |
| D | misc_helpers.S | 2 * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
33 /* -----------------------------------------------------------------------
42 * -----------------------------------------------------------------------
46 /* -----------------------------------------------------------------------
55 * -----------------------------------------------------------------------
67 /* -----------------------------------------------------------------------
75 * is disabled, all memory behaves like Device-nGnRnE memory (see section
77 * NOTE: The code assumes that the block size as defined in DCZID_EL0
80 * -----------------------------------------------------------------------
[all …]
|
| /external/trusty/arm-trusted-firmware/lib/aarch64/ |
| D | misc_helpers.S | 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
33 /* -----------------------------------------------------------------------
42 * -----------------------------------------------------------------------
46 /* -----------------------------------------------------------------------
55 * -----------------------------------------------------------------------
67 /* -----------------------------------------------------------------------
75 * is disabled, all memory behaves like Device-nGnRnE memory (see section
77 * NOTE: The code assumes that the block size as defined in DCZID_EL0
80 * -----------------------------------------------------------------------
[all …]
|