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/external/llvm/lib/Target/X86/
DX86Schedule.td17 def ReadAfterLd : SchedRead;
21 def WriteRMW : SchedWrite;
35 def Ld : SchedWrite;
37 def NAME : X86FoldableSchedWrite {
45 def WriteIMulH : SchedWrite; // Integer multiplication, high part.
47 def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
53 def WriteLoad : SchedWrite;
54 def WriteStore : SchedWrite;
55 def WriteMove : SchedWrite;
59 def WriteZero : SchedWrite;
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/external/llvm/lib/Target/ARM/
DARMSchedule.td32 // def WriteALUsr : SchedWrite;
33 // def ReadAdvanceALUsr : ScheRead;
36 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
45 // def P01 : ProcResource<3>; // ALU unit (3 of it).
48 // def : WriteRes<WriteALUsr, [P01, P01]> {
55 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
58 def WriteALU : SchedWrite;
59 def ReadALU : SchedRead;
62 def WriteALUsi : SchedWrite; // Shift by immediate.
63 def WriteALUsr : SchedWrite; // Shift by register.
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsHexagon.td71 def int_hexagon_circ_ldd :
76 def int_hexagon_circ_ldw :
81 def int_hexagon_circ_ldh :
86 def int_hexagon_circ_lduh :
91 def int_hexagon_circ_ldb :
96 def int_hexagon_circ_ldub :
102 def int_hexagon_circ_std :
107 def int_hexagon_circ_stw :
112 def int_hexagon_circ_sth :
117 def int_hexagon_circ_sthhi :
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DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
16 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
17 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
18 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
20 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
21 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
22 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
24 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
27 def int_aarch64_clrex : Intrinsic<[]>;
29 def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMSchedule.td31 // def WriteALUsr : SchedWrite;
32 // def ReadAdvanceALUsr : ScheRead;
35 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
47 // def : WriteRes<WriteALUsr, [P01, P01]> {
54 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
60 def WriteALU : SchedWrite;
61 def ReadALU : SchedRead;
64 def WriteALUsi : SchedWrite; // Shift by immediate.
65 def WriteALUsr : SchedWrite; // Shift by register.
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/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/IR/
DIntrinsicsHexagonDep.td1063 def int_hexagon_A2_abs :
1066 def int_hexagon_A2_absp :
1069 def int_hexagon_A2_abssat :
1072 def int_hexagon_A2_add :
1075 def int_hexagon_A2_addh_h16_hh :
1078 def int_hexagon_A2_addh_h16_hl :
1081 def int_hexagon_A2_addh_h16_lh :
1084 def int_hexagon_A2_addh_h16_ll :
1087 def int_hexagon_A2_addh_h16_sat_hh :
1090 def int_hexagon_A2_addh_h16_sat_hl :
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DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
26 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
28 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
31 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
35 def int_aarch64_clrex : Intrinsic<[]>;
37 def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/
DARMSchedule.td31 // def WriteALUsr : SchedWrite;
32 // def ReadAdvanceALUsr : ScheRead;
35 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
47 // def : WriteRes<WriteALUsr, [P01, P01]> {
54 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
60 def WriteALU : SchedWrite;
61 def ReadALU : SchedRead;
64 def WriteALUsi : SchedWrite; // Shift by immediate.
65 def WriteALUsr : SchedWrite; // Shift by register.
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/external/clang/include/clang/Basic/
DStmtNodes.td12 def NullStmt : Stmt;
13 def CompoundStmt : Stmt;
14 def LabelStmt : Stmt;
15 def AttributedStmt : Stmt;
16 def IfStmt : Stmt;
17 def SwitchStmt : Stmt;
18 def WhileStmt : Stmt;
19 def DoStmt : Stmt;
20 def ForStmt : Stmt;
21 def GotoStmt : Stmt;
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DDiagnosticGroups.td10 def ImplicitFunctionDeclare : DiagGroup<"implicit-function-declaration">;
11 def ImplicitInt : DiagGroup<"implicit-int">;
14 def Implicit : DiagGroup<"implicit", [
20 def : DiagGroup<"abi">;
21 def AbsoluteValue : DiagGroup<"absolute-value">;
22 def AddressOfTemporary : DiagGroup<"address-of-temporary">;
23 def : DiagGroup<"aggregate-return">;
24 def GNUAlignofExpression : DiagGroup<"gnu-alignof-expression">;
25 def AmbigMemberTemplate : DiagGroup<"ambiguous-member-template">;
26 def GNUAnonymousStruct : DiagGroup<"gnu-anonymous-struct">;
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DDeclNodes.td13 def TranslationUnit : Decl, DeclContext;
14 def PragmaComment : Decl;
15 def PragmaDetectMismatch : Decl;
16 def ExternCContext : Decl, DeclContext;
17 def Named : Decl<1>;
18 def Namespace : DDecl<Named>, DeclContext;
19 def UsingDirective : DDecl<Named>;
20 def NamespaceAlias : DDecl<Named>;
21 def Label : DDecl<Named>;
22 def Type : DDecl<Named, 1>;
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/
DRISCVSchedule.td9 /// Define scheduler resources associated with def operands.
10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
13 def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
14 def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
15 def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
16 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
17 def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
18 def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/
DPPCSchedule.td12 def IIC_IntSimple : InstrItinClass;
13 def IIC_IntGeneral : InstrItinClass;
14 def IIC_IntCompare : InstrItinClass;
15 def IIC_IntISEL : InstrItinClass;
16 def IIC_IntDivD : InstrItinClass;
17 def IIC_IntDivW : InstrItinClass;
18 def IIC_IntMFFS : InstrItinClass;
19 def IIC_IntMFVSCR : InstrItinClass;
20 def IIC_IntMTFSB0 : InstrItinClass;
21 def IIC_IntMTSRD : InstrItinClass;
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/external/clang/include/clang/AST/
DCommentHTMLNamedCharacterReferences.td15 def : NCR<"copy", 0x000A9>;
16 def : NCR<"COPY", 0x000A9>;
17 def : NCR<"trade", 0x02122>;
18 def : NCR<"TRADE", 0x02122>;
19 def : NCR<"reg", 0x000AE>;
20 def : NCR<"REG", 0x000AE>;
21 def : NCR<"lt", 0x0003C>;
22 def : NCR<"Lt", 0x0003C>;
23 def : NCR<"LT", 0x0003C>;
24 def : NCR<"gt", 0x0003E>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCSchedule.td12 def IIC_IntSimple : InstrItinClass;
13 def IIC_IntGeneral : InstrItinClass;
14 def IIC_IntCompare : InstrItinClass;
15 def IIC_IntISEL : InstrItinClass;
16 def IIC_IntDivD : InstrItinClass;
17 def IIC_IntDivW : InstrItinClass;
18 def IIC_IntMFFS : InstrItinClass;
19 def IIC_IntMFVSCR : InstrItinClass;
20 def IIC_IntMTFSB0 : InstrItinClass;
21 def IIC_IntMTSRD : InstrItinClass;
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/external/llvm/lib/Target/PowerPC/
DPPCSchedule.td13 def IIC_IntSimple : InstrItinClass;
14 def IIC_IntGeneral : InstrItinClass;
15 def IIC_IntCompare : InstrItinClass;
16 def IIC_IntISEL : InstrItinClass;
17 def IIC_IntDivD : InstrItinClass;
18 def IIC_IntDivW : InstrItinClass;
19 def IIC_IntMFFS : InstrItinClass;
20 def IIC_IntMFVSCR : InstrItinClass;
21 def IIC_IntMTFSB0 : InstrItinClass;
22 def IIC_IntMTSRD : InstrItinClass;
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AVR/
DAVRDevices.td34 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
38 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
43 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL", "true",
48 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL", "true",
53 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW", "true",
58 def FeatureSmallStack
64 def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
70 def FeaturePROGMEM : SubtargetFeature<"progmem", "m_hasPROGMEM", "true",
74 def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
78 def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRDevices.td35 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
39 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
45 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL",
51 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL",
56 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW",
61 def FeatureSmallStack : SubtargetFeature<"smallstack", "m_hasSmallStack",
66 def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
71 def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
75 def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
80 def FeatureELPM : SubtargetFeature<"elpm", "m_hasELPM", "true",
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV5.td9 def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>;
10 def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>;
11 def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>;
14 def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>;
16 def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>;
17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>;
18 def: T_PP_pat<A2_minp, int_hexagon_A2_minp>;
19 def: T_PP_pat<A2_minup, int_hexagon_A2_minup>;
20 def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>;
21 def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV5.td9 def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>;
10 def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>;
11 def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>;
14 def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>;
16 def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>;
17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>;
18 def: T_PP_pat<A2_minp, int_hexagon_A2_minp>;
19 def: T_PP_pat<A2_minup, int_hexagon_A2_minup>;
20 def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>;
21 def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>;
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/external/mesa3d/src/util/
Ddriconf.h72 #define DRI_CONF_OPT_B(_name, def, _desc) { \ argument
78 .value = { ._bool = def }, \
81 #define DRI_CONF_OPT_I(_name, def, min, max, _desc) { \ argument
88 .value = { ._int = def }, \
91 #define DRI_CONF_OPT_F(_name, def, min, max, _desc) { \ argument
98 .value = { ._float = def }, \
101 #define DRI_CONF_OPT_E(_name, def, min, max, _desc, values) { \ argument
108 .value = { ._int = def }, \
112 #define DRI_CONF_OPT_S(_name, def, _desc) { \ argument
118 .value = { ._string = #def }, \
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/external/ply/ply/example/ansic/
Dcparse.py17 def p_translation_unit_1(t):
22 def p_translation_unit_2(t):
29 def p_external_declaration_1(t):
34 def p_external_declaration_2(t):
41 def p_function_definition_1(t):
46 def p_function_definition_2(t):
51 def p_function_definition_3(t):
56 def p_function_definition_4(t):
63 def p_declaration_1(t):
68 def p_declaration_2(t):
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVSchedule.td9 /// Define scheduler resources associated with def operands.
10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShift32 : SchedWrite; // 32-bit shift operations on RV64Ix
13 def WriteShift : SchedWrite; // 32 or 64-bit shift operations
14 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
15 def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
16 def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
17 def WriteIMul32 : SchedWrite; // 32-bit multiply on RV64I
18 def WriteJmp : SchedWrite; // Jump
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/external/sdv/vsomeip/third_party/boost/icl/doc/
Dicl.qbk23 [def __itv__ [classref boost::icl::interval interval]]
24 [def __Itv__ [classref boost::icl::interval Interval]]
26 [def __itv_tr__ [classref boost::icl::interval_traits interval_traits]]
27 [def __Itv_tr__ [classref boost::icl::interval_traits Interval_traits]]
29 [def __ro_itv__ [classref boost::icl::right_open_interval right_open_interval]]
30 [def __lo_itv__ [classref boost::icl::left_open_interval left_open_interval]]
31 [def __op_itv__ [classref boost::icl::open_interval open_interval]]
32 [def __cl_itv__ [classref boost::icl::closed_interval closed_interval]]
34 [def __dc_itv__ [classref boost::icl::discrete_interval discrete_interval]]
35 [def __ct_itv__ [classref boost::icl::continuous_interval continuous_interval]]
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/external/sdv/vsomeip/third_party/boost/fusion/doc/
Dfusion.qbk24 [def __spirit__ [@http://boost-spirit.com/home/ Spirit]]
25 [def __phoenix__ [@http://www.boost.org/libs/phoenix Phoenix]]
26 [def __mpl__ [@http://www.boost.org/libs/mpl MPL]]
27 [def __stl__ [@http://en.wikipedia.org/wiki/Standard_Template_Library STL]]
28 [def __tuple__ [@http://www.boost.org/libs/tuple Boost.Tuple]]
29 [def __tr1__tuple__ [@http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2002/n1403.pdf…
30 [def __boost_tools__ [@http://www.boost.org/tools/index.html Boost Tools]]
31 [def __spirit_list__ [@https://sourceforge.net/projects/spirit/lists/spirit-general Spir…
32 [def __list_archive__ [@https://sourceforge.net/p/spirit/mailman/spirit-general/ archive]]
33 [def __jaakko_jarvi__ [@http://www.boost.org/people/jaakko_jarvi.htm Jaakko Jarvi]]
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