| /external/arm-neon-tests/ |
| D | Init.s | 4 ; Cortex-A8 Dhrystone example - Startup Code
26 ; Disable Cortex-A8 MMU if enabled
51 MCR p15, 0, r0, c8, c7, 0 ; Cortex-A8 I-TLB and D-TLB invalidation
54 ; Cache Invalidation code for Cortex-A8
57 ; Invalidate L1 Instruction Cache
60 TST r0, #0x3 ; Harvard Cache?
62 MCRNE p15, 0, r0, c7, c5, 0 ; Invalidate Instruction Cache
68 MOV r3, r3, LSR #23 ; Total cache levels << 1
71 MOV r10, #0 ; R10 holds current cache level << 1
72 Loop1 ADD r2, r10, r10, LSR #1 ; R2 holds cache "Set" position
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| /external/mesa3d/src/amd/compiler/ |
| D | README-ISA.md | 8 D.u = abs(S0.i - S1.i) + S2.u.
15 ABS_DIFF (A,B) = (A>B) ? (A-B) : (B-A)
21 `v_sad_u32(-5, 0, 0)` would return `4294967291` (`-5` interpreted as unsigned),
78 > and sent to the texture cache. Any texture or buffer resources and samplers
79 > are also sent immediately. However, write-data is not immediately sent to the
80 > texture cache.
102 ## FLAT, Scratch, Global instructions
118 GFX7-8 ISA manuals are mistaken about the available LDS size.
138 ## RDNA L0, L1 cache and DLC, GLC bits
140 The old L1 cache was renamed to L0, and a new L1 cache was added to RDNA. The
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| /external/mesa3d/src/amd/common/ |
| D | amd_kernel_code_t.h | 4 * SPDX-License-Identifier: MIT
10 //---------------------------------------------------------------------------//
12 //---------------------------------------------------------------------------//
48 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH) - 1)
54 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_WIDTH) - 1)
60 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_WIDTH) - 1)
66 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH) - 1)
72 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_WIDTH) - 1)
78 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_WIDTH) - 1)
84 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_WIDTH) - 1)
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| /external/tensorflow/tensorflow/core/kernels/ |
| D | deep_conv2d.cc | 7 http://www.apache.org/licenses/LICENSE-2.0
57 // Element-wise products (each product is a MatMul across depth). in GetDeepConvCost()
66 const int64_t row_tiles = (out_rows + out_tile_rows - 1) / out_tile_rows; in GetDeepConvCost()
67 const int64_t col_tiles = (out_cols + out_tile_cols - 1) / out_tile_cols; in GetDeepConvCost()
208 const int64_t base_filter_rows = transform->filter_shape().rows; in operator ()()
209 const int64_t base_filter_cols = transform->filter_shape().cols; in operator ()()
212 const int64_t tile_rows = transform->input_shape().rows; in operator ()()
213 const int64_t tile_cols = transform->input_shape().cols; in operator ()()
266 // 'filter_in' into 'filter_buf', adding zero-padding as needed.
294 const int64_t num_filters = od_limit - od_start; in operator ()()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDKernelCodeT.h | 1 //===-- AMDGPUKernelCodeT.h - Print AMDGPU assembly code ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
20 //---------------------------------------------------------------------------//
22 //---------------------------------------------------------------------------//
91 …BUFFER = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH) - 1) << AMD_CODE_PROPE…
95 …GPR_DISPATCH_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
99 …AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_WIDTH) - …
103 …GMENT_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
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| D | SIInstrFormats.td | 1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 // Low bits - basic encoding information.
43 field bit FLAT = 0;
50 // High bits - other information.
63 // Most sopk treat the immediate as a signed 16-bit, however some
67 // This is an s_store_dword* instruction that requires a cache flush
69 // SMEM instructions like the cache flush ones.
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| D | AMDKernelCodeT.h | 1 //===-- AMDGPUKernelCodeT.h - Print AMDGPU assembly code ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
16 //---------------------------------------------------------------------------//
18 //---------------------------------------------------------------------------//
87 …BUFFER = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH) - 1) << AMD_CODE_PROPE…
91 …GPR_DISPATCH_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
95 …AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_WIDTH) - …
99 …GMENT_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
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|
| D | SIInstrFormats.td | 1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 // Low bits - basic encoding information.
44 field bit FLAT = 0;
57 // High bits - other information.
70 // Most sopk treat the immediate as a signed 16-bit, however some
74 // This is an s_store_dword* instruction that requires a cache flush
76 // SMEM instructions like the cache flush ones.
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDKernelCodeT.h | 1 //===-- AMDGPUKernelCodeT.h - Print AMDGPU assembly code ---------*- C++ -*-===//
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
21 //---------------------------------------------------------------------------//
23 //---------------------------------------------------------------------------//
92 …BUFFER = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH) - 1) << AMD_CODE_PROPE…
96 …GPR_DISPATCH_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
100 …AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_WIDTH) - …
104 …GMENT_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
108 …_SGPR_DISPATCH_ID = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_WIDTH) - 1) << AMD_CODE_PROPE…
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|
| /external/mesa3d/docs/relnotes/ |
| D | 18.1.6.rst | 16 ----------------
20 580e03328ffefe1fd43b19ab7669f20d931601a1c0a4c0f8b9c65d6e81a06df3 mesa-18.1.6.tar.gz
21 bb7ce759069801804fcfb8152da3457f76cd7b4e0096e4870ff5adcb5c894289 mesa-18.1.6.tar.xz
24 ------------
29 ---------
31 - `Bug 13728 <https://bugs.freedesktop.org/show_bug.cgi?id=13728>`__ -
34 - `Bug 98699 <https://bugs.freedesktop.org/show_bug.cgi?id=98699>`__ -
36 - `Bug 99730 <https://bugs.freedesktop.org/show_bug.cgi?id=99730>`__ -
39 - `Bug 106382 <https://bugs.freedesktop.org/show_bug.cgi?id=106382>`__
40 - Shader cache breaks INTEL_DEBUG=shader_time
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|
| D | 9.1.1.rst | 15 -------------
19 6508d9882d8dce7106717f365632700c MesaLib-9.1.1.tar.gz
20 6ea2bdc3b7ecfb4257b39814b4182580 MesaLib-9.1.1.tar.bz2
21 3434c0eb47849a08c53cd32833d10d13 MesaLib-9.1.1.zip
24 ------------
29 ---------
33 - `Bug 30232 <https://bugs.freedesktop.org/show_bug.cgi?id=30232>`__ -
35 - `Bug 32429 <https://bugs.freedesktop.org/show_bug.cgi?id=32429>`__ -
37 - `Bug 38086 <https://bugs.freedesktop.org/show_bug.cgi?id=38086>`__ -
38 Mesa 7.11-devel implementation error: Unexpected program target in
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|
| D | 9.1.3.rst | 15 -------------
19 952ccd03547ed72333b64e1746cf8ada MesaLib-9.1.3.tar.bz2
20 26d2f1aa8e9db388d51fcbd163c61fb7 MesaLib-9.1.3.tar.gz
21 7017b7bdf0ebfd39a5c46cee7cf6b567 MesaLib-9.1.3.zip
24 ------------
29 ---------
33 - `Bug 39251 <https://bugs.freedesktop.org/show_bug.cgi?id=39251>`__ -
36 - `Bug 47478 <https://bugs.freedesktop.org/show_bug.cgi?id=47478>`__ -
39 - `Bug 56416 <https://bugs.freedesktop.org/show_bug.cgi?id=56416>`__ -
42 - `Bug 57436 <https://bugs.freedesktop.org/show_bug.cgi?id=57436>`__ -
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|
| /external/tensorflow/tensorflow/dtensor/cc/ |
| D | dtensor_tpu_kernels.cc | 7 http://www.apache.org/licenses/LICENSE-2.0
57 Status status = resource_manager->Delete<ResourceT>( in DeleteIfExists()
58 resource_manager->default_container(), resource_name); in DeleteIfExists()
89 OP_REQUIRES_OK(ctx, tpu_system->Initialize(ctx, rmgr, retry_timeout, in Compute()
105 ctx->allocate_output( in Compute()
109 ctx_output->flat<int32>()(i) = core_id_output_vec[i]; in Compute()
133 // Create the subgraph compilation cache and put it in the local resource in InitializeInternal()
150 while (!tpu_platform->Initialized() && in InitializeInternal()
151 (absl::Now() - start < retry_timeout)) { in InitializeInternal()
153 init_status = tpu_platform->Initialize({}); in InitializeInternal()
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|
| /external/mesa3d/docs/drivers/ |
| D | asahi.rst | 7 -----------------
12 reverse-engineering the hardware, as glue to get at the "interesting" GPU
15 The library is only built if ``-Dtools=asahi`` is passed. It builds a single
24 -----------------
36 ``st_var`` instruction. ``st_var`` takes a *vertex output index* and a 32-bit
39 consist of a single 32-bit value or an aligned 16-bit register pair, depending
40 on whether interpolation should happen at 32-bit or 16-bit. Vertex outputs are
42 32-bit user varyings coming next with perspective, flat, and linear interpolated
43 varyings grouped in that order, then 16-bit user varyings with the same groupings,
51 .. list-table:: Ordering of vertex outputs with all outputs used
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| /external/tensorflow/tensorflow/core/kernels/mkl/ |
| D | mkl_conv_ops.cc | 7 http://www.apache.org/licenses/LICENSE-2.0
100 return context_.fwd_pd->scratchpad_desc(); in GetScratchPadDesc()
121 // When we are using single global cache then in this case we can have in Execute()
127 // TODO(intel-tf): Create a common function and avoid the duplicate code in Execute()
128 context_.src_mem->set_data_handle( in Execute()
130 context_.filter_mem->set_data_handle( in Execute()
133 context_.bias_mem->set_data_handle( in Execute()
137 context_.bn_scale_mem->set_data_handle( in Execute()
139 context_.bn_mean_mem->set_data_handle( in Execute()
141 context_.bn_rsqrt_mem->set_data_handle( in Execute()
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| D | mkl_qmatmul_op.cc | 7 http://www.apache.org/licenses/LICENSE-2.0
16 // Implements a quantized eight-bit version of the matmul operation with bias,
19 // - Input: quantized as uint8 via either MIN_FIRST or SCALE mode.
20 // SCALE mode is selected when input is guaranteed to be non-
23 // - Weight: quantized to int8 via SCALE mode.
24 // - Bias: float32/int32. For int32, it is quantized according to input and
25 // filter min-max values.
35 // With SCALE quantization (used for non-negative Af32), Qa and Au8 can be
40 // Q'a = 255.0 / (Max(Af32) - Min(Af32))
41 // A'u8 = round(Q'a * (Af32 - Min(Af32) * ones(Af32))),
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| D | mkl_batch_matmul_op.cc | 7 http://www.apache.org/licenses/LICENSE-2.0
18 // This file uses oneDNN library for acceleration of Batch Matrix-Matrix
52 OP_REQUIRES_OK(context, context->GetAttr("adj_x", &adj_x_)); in BatchMatMulMkl()
53 OP_REQUIRES_OK(context, context->GetAttr("adj_y", &adj_y_)); in BatchMatMulMkl()
59 const Tensor& lhs = ctx->input(0); in Compute()
60 const Tensor& rhs = ctx->input(1); in Compute()
73 for (int i = 0; i < ndims - 2; ++i) { in Compute()
103 auto lhs_rows = lhs.dim_size(ndims_lhs - 2); in Compute()
104 auto lhs_cols = lhs.dim_size(ndims_lhs - 1); in Compute()
105 auto rhs_rows = rhs.dim_size(ndims_rhs - 2); in Compute()
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| /external/tensorflow/tensorflow/lite/kernels/internal/ |
| D | types.h | 7 http://www.apache.org/licenses/LICENSE-2.0
61 // This enumeration allows for non-default formats for the weights array
62 // of a fully-connected operator, allowing the use of special optimized
65 // Default format (flat 2D layout, the inner contiguous dimension
66 // is input_depth, the outer non-contiguous dimension is output_depth)
70 // 8-bit quantized layers.
72 // The use case we're concerned with here is: 8-bit quantization,
73 // large weights matrix that doesn't fit in cache (e.g. 4096x2048 in
74 // a key application that drove this), very small batch size (e.g. 1 -- 4).
76 // Even with 8-bit quantization of weights, the performance of memory
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| /external/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
| D | fd3_program.c | 47 return (!rast->depth_clip_near || in fd3_needs_manual_clipping()
48 util_bitcount(rast->clip_plane_enable) > 6 || in fd3_needs_manual_clipping()
57 const struct ir3_info *si = &so->info; in emit_shader()
62 if (so->type == MESA_SHADER_VERTEX) { in emit_shader()
69 sz = si->sizedwords; in emit_shader()
71 bin = fd_bo_map(so->bo); in emit_shader()
81 CP_LOAD_STATE_0_NUM_UNIT(so->instrlen)); in emit_shader()
86 OUT_RELOC(ring, so->bo, 0, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0); in emit_shader()
112 vsi = &vp->info; in fd3_program_emit()
113 fsi = &fp->info; in fd3_program_emit()
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| /external/libchrome/base/containers/ |
| D | README.md | 5 This directory contains some STL-like containers.
19 For STL-like containers our policy is that they should use STL-like naming even
21 be lower case with underscores. Non-STL-like classes and functions should use
35 moved efficiently. In this case, consider **base::flat\_map** and
36 **base::flat\_set**. You need to be aware of the maximum expected size of
40 several dozen items, and efficiently-moved types are unlikely to have
47 mutation performance of large containers that base::flat\_map has. But this
56 Sizes are on 64-bit platforms. Stable iterators aren't invalidated when the
59 | Container | Empty size | Per-item overhead | Stable ite…
60 |:---------------------------------------- |:--------------------- |:----------------- |:----------…
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| /external/tensorflow/tensorflow/compiler/jit/tests/ |
| D | xla_compilation_cache_test_helper.cc | 7 http://www.apache.org/licenses/LICENSE-2.0
32 for (int64 i = 0; i < tensor.flat<float>().size(); ++i) { in CreateInputTensor()
33 tensor.flat<float>()(i) = offset + i; in CreateInputTensor()
49 node.mutable_attr()->insert({attr.first, attr.second.proto}); in MakeNode()
72 *graph.mutable_library()->add_function() = make_test_fn; in GetTestGraph()
92 TF_RETURN_IF_ERROR(session->Create(graph)); in ExecuteWithBatch()
98 TF_RETURN_IF_ERROR(session->Run( in ExecuteWithBatch()
103 TF_RETURN_IF_ERROR(session->Close()); in ExecuteWithBatch()
111 *options.config.mutable_graph_options()->mutable_optimizer_options(); in ExecuteWithBatch()
116 TF_RETURN_IF_ERROR(session->Create(graph)); in ExecuteWithBatch()
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| /external/tensorflow/tensorflow/core/util/ |
| D | mkl_util.h | 7 http://www.apache.org/licenses/LICENSE-2.0
152 // distinguish between blocked and non-blocked formats, we have defined a new
155 // 1) FORMAT_BLOCKED: as described above, this is needed for element-wise
157 // 2) FORMAT_INVALID: for error-checking (ex. unsupported format)
160 // FORMAT_X - 1D tensor
161 // FORMAT_NC - 2D tensor
162 // FORMAT_TNC - 3D tensor
264 #define INVALID_DIM_SIZE -1
270 data_.sizes_[i] = -1;
273 data_.map_[i] = -1;
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| /external/tensorflow/tensorflow/compiler/jit/kernels/ |
| D | xla_ops.cc | 7 http://www.apache.org/licenses/LICENSE-2.0
57 (CTX)->CtxFailureWithWarning(__FILE__, __LINE__, _s); \
133 XlaExecutableClosure value = std::move(it->second); in Consume()
153 return ctx->op_device_context() ? ctx->op_device_context()->stream() in GetStream()
161 int device_ordinal = stream ? stream->parent()->device_ordinal() in GetLaunchContext()
162 : client->default_device_ordinal(); in GetLaunchContext()
178 auto start_time = env->NowMicros(); in RunExecutable()
183 run_options.set_intra_op_thread_pool(&ctx->eigen_cpu_device()); in RunExecutable()
190 executable->Run(std::move(execution_inputs), run_options); in RunExecutable()
193 executable->RunAsync(std::move(execution_inputs), run_options); in RunExecutable()
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|
| /external/python/httplib2/ |
| D | index.html | 3 <!--#include virtual="header.html" -->
8 <!--#include virtual="titlebar.html" -->
23 <dt>Keep-Alive</dt>
24 <dd>Supports HTTP 1.1 Keep-Alive, keeping the socket
36 …<li><a href="http://franklinmint.fm/2006/02/28/draft-sayre-http-hmac-digest.html">HMAC Digest</a><…
43 cache that understands the Cache-Control: header and
44 uses both the ETag and Last-Modified cache validators.
71 h = httplib2.Http(".cache")
84 h = httplib2.Http(".cache")
88 headers={'content-type':'text/plain'} )
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| /external/tensorflow/tensorflow/compiler/tf2tensorrt/kernels/ |
| D | trt_engine_op.cc | 7 http://www.apache.org/licenses/LICENSE-2.0
66 LOG_FIRST_N(WARNING, 5) << "TF-TRT Warning: "
80 device_memory_allocator_->free(device_memory_); in ~ContextDeviceMemory()
92 device_memory_ = device_memory_allocator_->allocate( in AllocateDeviceMemory()
103 execution_context_->setDeviceMemory(device_memory_); in AllocateDeviceMemory()
192 // engine fails, enters a dummy entry into the cache_resource cache so we
255 // user-provided quantization ranges.
280 return (void*)X->flat<EnumToDataType<dt>::Type>().data(); \
284 auto tensor_type = tensor_ptr->dtype(); in GetTensorAddress()
301 flib_runtime->GetFunctionLibraryDefinition(); in FunctionDefToGraphDef()
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|