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/external/perfetto/docs/data-sources/
Dcpu-freq.md14 in-kernel cpufreq scaling driver changes the frequency. Note that this is not
15 supported on all platforms. In our experience it works reliably on ARM-based
16 SoCs but produces no data on most modern Intel-based platforms. This is
17 because recent Intel CPUs use an internal DVFS which is directly controlled
19 Also note that even on ARM-based platforms, the event is emitted only
28 current value in the trace buffer. Works on both Intel and ARM-based
31 On most Android devices the frequency scaling is per-cluster (group of
37 It is possible to record one-off also the full list of frequencies supported by
42 [`cpu_freq` table](/docs/analysis/sql-tables.autogen#cpu_freq).
44 This is not supported on modern Intel platforms for the same aforementioned
[all …]
/external/mesa3d/docs/relnotes/
D21.1.7.rst1 Mesa 21.1.7 Release Notes / 2021-08-11
18 ---------------
22 e9e67c10654f2e4bf15b944bb048007a614292aa4792b1b7512eb700b7b3a7bb mesa-21.1.7.tar.xz
26 ------------
28 - None
32 ---------
34 - Miscompilation of a switch case
35 - [radeonsi][regression] CPU is being used ~10 times more than usual after c5478f9067f.
36 - dEQP-VK.wsi.android.swapchain.create#image_swapchain_create_info crash on Android R
37 - The image is distorted while use iGPU(Intel GPU) rendering and output via dGPU (AMD GPU)
[all …]
D23.0.4.rst1 Mesa 23.0.4 Release Notes / 2023-05-30
18 ---------------
22 ee7f2cad1c58f943ea3048e59871908900b0a656ebdcf6a309e60af4270792f6 mesa-23.0.4.tar.xz
27 ------------
29 - None
33 ---------
35 - radv: Battlefield {1,5} hangs on RX 7900 XTX
36 - radv: graphical artifacts in MSFS running via DXVK on RX7900XT
37 - [radeonsi] flickering debug chunk border lines in Minecraft
38 - vulkan/device_select: no way to select between GPUs of the same model due to bugs
[all …]
D22.0.1.rst1 Mesa 22.0.1 Release Notes / 2022-03-29
18 ---------------
22 c05f9682c54560b36e0afa70896233fc73f1ed715e10d1a028b0eb84fd04426f mesa-22.0.1.tar.xz
26 ------------
28 - None
32 ---------
34 - freedreno: crash in PUBG
35 - [regression][bisected] MSVC: Build failure in libmesa_util when targeting x86 32-bit
36 - A crash in radeonsi driver
37 - freedreno: deqp cts fails
[all …]
D21.2.6.rst1 Mesa 21.2.6 Release Notes / 2021-11-24
18 ---------------
22 1e7e22d93c6e8859fa044b1121119d26b2e67e4184b92ebb81c66497dc80c954 mesa-21.2.6.tar.xz
26 ------------
28 - None
32 ---------
34 - NIR validation failed after nir_copy_prop
35 - lima: Corrupted Android-12 UI on Allwinner A64
36 - RADV/ACO: Rendering glitches in Forza Horizon 5 windshields
37 - dEQP-GLES31.*imulextended* compiling fp64 glsl 4.00 shader
[all …]
D22.0.2.rst1 Mesa 22.0.2 Release Notes / 2022-04-21
18 ---------------
22 df4fa560dcce6680133067cd15b0505fc424ca703244ce9ab247c74d2fab6885 mesa-22.0.2.tar.xz
26 ------------
28 - None
32 ---------
34 - Vulkan::Calling vkWaitForFences Timeout
35 - Intel (CHT) - Uplink text rendering bugged out in Mesa 22.0
36 - gen9atom gpu hang on dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_1
37 - bad memory managment on panfrost RK3399 - cannot alocate more ram - fury unleashed
[all …]
D18.0.5.rst15 ----------------
19 ea3e00329cea899b1e32db812fd2f426832be37e4baa2e2fd9288a3480f30531 mesa-18.0.5.tar.gz
20 5187bba8d72aea78f2062d134ec6079a508e8216062dce9ec9048b5eb2c4fc6b mesa-18.0.5.tar.xz
23 ------------
28 ---------
30 - `Bug 78097 <https://bugs.freedesktop.org/show_bug.cgi?id=78097>`__ -
32 - `Bug 102390 <https://bugs.freedesktop.org/show_bug.cgi?id=102390>`__
33 - centroid interpolation causes broken attribute values
34 - `Bug 105351 <https://bugs.freedesktop.org/show_bug.cgi?id=105351>`__
35 - [Gen6+] piglit's arb_shader_image_load_store-host-mem-barrier fails
[all …]
D21.1.2.rst1 Mesa 21.1.2 Release Notes / 2021-06-02
18 ---------------
22 23b4b63760561f3a4f98b5be12c6de621e9a6bdf355e087a83d9184cd4e2825f mesa-21.1.2.tar.xz
26 ------------
28 - None
32 ---------
34 - zink: regression for primitive-restart on ANV
35 - zink: Expected Image Operand ConstOffset to be a const object
36 - [RADV] - Path of Exile (238960) - Ground decals are missing or corrupted using the Vulkan rendere…
37 - [ADL-S / TGL-U / TGL-H] Pixels missing / flickering when render some app on weston
[all …]
D18.1.1.rst16 ----------------
20 366a35f7530a016f2a8284fb0ee5759eeb216b4d6fa47f0e96b89ad2e43faf96 mesa-18.1.1.tar.gz
21 d3312a2ede5aac14a47476b208b8e3a401367838330197c4588ab8ad420d7781 mesa-18.1.1.tar.xz
24 ------------
29 ---------
34 -------
38 - i965/glk: Add l3 banks count for 2x6 configuration
42 - radv: Fix multiview queries.
43 - radv: Translate logic ops.
44 - radv: Fix up 2_10_10_10 alpha sign.
[all …]
/external/mesa3d/src/util/
Dhalf_float.c2 * Mesa 3-D graphics library
4 * Copyright (C) 1999-2007 Brian Paul All Rights Reserved.
7 * Copyright (C) 2018-2019 Intel Corporation
39 * Convert a 4-byte float to a 2-byte half float.
47 * - It has no sign bias.
49 * - It reproduces the behavior of real hardware: opcode F32TO16 in Intel's
52 * - By reproducing the behavior of the GPU (at least on Intel hardware),
53 * compile-time evaluation of constant packHalf2x16 GLSL expressions will
72 /* m = 0; - already set */ in _mesa_float_to_half_slow()
76 /* denorm -- denorm float maps to 0 half */ in _mesa_float_to_half_slow()
[all …]
Ddouble.h2 * Mesa 3-D graphics library
4 * Copyright (C) 2018-2019 Intel Corporation
56 * first non-fitting bit is set, so we get a tie, but with the least
60 * still ties, but now we lost the tie-up bit, and instead we round to the
83 int f64_to_16_tie_bit = significand_bits64 - significand_bits16 - 1; in _mesa_double_to_float16_rtne()
84 int f32_to_16_tie_bit = significand_bits32 - significand_bits16 - 1; in _mesa_double_to_float16_rtne()
85 uint64_t f64_rounds_up_mask = ((1ULL << f64_to_16_tie_bit) - 1); in _mesa_double_to_float16_rtne()
93 bool f64_has_tie = (src.ui & (1ULL << f64_to_16_tie_bit)) != 0; in _mesa_double_to_float16_rtne()
94 bool f64_rounds_up = (src.ui & f64_rounds_up_mask) != 0; in _mesa_double_to_float16_rtne()
96 dst.ui |= (f64_has_tie && f64_rounds_up); in _mesa_double_to_float16_rtne()
[all …]
/external/mesa3d/docs/_static/specs/
DMESA_texture_const_bandwidth.spec17 Tapani Pälli, Intel
38 can introduce a form of side-channel, in that the bandwidth used for
67 GetTexParameterI{i ui}v, GetTextureParameter{if}v, and
68 GetTextureParameterI{i ui}v when the <pname> parameter is
70 TexParameter{ifx}{v}, TexParameterI{i ui}v, TextureParameter{if}{v},
71 TextureParameterI{i ui}v when the <pname> parameter is
82 Version 1, 2023-9-28 (Rob Clark)
/external/mesa3d/docs/
Dperfetto.rst6 `producers <https://perfetto.dev/docs/concepts/service-model>`__ each with
7 one or more data-sources. Perfetto already provides various producers and
8 data-sources for things like:
10 - CPU scheduling events (``linux.ftrace``)
11 - CPU frequency scaling (``linux.ftrace``)
12 - System calls (``linux.ftrace``)
13 - Process memory utilization (``linux.process_stats``)
21 - pps-producer: A systemwide daemon that can collect global performance
23 - mesa: Per-process producer within mesa to capture render-stage traces
28 .. list-table:: Supported data-sources
[all …]
/external/mesa3d/bin/
Dpick-ui.py2 # Copyright © 2019-2020 Intel Corporation
26 from pick.ui import UI, PALETTE
29 u = UI()
/external/angle/infra/
DREADME.md4 the tree. We scale our pre-commit and post-commit testing to many machines
6 existing work in Chromium. We also run compile-only
11 ## Pre-Commit Testing
13 See the pre-commit try waterfall here:
17 We currently run pre-commit tests on:
19 * Windows 32-bit AMD and Windows 64-bit Intel and NVIDIA GPUs
20 * Linux 64-bit NVIDIA and Intel GPUs
21 * Mac NVIDIA, Intel and AMD GPUs
27 [`https://ci.chromium.org/ui/p/angle/builders/ci/mac-rel/8123/overview`](https://ci.chromium.org/ui…
36 [Swarming]: https://chromium-swarm.appspot.com/
[all …]
/external/mesa3d/
Dmeson_options.txt1 # Copyright © 2017-2019 Intel Corporation
2 # SPDX-License-Identifier: MIT
16 'egl-native-platform',
27 'android-stub',
30 description : 'Build against android-stub',
34 'android-strict',
43 'android-libbacktrace',
56 'dri-drivers-path',
63 'dri-search-path',
67 'separated list. Default: dri-drivers-path.'
[all …]
/external/wpa_supplicant_8/hostapd/
DREADME-WPS1 hostapd and Wi-Fi Protected Setup (WPS)
5 configured and how an external component on an AP (e.g., web UI) is
10 -------------------
12 Wi-Fi Protected Setup (WPS) is a mechanism for easy configuration of a
16 with PIN method and push-button configuration (PBC) being the most
28 - access point: the WLAN access point
29 - Registrar: a device that control a network and can authorize
33 - Enrollee: a device that is being authorized to use the network
40 More information about WPS is available from Wi-Fi Alliance:
41 http://www.wi-fi.org/wifi-protected-setup
[all …]
/external/mesa3d/src/gfxstream/
Dmeson_options.txt2 # Copyright © 2017-2019 Intel Corporation
3 # SPDX-License-Identifier: MIT
17 'egl-native-platform',
28 'android-stub',
31 description : 'Build against android-stub',
35 'android-libbacktrace',
48 'dri-drivers-path',
55 'dri-search-path',
59 'separated list. Default: dri-drivers-path.'
71 'gallium-drivers',
[all …]
/external/mesa3d/.gitlab-ci/build/
Dgitlab-ci.yml2 .build-common:
3 extends: .container+build-rules
6 # Build jobs don't take more than 1-3 minutes. 5-8 min max on a fresh runner
18 - _build/meson-logs/*.txt
19 - _build/meson-logs/strace
20 - shader-db
21 - artifacts
24 .build-linux:
25 extends: .build-common
32 - !reference [default, before_script]
[all …]
/external/autotest/client/site_tests/audio_Aplay/
Daudio_Aplay.py3 # Use of this source code is governed by a BSD-style license that can be
20 # Expected results of 'aplay -v' commands.
27 Sample output from aplay -v:
31 Hardware PCM card 0 'HDA Intel PCH' device 0 subdevice 0
62 '-v', # show verbose details
63 '-D %s' % device_name,
64 '-d %d' % duration,
65 '-c %d' % channel_count,
66 '-r 44100',
67 '-f S16_LE',
[all …]
/external/mesa3d/src/util/tests/
Dhalf_float_test.cpp2 * Copyright © 2021 Intel Corporation
44 uint32_t ui = fui(x); in issignaling() local
45 return (((ui >> 23) & 0xff) == 0xff) && !(ui & (1 << 22)); in issignaling()
50 * (PA-RISC, old MIPS without IEEE-754-2008 support).
68 /* Make sure that our 32-bit float nan test value we're using is a
69 * non-signaling NaN.
86 EXPECT_EQ(fui(func(0x8000)), fui(-0.0f)); in test_half_to_float_limits()
97 /* -inf */ in test_half_to_float_limits()
101 /* Test the optionally HW instruction-using path. */
125 EXPECT_EQ(func(-0.0f), 0x8000); in test_float_to_half_limits()
[all …]
/external/mesa3d/bin/pick/
Dui.py1 # Copyright © 2019-2020 Intel Corporation
21 """Urwid UI for pick script."""
46 def __init__(self, *args, ui: 'UI', **kwargs): argument
48 self.ui = ui
53 def __init__(self, *args, ui: 'UI', **kwargs): argument
55 self.ui = ui
57 def keypress(self, size: int, key: str) -> typing.Optional[str]:
61 asyncio.ensure_future(self.ui.update())
63 self.ui.add()
75 def __init__(self, ui: 'UI', commit: 'core.Commit'): argument
[all …]
/external/aws-sdk-java-v2/.changes/2.15.x/
D2.15.37.json3 "date": "2020-12-01",
9 …ds support for: EBS gp3 volumes; and D3/D3en/R5b/M5zn instances powered by Intel Cascade Lake CPUs"
15 … Amplify Admin UI offers an accessible way to develop app backends and manage app content. We reco…
39 …ersations, both real-time and post-call. The ListRealtimeContactAnalysisSegments API returns a lis…
51 …"description": "S3 adds support for multiple-destination replication, option to sync replica modif…
63 …manage the lifecycle for Kubernetes add-ons for your clusters. This release adds support for the A…
/external/skia/site/docs/dev/testing/
Dskiagold.md1 ---
4 ---
13 - Baselines are managed in Gold outside of Git, but in lockstep with Git
15 - Each commit creates >500k images.
16 - Deviations from the baseline are triaged after a CL lands and images are
21 - We test across a range of dimensions, e.g.:
23 - OS (Windows, Linux, Mac, Android, iOS)
24 - Architectures (Intel, ARM)
25 - Backends (CPU, OpenGL, Vulkan etc.)
26 - etc.
[all …]
/external/autotest/client/cros/power/
Dpower_utils.py3 # Use of this source code is governed by a BSD-style license that can be
35 Intel's processor naming conventions is a mine field of inconsistencies.
40 http://www.intel.com/content/www/us/en/processors/processor-numbers.html
48 if re.search(r'AMD.*[AE][269]-9[0-9][0-9][0-9].*RADEON.*R[245]', cpuinfo):
52 if re.search(r'Intel.*Atom.*[NZ][2-6]', cpuinfo):
54 if re.search(r'Intel.*Celeron.*N2[89][0-9][0-9]', cpuinfo):
56 if re.search(r'Intel.*Celeron.*N3[0-9][0-9][0-9]', cpuinfo):
58 if re.search(r'Intel.*Celeron.*[0-9]{3,4}', cpuinfo):
60 # https://ark.intel.com/products/series/94028/5th-Generation-Intel-Core-M-Processors
61 # https://ark.intel.com/products/series/94025/6th-Generation-Intel-Core-m-Processors
[all …]

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